Semiconductor device

Abstract

According to one embodiment, a semiconductor device is provided with: a base substrate; the shell is arranged on the upper surface of the substrate; a first laminate disposed on an upper surface of the substrate on an inner side of the case; a second laminate disposed on the upper surface of the base substrate so as to be separated from the first laminate; and a flat first conductor having a first portion in contact with the first laminate and a second portion in contact with the second laminate. The first laminated body includes a first insulator, a second conductor provided on an upper surface of the first insulator and in contact with a first portion of the first conductor, and a first semiconductor element electrically connected to the second conductor. The second laminated body includes a second insulator and a third conductor provided on an upper surface of the second insulator and in contact with a second portion of the first conductor, and does not include a semiconductor element.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device. Background Art

[0002] A power module is known as a semiconductor device that realizes high output. A power module is configured as a package in which a plurality of power semiconductors are integrated.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2016 / 056532

[0006] Patent Document 2: Japanese Patent Application Publication No. 2016-076563

[0007] Patent Document 3: Japanese Patent Application Publication No. 2010-035346 Summary of the invention

[0008] Problems to be solved by the invention

[0009] Suppresses temperature rise.

[0010] Means for solving problems

[0011] The semiconductor device of the embodiment comprises: a base substrate; a housing provided on the upper surface of the base substrate; a first stack provided on the inner side of the housing on the upper surface of the base substrate; a second stack provided on the upper surface of the base substrate separately from the first stack; and a flat first conductor having a first portion in contact with the first stack and a second portion in contact with the second stack. The first stack includes a first insulator, a second conductor provided on the upper surface of the first insulator and in contact with the first portion of the first conductor, and a first semiconductor element electrically connected to the second conductor. The second stack includes a second insulator and a third conductor provided on the upper surface of the second insulator and in contact with the second portion of the first conductor, and the second stack does not include a semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a perspective view showing the external structure of the semiconductor device according to the first embodiment.

[0013] Figure 2 This is a circuit diagram showing an example of a circuit configuration of the semiconductor device according to the first embodiment.

[0014] Figure 3 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the first embodiment.

[0015] Figure 4 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the first embodiment.

[0016] Figure 5 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the second embodiment.

[0017] Figure 6 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the second embodiment.

[0018] Figure 7 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the third embodiment.

[0019] Figure 8 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the third embodiment.

[0020] Fig. 9 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the fourth embodiment.

[0021] Fig.10 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fourth embodiment.

[0022] Fig.11 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the fifth embodiment.

[0023] Fig.12 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fifth embodiment.

[0024] Fig.13 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a first modification.

[0025] Fig.14 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a second modification.

[0026] Fig.15 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third modification. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments will be described with reference to the drawings. Dimensions and ratios in the drawings are not necessarily the same as those in reality.

[0028] In the following description, components having substantially the same function and structure are denoted by the same reference numerals. In order to distinguish components having the same structure from each other, different letters or numbers may be added to the end of the same reference numerals.

[0029] 1. First Implementation

[0030] A semiconductor device according to a first embodiment will be described.

[0031] The semiconductor device of the first embodiment is a power module. The semiconductor device of the first embodiment is applied to, for example, a power conversion device for a railway vehicle or a power unit of industrial equipment or the like.

[0032] The structure of the semiconductor device according to the first embodiment will be described.

[0033] First, the external structure of the semiconductor device according to the first embodiment will be described.

[0034] Figure 1 1 is a perspective view showing an example of the external structure of the semiconductor device of the first embodiment. As the external structure, the semiconductor device 1 includes a base substrate BS, a housing CS, and a cover CV. The base substrate BS, the housing CS, and the cover CV form a container of the semiconductor device 1. In the container of the semiconductor device 1, a circuit structure (not shown) including a semiconductor element is accommodated.

[0035] The base substrate BS is a support body corresponding to the lower part of the container of the semiconductor device 1. The base substrate BS has a flat plate shape and is fixed to a device (not shown) outside the semiconductor device 1 via screw holes formed at four corners, for example.

[0036] A case CS is provided on the upper surface of the base substrate BS. The case CS is an insulator having a square tube shape. The case CS corresponds to the side of the container of the semiconductor device 1. The case CS is fixed to the base substrate BS.

[0037] A cover CV is provided on the upper surface of the case CS. The cover CV is an insulator having a flat plate shape. The cover CV corresponds to the upper portion of the container of the semiconductor device 1. The cover CV is fixed relative to the case CS.

[0038] By assembling the base substrate BS, the case CS, and the cover CV as described above, a space for arranging the circuit structure is formed inside the container.

[0039] In addition, the semiconductor device 1 further includes a plurality of terminals T (T_P, T_N, T_AC, and T_S).

[0040] The terminals T_P, T_N, T_AC, and T_S are ends of bus bars (not shown) that electrically connect devices outside the semiconductor device 1 to the internal circuit structure. Figure 1In the example of FIG. 1 , two terminals T_P, two terminals T_N, three terminals T_AC, and eight terminals T_S are shown. In addition, the number of terminals T_P, T_N, T_AC, and T_S is not limited to Figure 1 Examples can be designed to be any number.

[0041] The two terminals T_P are input terminals. The two terminals T_P have a P (Positive) polarity. The two terminals T_P are electrically connected to each other. The two terminals T_P are arranged on one of two opposing short sides of the semiconductor device 1 .

[0042] The two terminals T_N are input terminals. The two terminals T_N have N (Negative) polarity. The two terminals T_N are electrically connected to each other. The two terminals T_N are arranged on one of the two opposing short sides of the semiconductor device 1 in parallel with the two terminals T_P.

[0043] The three terminals T_AC are output terminals. The three terminals T_AC are also called AC (Alternating Current) terminals. The three terminals T_AC are electrically connected to each other. The three terminals T_AC are arranged on the other of the two opposing short sides of the semiconductor device 1 .

[0044] The eight terminals T_S are control terminals and monitoring terminals. The control terminal is, for example, a terminal for controlling whether to drive a semiconductor element included in the circuit structure of the semiconductor device 1. The monitoring terminal is, for example, a terminal for monitoring the electrical characteristics of the circuit structure of the semiconductor device 1. The eight terminals T_S are arranged four each on two opposing long sides of the semiconductor device 1.

[0045] Next, the circuit configuration of the semiconductor device according to the first embodiment will be described.

[0046] Figure 2 FIG. 1 is a circuit diagram showing an example of a circuit structure of a semiconductor device according to the first embodiment. Figure 2 As shown, the plurality of terminals T_S include terminals T_S1, T_S2, T_S3 and T_S4. Figure 2 In the example of FIG. 1 , a case is shown in which the semiconductor device 1 includes transistors TR_up and TR_low as electrical elements included in the internal circuit structure.

[0047] The transistors TR_up and TR_low are, for example, insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistor) or field effect transistors (MOSFET: Metal-Oxide-Silicon Field-Effect Transistor) using silicon carbide (SiC). The transistors TR_up and TR_low are connected in series. Figure 2 In the example of FIG. 1 , one transistor TR_up and one transistor TR_low are shown, but the present invention is not limited to this. For example, each of the transistors TR_up and TR_low may be composed of a plurality of transistors connected in parallel to each other.

[0048] Specifically, the transistor TR_up has a drain terminal connected to the terminal T_P, a source terminal connected to the drain terminal of the transistor TR_low, and a gate terminal connected to the terminal T_S1. The transistor TR_low has a drain terminal connected to the source terminal of the transistor TR_up, a source terminal connected to the terminal T_N, and a gate terminal connected to the terminal T_S2. The source terminal of the transistor TR_up and the drain terminal of the transistor TR_low are commonly connected to the terminal T_AC, the terminal T_S3, and the terminal T_S4.

[0049] Terminals T_S1 and T_S2 correspond to two different control terminals of terminal T_S. Terminals T_S3 and T_S4 correspond to two different monitoring terminals of terminal T_S. Terminal T_S3 is located closer to transistor TR_up than terminal T_AC. Terminal T_S4 is located closer to transistor TR_low than terminal T_3.

[0050] With the above-described configuration, the semiconductor element inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1 .

[0051] Next, a cross-sectional structure of the semiconductor device according to the first embodiment will be described.

[0052] Figure 3 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the first embodiment. Figure 4 1 is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device of the first embodiment. The first example and the second example are cross-sectional views of the semiconductor device 1 along different cross sections. Specifically, in the first example, an example of the cross-sectional structure of the semiconductor device 1 in which the bus bar functioning as the terminal T and the transistor TR are provided on the same conductor is shown. In the second example, an example of the cross-sectional structure of the semiconductor device 1 in which the bus bar functioning as the terminal T and the transistor TR are provided on different conductors is shown.

[0053] The semiconductor device 1 includes conductors 10, 12, 13, 15, 17, 18, and 19, insulators 11, 14, and 20, and a semiconductor element 16. The conductor 12 includes conductors 12a, 12b, and 12c. The conductor 13 includes conductors 13a, 13b, and 13c. The insulator 14 includes insulators 14a, 14b, and 14c. The conductor 15a includes conductors 15a-1, 15a-2, 15b, and 15c. The conductor 17 includes conductors 17-1 and 17-2. The conductor 18 includes conductors 18-1 and 18-2.

[0054] The conductor 10 corresponds to the base substrate BS and includes, for example, copper (Cu) or ceramics.

[0055] An insulator 11 corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11 includes, for example, polyphenylene sulfide (PPC: Poly-Phenylene Sulfide).

[0056] The three laminated bodies LS1 , LS2 , and LS3 are provided separately from each other in a region (inside) surrounded by the insulator 11 on the upper surface of the conductor 10 .

[0057] like Figure 3 and Figure 4 As shown, the laminate LS1 includes a conductor 12a, a conductor 13a, an insulator 14a, conductors 15a-1, 15a-2 and a semiconductor element 16. The conductor 12a is provided on the upper surface of the conductor 10. The conductor 12a includes, for example, solder. The conductor 13a is provided on the upper surface of the conductor 12a. The conductor 13a includes, for example, copper (Cu). The insulator 14a is provided on the upper surface of the conductor 13a. The insulator 14a is, for example, an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductors 15a-1 and 15a-2 are provided separately from each other on the upper surface of the insulator 14a. The conductors 15a-1 and 15a-2 include, for example, copper (Cu). The semiconductor element 16 is provided on the upper surface of the conductor 15a-1. That is, the insulator 14a is an insulating substrate on which the semiconductor element 16 is mounted. The semiconductor element 16 is a chip including a transistor TR (TR_up or TR_low). The upper surface of the semiconductor element 16 and the upper surface of the conductor 15a-2 are electrically connected via a conductor 19. The conductor 19 is, for example, a bonding wire.

[0058] like Figure 3As shown, the stacked body LS2 includes a conductor 12b, a conductor 13b, an insulator 14b and a conductor 15b. The conductor 12b is arranged on the upper surface of the conductor 10. The conductor 12b includes, for example, solder. The conductor 13b is arranged on the upper surface of the conductor 12b. The conductor 13b includes, for example, copper (Cu). The insulator 14b is arranged on the upper surface of the conductor 13b. The insulator 14b includes, for example, insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15b is arranged on the upper surface of the insulator 14b. The conductor 15b includes, for example, copper (Cu). In addition, the semiconductor element 16 is not arranged above the insulator 14b. That is, all the semiconductor elements 16 possessed by the semiconductor device 1 are not included in the stacked body LS2.

[0059] like Figure 4 As shown, the stacked body LS3 includes a conductor 12c, a conductor 13c, an insulator 14c and a conductor 15c. The conductor 12c is arranged on the upper surface of the conductor 10. The conductor 12c includes, for example, solder. The conductor 13c is arranged on the upper surface of the conductor 12c. The conductor 13c includes, for example, copper (Cu). The insulator 14c is arranged on the upper surface of the conductor 13c. The insulator 14c is, for example, an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15c is arranged on the upper surface of the insulator 14c. The conductor 15c includes, for example, copper (Cu). In addition, the semiconductor element 16 is not arranged above the insulator 14c. That is, all the semiconductor elements 16 possessed by the semiconductor device 1 are not included in the stacked body LS3.

[0060] The laminated bodies LS2 and LS3 are arranged between the laminated body LS1 and the insulator 11. That is, the laminated bodies LS2 and LS3 are arranged on the insulator 11 side (outside) of the laminated body LS1 when viewed in the up-down direction.

[0061] The conductors 17-1, 17-2, 18-1 and 18-2 are, for example, flat conductive materials containing copper (Cu). The conductors 17-1, 17-2, 18-1 and 18-2 are formed, for example, by bending a flat plate having a substantially uniform thickness. The thickness of the conductors 17-1, 17-2, 18-1 and 18-2 is designed to be, for example, within a range of 0.4 mm or more and 4.0 mm or less.

[0062] The conductor 17-1 has a first end joined to the upper surface of the conductor 15a-1 and a second end joined to the upper surface of the conductor 15b. The conductor 18-1 has a first end joined to the upper surface of the first end of the conductor 17-1 and a second end arranged on the upper surface of the insulator 11 and functioning as a terminal T. The first end of the conductor 17-1 is electrically connected to the semiconductor element 16 via the conductor 15a-1, and is electrically connected to the terminal T via the conductor 18-1. The second end of the conductor 17-1 is connected to the insulator 14b via the conductor 15b. Thus, the conductor 17-1 functions as a heat dissipation path for releasing heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 14b.

[0063] The conductor 17-2 has a first end joined to the upper surface of the conductor 15a-2 and a second end joined to the upper surface of the conductor 15c. The conductor 18-2 has a first end joined to the upper surface of the first end of the conductor 17-2 and a second end arranged on the upper surface of the insulator 11 and functioning as a terminal T. The first end of the conductor 17-2 is electrically connected to the semiconductor element 16 via the conductors 15a-2 and 19, and is electrically connected to the terminal T via the conductor 18-2. The second end of the conductor 17-2 is connected to the insulator 14c via the conductor 15c. Thus, the conductor 17-2 functions as a heat dissipation path for releasing heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 14c.

[0064] The first end of the conductor 17-1 and the conductor 15a-1, the second end of the conductor 17-1 and the conductor 15b, the first end of the conductor 17-2 and the conductor 15a-2, and the second end of the conductor 17-2 and the conductor 15c are bonded together, for example, by ultrasonic bonding. Similarly, the first end of the conductor 18-1 and the first end of the conductor 17-1, and the first end of the conductor 18-2 and the first end of the conductor 17-2 are bonded together, for example, by ultrasonic bonding. In this case, an indentation having fine concave and convex shapes, such as a knurling shape transferred, is formed on the upper surfaces of the first end and the second end of the conductor 17-1, the first end and the second end of the conductor 17-2, the first end of the conductor 18-1, and the first end of the conductor 18-2.

[0065] The second end of the conductor 18-1 and the second end of the conductor 18-2 are each connected to an external device via a threaded hole (not shown). In addition, the type of terminal T corresponding to the second end of the conductor 18-1 and the second end of the conductor 18-2 can be any one of the terminals T_P, T_N, T_AC and T_S. In the case where the semiconductor element 16 is a transistor TR_up, the second end of the conductor 18-1 and the second end of the conductor 18-2 can be the terminal T_P and the terminal T_AC, T_S1 or T_S3, respectively. In the case where the semiconductor element 16 is a transistor TR_low, the second end of the conductor 18-1 and the second end of the conductor 18-2 can be the terminal T_AC or T_S4 and the terminal T_N or T_S2, respectively.

[0066] In addition, the width of the portion between the first end and the second end of the conductor 17-1 in the paper depth direction is preferably designed to be greater than the width of the portion between the first end and the second end of the conductor 18-1 in the paper depth direction, for example, by 0.5 mm or more. In this case, when the inside of the semiconductor device 1 is viewed from above, a portion of the conductor 17-1 is not blocked by the conductor 18-1 and can be seen.

[0067] Similarly, the width of the portion between the first end and the second end of the conductor 17-2 in the paper depth direction is preferably designed to be greater than the width of the portion between the first end and the second end of the conductor 18-2 in the paper depth direction, for example, by 0.5 mm or more. In this case, when the inside of the semiconductor device 1 is viewed from above, a portion of the conductor 17-2 is not blocked by the conductor 18-2 and can be seen.

[0068] The internal structure of the semiconductor device 1 configured as described above is sealed by the insulator 20 except for the portions of the conductors 18-1 and 18-2 functioning as the terminals T. The insulator 20 has a function of physically and electrically protecting the internal structure of the semiconductor device 1 from the outside of the semiconductor device 1.

[0069] According to the first embodiment, it is possible to suppress a temperature increase in the semiconductor device 1. This effect will be described below.

[0070] Insulators 14a, 14b and 14c are provided on the upper surface of the conductor 10 separately from each other. Conductors 15a-1 and 15a-2 are provided on the upper surface of the insulator 14a. Conductors 15b and 15c are provided on the upper surfaces of the insulators 14b and 14c, respectively. Conductor 17-1 has a first end connected to conductor 15a-1 and a second end connected to conductor 15b. Conductor 17-2 has a first end connected to conductor 15a-2 and a second end connected to conductor 15c. Semiconductor element 16 is electrically connected to conductors 17-1 and 17-2. Thus, conductors 17-1 and 17-2 can form heat dissipation paths for releasing heat generated by semiconductor element 16 to conductor 10 via laminated bodies LS2 and LS3, respectively. Therefore, it is possible to suppress the temperature rise of laminated body LS1 including semiconductor element 16.

[0071] In addition, the conductor 18-1 has a first end connected to the first end of the conductor 17-1 and a second end located on the upper surface of the insulator 11 and functioning as a terminal T. The conductor 18-2 has a first end connected to the first end of the conductor 17-2 and a second end located on the upper surface of the insulator 11 and functioning as a terminal T. Thus, the conductors 17-1 and 17-2 can form heat dissipation paths that release heat flowing into the terminal T to the conductor 10 via the laminated bodies LS2 and LS3, respectively. Therefore, the temperature rise of the terminal T can be suppressed.

[0072] In addition, the appearance of the semiconductor device 1 is standardized for the purpose of improving user convenience. Therefore, the semiconductor device 1 is required to increase the allowable current to a limit within the range of the standard. The higher the allowable current, the more heat flows into the stacked body LS1 including the semiconductor element 16 and the terminal T.

[0073] According to the first embodiment, the stack LS1 and the terminal T are connected to the stack LS2 and LS3 via the conductors 17-1 and 17-2, respectively. The stack LS2 and LS3 do not include the semiconductor element 16. Therefore, the stack LS2 and LS3 themselves do not become a heat source, and can function as a heat dissipation mechanism to suppress the temperature rise of the stack LS1 and the terminal T.

[0074] In addition, the conductors 17-1, 17-2, 18-1 and 18-2 contain copper (Cu) as an equivalent material. Thus, the mismatch of the thermal expansion coefficient of the joint portion due to the temperature rise is suppressed. In addition, the conductors 17-1, 17-2, 18-1 and 18-2 are ultrasonically joined. Thus, compared with the case of connection via solder, for example, it is possible to suppress the strength degradation of the joint portion accompanied by the temperature rise.

[0075] 2. Second Implementation

[0076] Next, a semiconductor device according to a second embodiment will be described.

[0077] The second embodiment is different from the first embodiment in that the busbars forming the heat dissipation path are integrally formed with the busbars functioning as the terminals T. Hereinafter, the structures different from the first embodiment will be mainly described. The description of the structures equivalent to the first embodiment will be appropriately omitted.

[0078] Figure 5 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the second embodiment. Figure 6 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the second embodiment. Figure 5 and Figure 6 Respectively with the first embodiment Figure 3 and Figure 4 correspond.

[0079] The semiconductor device 1A of the second embodiment includes conductors 18A-1 and 18A-2 instead of the conductors 17-1 and 18-1 and the conductors 17-2 and 18-2. The structure of the semiconductor device 1A other than the conductors 18A-1 and 18A-2 is the same as the corresponding structure of the semiconductor device 1 of the first embodiment.

[0080] Conductors 18A-1 and 18A-2 are, for example, flat conductive materials containing copper (Cu). Conductors 18A-1 and 18A-2 are formed, for example, by bending a flat plate having a substantially uniform thickness. The thickness of conductors 18A-1 and 18A-2 is designed to be within a range of 0.4 mm to 4.0 mm, for example.

[0081] The conductor 18A-1 has a first end joined to the upper surface of the conductor 15a-1, a second end located on the upper surface of the insulator 11 and functioning as a terminal T, and a central portion located between the first end and the second end and joined to the upper surface of the conductor 15b. Thus, the conductor 18A-1 functions as a heat dissipation path for releasing heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 14b.

[0082] The conductor 18A-2 has a first end joined to the upper surface of the conductor 15a-2, a second end located on the upper surface of the insulator 11 and functioning as a terminal T, and a central portion located between the first end and the second end and joined to the upper surface of the conductor 15c. Thus, the conductor 18A-2 functions as a heat dissipation path for releasing heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 14c.

[0083] The first end of the conductor 18A-1 and the conductor 15a-1, and the central portion of the conductor 18A-1 and the conductor 15b are bonded together by, for example, ultrasonic bonding. Similarly, the first end of the conductor 18A-2 and the conductor 15a-2, and the central portion of the conductor 18A-2 and the conductor 15c are bonded together by, for example, ultrasonic bonding. In this case, an indentation having fine concave and convex shapes, as if the knurled shape is transferred, is formed on the upper surface of each of the first end and the central portion of the conductor 18A-1 and the first end and the central portion of the conductor 18A-2.

[0084] The internal structure of the semiconductor device 1 configured as described above is sealed by the insulator 20 except for the portions functioning as the terminals T in the conductors 18A- 1 and 18A- 2 .

[0085] According to the second embodiment, the conductor 18A-1 has a first end connected to the conductor 15a-1, a second end located on the upper surface of the insulator 11 and functioning as a terminal T, and a central portion located between the first end and the second end and connected to the conductor 15b. The conductor 18A-2 has a first end connected to the conductor 15a-2, a second end located on the upper surface of the insulator 11 and functioning as a terminal T, and a central portion located between the first end and the second end and connected to the conductor 15c. Thus, the conductors 18A-1 and 18A-2 can function as a heat dissipation path for releasing heat flowing into the terminal T and the laminate LS1 to the conductor 10 via the laminates LS2 and LS3, and can also function as a current path between the terminal T and the semiconductor element 16.

[0086] 3. Third Implementation

[0087] Next, a semiconductor device according to a third embodiment will be described.

[0088] The third embodiment is different from the first and second embodiments in that a heat dissipation path is formed inside the housing CS. Hereinafter, the structures different from the first and second embodiments will be mainly described. The description of the structures equivalent to the first and second embodiments will be appropriately omitted.

[0089] Figure 7 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the third embodiment. Figure 8 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the third embodiment. Figure 7 and Figure 8 Respectively with the first embodiment Figure 3 and Figure 4 correspond.

[0090] The semiconductor device 1B of the third embodiment includes conductors 17B-1 and 17B-2 instead of the conductors 17-1 and 18-1 and the conductors 17-2 and 18-2. In addition, the semiconductor device 1B of the third embodiment includes insulators 11B, stacked bodies LS4 and stacked bodies LS5 instead of the insulators 11, stacked bodies LS2 and stacked bodies LS3. The structure of the semiconductor device 1B other than the conductors 17B-1 and 17B-2, the insulator 11B, the stacked bodies LS4 and the stacked bodies LS5 is equivalent to the corresponding structure of the semiconductor device 1 of the first embodiment.

[0091] An insulator 11B corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11B is made of, for example, PPC. A plurality of spaces penetrating from the lower end to the upper end are formed in a portion of the insulator 11B.

[0092] The conductor 17B- 1 has a first end joined to the upper surface of the conductor 15 a - 1 and a second end located on the upper surface of the insulator 11B and functioning as a terminal T.

[0093] The conductor 17B- 2 has a first end joined to the upper surface of the conductor 15 a - 2 and a second end located on the upper surface of the insulator 11B and functioning as a terminal T.

[0094] The internal structure of the semiconductor device 1B configured as described above is sealed by the insulator 20 except for the portions functioning as the terminals T in the conductors 17B- 1 and 17B- 2 .

[0095] In addition, if Figure 7 As shown, a laminate LS4 is provided in the internal space of the insulator 11B formed below the conductor 17B-1. The laminate LS4 includes an insulator 21b and a conductor 22b. The insulator 21b is, for example, a flat insulating sheet and includes a material different from that of an insulating substrate such as the insulator 14a. The conductor 22b includes, for example, copper (Cu).

[0096] The upper surface of the conductor 22b is in contact with the lower surface of the second end of the conductor 17B-1 that functions as the terminal T. The lower surface of the conductor 22b is in contact with the upper surface of the insulator 21b. The lower surface of the insulator 21b is in contact with the upper surface of the conductor 10. The insulator 21b electrically insulates the conductor 10 from the conductor 22b. Thus, the conductor 17B-1 functions as a heat dissipation path that releases heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the conductor 22b and the insulator 21b.

[0097] like Figure 8As shown, a stack LS5 is provided in the internal space of the insulator 11B formed below the conductor 17B-2. The stack LS5 includes an insulator 21c and a conductor 22c. The conductor 22c is provided separately from the conductor 22b via the insulator 11B. Thus, the conductors 22b and 22c are electrically insulated. The insulator 21c is, for example, a flat insulating sheet, and includes a material different from an insulating substrate such as the insulator 14a. The conductor 22c includes, for example, copper (Cu).

[0098] The upper surface of the conductor 22c is in contact with the lower surface of the second end of the conductor 17B-2 that functions as the terminal T. The lower surface of the conductor 22c is in contact with the upper surface of the insulator 21c. The lower surface of the insulator 21c is in contact with the upper surface of the conductor 10. The insulator 21c electrically insulates the conductor 10 from the conductor 22c. Thus, the conductor 17B-2 functions as a heat dissipation path that releases heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the conductor 22c and the insulator 21c.

[0099] In addition, the first end of the conductor 17B-1 and the conductor 15a-1, the second end of the conductor 17B-1 and the conductor 22b, the first end of the conductor 17B-2 and the conductor 15a-2, and the second end of the conductor 17B-2 and the conductor 22c are joined by, for example, ultrasonic joining. In this case, an indentation having fine concave and convex shapes, as if the knurled shape is transferred, is formed on the upper surface of each of the first end and the second end of the conductor 17B-1 and the first end and the second end of the conductor 17B-2.

[0100] According to the third embodiment, the insulator 21b and the conductor 22b and the insulator 21c and the conductor 22c are provided in the space inside the insulator 11B. The conductor 17B-1 has a first end connected to the conductor 15a-1, and a second end connected to the conductor 22b and located on the upper surface of the insulator 11B and functioning as a terminal T. The conductor 17B-2 has a first end connected to the conductor 15a-2, and a second end connected to the conductor 22c and located on the upper surface of the insulator 11B and functioning as a terminal T. Thus, the conductors 17B-1 and 17B-2 can function as a heat dissipation path for releasing heat flowing into the terminal T and the laminated body LS1 to the conductor 10 via the conductors 22b and 22c, and can also function as a current path between the terminal T and the semiconductor element 16. Furthermore, since the heat dissipation path can be formed in the space inside the insulator 11B, the constraints on the layout of the internal structure of the semiconductor device 1B can be relaxed compared to the case where the heat dissipation path is formed inside the insulator 11B.

[0101] 4. Fourth Implementation

[0102] Next, a semiconductor device according to a fourth embodiment will be described.

[0103] The fourth embodiment is different from the third embodiment in that the conductor provided inside the housing CS and the busbar electrically connecting the semiconductor element 16 and the terminal T are integrally formed. Hereinafter, the structure different from the third embodiment will be mainly described. The description of the structure equivalent to the third embodiment will be appropriately omitted.

[0104] Fig. 9 It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the fourth embodiment. Fig.10 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fourth embodiment. Fig. 9 and Fig.10 Respectively with the third embodiment Figure 7 and Figure 8 correspond.

[0105] The semiconductor device 1C of the fourth embodiment includes an insulator 11C, a conductor 23b, and a conductor 23c instead of the insulator 11B, the conductors 17B-1 and 22b, and the conductors 17B-2 and 22c. The structure of the semiconductor device 1C other than the insulator 11C, the conductor 23b, and the conductor 23c is equivalent to the corresponding structure of the semiconductor device 1B of the third embodiment.

[0106] An insulator 11C corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11C includes, for example, PPC. A plurality of spaces penetrating from the lower end to the upper end are formed in a portion of the insulator 11C. Each space is connected to the internal space of the semiconductor device 1C via a hole formed on the inner side surface of the insulator 11C.

[0107] like Fig. 9 As shown, the conductor 23b includes a busbar portion located in the internal space of the semiconductor device 1C, a heat dissipation portion located inside the insulator 11C, and a terminal portion located on the upper surface of the insulator 11C. The busbar portion of the conductor 23b has a first end joined to the upper surface of the conductor 15a-1 and a second end connected to the heat dissipation portion of the conductor 23b via a hole formed on the side surface of the inner side of the insulator 11C. The heat dissipation portion of the conductor 23b has a lower surface that is in contact with the upper surface of the insulator 21b. The terminal portion of the conductor 23b is located at the upper part of the heat dissipation portion of the conductor 23b and functions as a terminal T. As a result, the conductor 23b functions as a heat dissipation path that releases the heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 21b.

[0108] like Fig.10As shown, the conductor 23c includes a busbar portion located in the internal space of the semiconductor device 1C, a heat dissipation portion located inside the insulator 11C, and a terminal portion located on the upper surface of the insulator 11C. The busbar portion of the conductor 23c has a first end joined to the upper surface of the conductor 15a-2 and a second end connected to the heat dissipation portion of the conductor 23c via a hole formed on the side surface of the inner side of the insulator 11C. The heat dissipation portion of the conductor 23c has a lower surface in contact with the upper surface of the insulator 21c. The terminal portion of the conductor 23c is located at the upper part of the heat dissipation portion of the conductor 23c and functions as a terminal T. As a result, the conductor 23c functions as a heat dissipation path for releasing the heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the insulator 21c.

[0109] In addition, the first end of the busbar portion of the conductor 23b and the conductor 15a-1 and the first end of the busbar portion of the conductor 23c and the conductor 15a-2 are joined by, for example, ultrasonic joining. In this case, an indentation having fine concave and convex shapes, such as a knurled shape transferred, is formed on the upper surface of each of the first end of the busbar portion of the conductor 23b and the first end of the busbar portion of the conductor 23c.

[0110] According to the fourth embodiment, the conductors 23b and 23c each include a heat dissipation portion, a busbar portion, and a terminal portion. The heat dissipation portion of the conductor 23b and the heat dissipation portion of the conductor 23c are provided in a space within the insulator 11C. The busbar portion of the conductor 23b has a first end connected to the conductor 15a-1 and a second end connected to the heat dissipation portion of the conductor 23b. The busbar portion of the conductor 23c has a first end connected to the conductor 15a-2 and a second end connected to the heat dissipation portion of the conductor 23c. The terminal portion of the conductor 23b and the terminal portion of the conductor 23c are located on the upper surface of the insulator 11C and function as a terminal T. Thus, the conductors 23b and 23c can function as a heat dissipation path for releasing the heat flowing into the terminal T and the laminate LS1 to the conductor 10 via the insulators 21b and 21c, and can also function as a current path between the terminal T and the semiconductor element 16.

[0111] 5. Fifth Implementation

[0112] Next, a semiconductor device according to a fifth embodiment will be described.

[0113] The fifth embodiment is different from the fourth embodiment in that a laminate including an insulating substrate is formed inside the casing CS. Hereinafter, the structure different from the fourth embodiment will be mainly described. The description of the structure equivalent to the fourth embodiment will be appropriately omitted.

[0114] Fig.11It is a cross-sectional view showing a first example of the cross-sectional structure of the semiconductor device according to the fifth embodiment. Fig.12 It is a cross-sectional view showing a second example of the cross-sectional structure of the semiconductor device according to the fifth embodiment. Fig.11 and Fig.12 Respectively with the fourth embodiment Fig. 9 and Fig.10 correspond.

[0115] The semiconductor device 1D of the fifth embodiment includes an insulator 11D, a stacked body LS6, and a stacked body LS7 instead of the insulator 11C, the stacked body LS4, and the stacked body LS5. The structure of the semiconductor device 1D other than the insulator 11D, the stacked body LS6, and the stacked body LS7 is equivalent to the corresponding structure of the semiconductor device 1C of the fourth embodiment.

[0116] An insulator 11D corresponding to the case CS is provided on the upper surface of the conductor 10. The insulator 11D includes, for example, PPC. A plurality of spaces penetrating from the lower end to the upper end are formed in a portion of the insulator 11D. Each space is connected to the internal space of the semiconductor device 1D via a hole formed on the inner side surface of the insulator 11D.

[0117] like Fig.11 As shown, the laminate LS6 includes a conductor 12d, a conductor 13d, an insulator 14d, a conductor 15d, and a conductor 23d. The conductor 12d is arranged inside the insulator 11D on the upper surface of the conductor 10. The conductor 12d includes, for example, solder. The conductor 13d is arranged on the upper surface of the conductor 12d. The conductor 13d includes, for example, copper (Cu). The insulator 14d is arranged on the upper surface of the conductor 13d. The insulator 14d is, for example, an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15d is arranged on the upper surface of the insulator 14d. The conductor 15d includes, for example, copper (Cu).

[0118] The conductor 23d includes a busbar portion located in the internal space of the semiconductor device 1D, a heat dissipation portion located inside the insulator 11D, and a terminal portion located on the upper surface of the insulator 11D. The busbar portion of the conductor 23d has a first end joined to the upper surface of the conductor 15a-1 and a second end connected to the heat dissipation portion of the conductor 23d via a hole formed on the side surface of the inner side of the insulator 11D. The heat dissipation portion of the conductor 23d has a lower surface connected to the upper surface of the conductor 15d. The terminal portion of the conductor 23d is located at the upper part of the heat dissipation portion of the conductor 23d and functions as a terminal T. Thus, the conductor 23d functions as a heat dissipation path for releasing the heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the laminate LS4.

[0119] like Fig.12 As shown, the laminate LS7 includes a conductor 12e, a conductor 13e, an insulator 14e, a conductor 15e, and a conductor 23e. The conductor 12e is provided inside the insulator 11D on the upper surface of the conductor 10. The conductor 12e includes, for example, solder. The conductor 13e is provided on the upper surface of the conductor 12e. The conductor 13e includes, for example, copper (Cu). The insulator 14e is provided on the upper surface of the conductor 13e. The insulator 14e is, for example, an insulating substrate including insulating ceramics such as aluminum nitride (AlN) and silicon nitride (SiN). The conductor 15e is provided on the upper surface of the insulator 14e. The conductor 15e includes, for example, copper (Cu).

[0120] The conductor 23e includes a busbar portion located in the internal space of the semiconductor device 1D, a heat dissipation portion located inside the insulator 11D, and a terminal portion located on the upper surface of the insulator 11D. The busbar portion of the conductor 23e has a first end joined to the upper surface of the conductor 15a-2 and a second end connected to the heat dissipation portion of the conductor 23e via a hole formed on the side surface of the inner side of the insulator 11D. The heat dissipation portion of the conductor 23e has a lower surface connected to the upper surface of the conductor 15e. The terminal portion of the conductor 23e is located at the upper part of the heat dissipation portion of the conductor 23e and functions as a terminal T. Thus, the conductor 23e functions as a heat dissipation path for releasing the heat transferred from the semiconductor element 16 to the insulator 14a and the terminal T to the conductor 10 via the laminate LS5.

[0121] According to the fifth embodiment, the conductor 12d contains solder, and the laminated body LS6 containing the insulator 14d is joined to the conductor 10 in the space inside the insulator 11D. The conductor 12e contains solder, and the laminated body LS7 containing the insulator 14e is joined to the conductor 10 inside the insulator 11D. Thus, the bonding strength between the laminated bodies LS6 and LS7 and the conductor 10 can be improved.

[0122] In addition, the conductors 23d and 23e each include a heat dissipation portion, a busbar portion, and a terminal portion. The heat dissipation portion of the conductor 23d and the heat dissipation portion of the conductor 23e are arranged in the space inside the insulator 11D. The busbar portion of the conductor 23d has a first end connected to the conductor 15a-1 and a second end connected to the heat dissipation portion of the conductor 23d. The busbar portion of the conductor 23e has a first end connected to the conductor 15a-2 and a second end connected to the heat dissipation portion of the conductor 23e. The terminal portion of the conductor 23d and the terminal portion of the conductor 23e are located on the upper surface of the insulator 11D and function as a terminal T. Thus, the conductors 23d and 23e can function as a heat dissipation path for releasing the heat flowing into the terminal T and the laminated body LS1 to the conductor 10 via the laminated bodies LS6 and LS7, and can also function as a current path between the terminal T and the semiconductor element 16.

[0123] 6. Modifications, etc.

[0124] In addition, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment are not limited to the above-mentioned examples, and various modifications can be applied.

[0125] For example, in the first, fourth, and fifth embodiments described above, the heat dissipation path suppresses the temperature rise of the stack LS1 and the terminal T at the same time, but the present invention is not limited thereto. The heat dissipation path for suppressing the temperature rise of the stack LS1 may be provided separately from the heat dissipation path for suppressing the temperature rise of the terminal T.

[0126] Fig.13 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a first modification. Fig.13 Compared with the first embodiment Figure 3 correspond.

[0127] like Fig.13 As shown, in the semiconductor device 1' of the first modification, the conductor 17-1 may be provided separately from the conductor 18-1. In this case, the conductor 17-1 and the stacked body LS2 connected to the conductor 17-1 mainly contribute to suppressing the temperature rise of the stacked body LS1.

[0128] Fig.14 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a second modification. Fig.14 Compared with the fourth embodiment Fig. 9 correspond.

[0129] like Fig.14 As shown, in the semiconductor device 1C' of the second modification, the conductor 23b' may have a busbar portion and a heat dissipation portion but no terminal portion. In this case, the conductor 23b' and the insulator 21b connected to the conductor 23b' mainly contribute to suppressing the temperature rise of the stack LS1.

[0130] Fig.15 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third modification. Fig.15 Compared with the fifth embodiment Fig.11 correspond.

[0131] like Fig.15 As shown, in the semiconductor device 1D' of the third modification, the conductor 23d' may have a busbar portion and a heat dissipation portion but no terminal portion. In this case, the conductor 23d' and the stack LS6 connected to the conductor 23d' mainly contribute to suppressing the temperature rise of the stack LS1.

[0132] In the first, second, third, fourth and fifth embodiments described above, the busbars are ultrasonically joined, but the present invention is not limited thereto. For example, the busbars may be joined using solder or sintered material.

[0133] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, characterized in that: have: substrate substrate; A housing is provided on the upper surface of the substrate; A first stacked body is arranged on the upper surface of the base substrate and inside the housing; a second stacked body disposed on the upper surface of the base substrate and separated from the first stacked body; as well as A first flat-plate-shaped conductor having a first portion in contact with the first stack and a second portion in contact with the second stack; The first stack includes a first insulator, a second conductor provided on an upper surface of the first insulator and in contact with the first portion of the first conductor, and a first semiconductor element electrically connected to the second conductor. The second stacked body includes a second insulator and a third conductor provided on an upper surface of the second insulator and in contact with the second portion of the first conductor, and the second stacked body does not include a semiconductor element.

2. The semiconductor device according to claim 1, wherein: The second stacked body is located between the first stacked body and the housing.

3. The semiconductor device according to claim 2, wherein: The semiconductor device further includes a fourth conductor having a third portion in contact with the first portion of the first conductor and a fourth portion located on the upper surface of the housing and functioning as a terminal.

4. The semiconductor device according to claim 2, wherein: The first conductor further includes a fifth portion located on the upper surface of the housing and functioning as a terminal.

5. The semiconductor device according to claim 1, wherein: The second stacked body is located inside the housing.

6. The semiconductor device according to claim 5, wherein: The second portion of the first conductor is located on the upper surface of the housing and functions as a terminal.

7. The semiconductor device according to claim 5, wherein: The second portion of the first conductor is in contact with the third conductor through the inner surface of the housing. The first conductor and the third conductor are one continuous member.

8. The semiconductor device according to claim 7, wherein: The material of the second insulator is different from that of the first insulator.

9. The semiconductor device according to claim 7, wherein: The material of the second insulator is substantially the same as that of the first insulator.

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