Semiconductor circuit and semiconductor device

Abstract

According to one embodiment, a semiconductor circuit includes transistors PM10-PM12, NM10, NM11, and a constant current source CS10. The transistor PM10 is connected between the node VDD and the node ND10, and the grid end of the transistor PM10 is connected to the node ND10 through the resistor R10. The transistor PM11 is connected between the node VDD and the node ND11, and the grid end of the transistor PM11 is connected to the node ND10. The node ND11 is connected to the output node OUT. The transistor NM10 is connected between the node ND10 and the node ND12, and the gate end of the transistor NM10 is connected to the input node IN. The transistor NM11 is connected between the nodes ND11 and ND12, and the gate terminal is connected to the input node / IN. One end and the other end of the constant current source CS10 are connected between the node ND12 and the node VSS. The transistor PM12 is connected between a node VDD and an input node / IN, and the gate end of the transistor PM12 is connected to the gate end of the transistor PM10.

Description

Technical Field

[0001] Embodiments relate to a semiconductor circuit and a semiconductor device. Background Art

[0002] A semiconductor circuit used for high-speed signal transmission in an integrated circuit is known.

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0343328 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] Provided is a semiconductor circuit capable of realizing high-speed signal transmission.

[0008] [Technical means to solve the problem]

[0009] The semiconductor circuit of the embodiment includes first to third first conductivity type transistors, first and second second conductivity type transistors, and a constant current source. One end and the other end of the first first conductivity type transistor are connected to the first power supply node and the first node, respectively. The gate end of the first first conductivity type transistor is connected to the first node via a resistor. One end and the other end of the second first conductivity type transistor are connected to the first power supply node and the second node, respectively. The second node is connected to the output node. The gate end of the second first conductivity type transistor is connected to the first node. One end and the other end of the first second conductivity type transistor are connected to the first node and the third node, respectively. The gate end of the first second conductivity type transistor is connected to the first input node. One end and the other end of the second second conductivity type transistor are connected to the second node and the third node, respectively. The gate end of the second second conductivity type transistor is connected to the second input node. One end and the other end of the constant current source are connected to the third node and the second power supply node, respectively. One end and the other end of the third first-conductivity-type transistor are connected to the first power supply node and the second input node, respectively. The gate end of the third first-conductivity-type transistor is connected to the gate end of the first first-conductivity-type transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit according to the first embodiment.

[0011] Figure 2 This is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit according to a modification of the first embodiment.

[0012] Figure 3This is a schematic diagram showing an overview of the operation of the semiconductor circuit according to the first embodiment.

[0013] Figure 4 It is a waveform chart showing the simulation result of the operation of the semiconductor circuit according to the first embodiment.

[0014] Figure 5 It is a waveform diagram showing a specific example of the operation of the semiconductor circuit of the comparative example.

[0015] Figure 6 This is a waveform diagram showing a specific example of the operation of the semiconductor circuit according to the first embodiment.

[0016] Figure 7 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the second embodiment.

[0017] Figure 8 This is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit according to a modification of the second embodiment.

[0018] Fig. 9 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the third embodiment.

[0019] Fig.10 This is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit according to a modification of the third embodiment.

[0020] Fig.11 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to a first configuration example of the fourth embodiment.

[0021] Fig.12 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the second configuration example of the fourth embodiment.

[0022] Fig.13 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the third configuration example of the fourth embodiment.

[0023] Fig.14 This is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit according to a fourth configuration example of the fourth embodiment.

[0024] Fig.15 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to a fifth configuration example of the fourth embodiment.

[0025] Fig.16 This is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to a sixth configuration example of the fourth embodiment.

[0026] Fig.17This is a block diagram showing an example of the configuration of a semiconductor device according to a first configuration example of the fifth embodiment.

[0027] Fig.18 This is a block diagram showing an example of the configuration of an input / output circuit included in the semiconductor device according to the first configuration example of the fifth embodiment.

[0028] Fig.19 This is a block diagram showing an example of the configuration of a data input circuit of a semiconductor device according to a first configuration example of the fifth embodiment.

[0029] Fig. 20 This is a circuit diagram showing an example of the configuration of a C2C (Current Mode Logic to Complementary Metal Oxide Semiconductor) circuit included in the data input circuit of the semiconductor device according to the first configuration example of the fifth embodiment.

[0030] Fig.21 This is a circuit diagram showing an example of the configuration of a C2C circuit included in the data input circuit of the semiconductor device according to the first configuration example of the fifth embodiment.

[0031] Fig. 22 This is a block diagram showing an example of the configuration of a semiconductor device according to a second configuration example of the fifth embodiment.

[0032] Fig.23 This is a block diagram showing an example of the configuration of a semiconductor device according to a third configuration example of the fifth embodiment.

[0033] Fig.24 This is a block diagram showing an example of the configuration of a semiconductor device according to a fourth configuration example of the fifth embodiment.

[0034] Fig.25 This is a block diagram showing an example of the configuration of a semiconductor device according to a fifth configuration example of the fifth embodiment.

[0035] Fig.26 This is a block diagram showing an example of the configuration of a semiconductor device according to a sixth configuration example of the fifth embodiment.

[0036] Fig. 27 This is a block diagram showing an example of the configuration of a semiconductor device according to a seventh configuration example of the fifth embodiment.

[0037] Fig.28 This is a block diagram showing an example of the configuration of a semiconductor device according to an eighth configuration example of the fifth embodiment.

[0038] Fig.29 This is a circuit diagram showing an example of a circuit configuration of a constant current source formed of N-type transistors.

[0039] Fig.30 This is a circuit diagram showing an example of a circuit configuration of a constant current source formed of a P-type transistor. DETAILED DESCRIPTION

[0040] Hereinafter, each embodiment will be described with reference to the accompanying drawings. Each embodiment illustrates a device or method for embodying the technical idea of ​​the invention. The accompanying drawings are schematic or conceptual. The diagrams of the components are appropriately omitted. In this specification, the same symbols are attached to the components having substantially the same function and structure. The numbers or characters attached to the reference symbols are referenced by the same reference symbols and are used to distinguish similar elements from each other.

[0041] In addition, in this specification, N-type transistors NM and NT are each, for example, N-type MOS (Metal Oxide Semiconductor) transistors. P-type transistors PM and PT are each, for example, P-type MOS transistors. Resistor R can be set by an element or by wiring. Constant current source CS is a power supply circuit that controls the output current to be constant. A power supply voltage is applied to the power supply node VDD. A ground voltage is applied to the ground node VSS. The power supply voltage is a voltage higher than the ground voltage. An input signal is input to the input node. An output signal is output from the output node. The voltages of the input node and the output node are referred to as "input voltage" and "output voltage", respectively. " / " attached to a reference symbol indicates an inversion signal of a signal input to or outputting a node of the combined reference symbol.

[0042] <1> First Embodiment

[0043] The semiconductor circuit 1 of the first embodiment is a 2-input 1-output (2in 1out) CML (Current Mode Logic) to CMOS (Complementary Metal Oxide Semiconductor) circuit (hereinafter referred to as a "C2C circuit") having a structure for feeding back a signal of an active inductor. The semiconductor circuit 1 of the first embodiment will be described in detail below.

[0044] <1-1>Composition

[0045] Figure 1 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 1 according to the first embodiment. Figure 1As shown, the semiconductor circuit 1 is a C2C circuit that receives small analog signals at input nodes IN and / IN and outputs large digital signals from an output node OUT. The semiconductor circuit 1 includes, for example, P-type transistors PM10 to PM12, N-type transistors NM10 and NM11, a resistor R10, a constant current source CS10, and nodes ND10 to ND12.

[0046] The source terminal and drain terminal of the P-type transistor PM10 are connected to the power supply node VDD and the node ND10, respectively. The gate terminal of the P-type transistor PM10 is connected to the node ND10 via the resistor R10. The drain terminal and source terminal of the N-type transistor NM10 are connected to the nodes ND10 and ND12, respectively. The gate terminal of the N-type transistor NM10 is connected to the input node IN.

[0047] The source terminal and drain terminal of the P-type transistor PM11 are connected to the power supply node VDD and the node ND11, respectively. The gate terminal of the P-type transistor PM11 is connected to the node ND10. The node ND11 is connected to the output node OUT. The drain terminal and source terminal of the N-type transistor NM11 are connected to the nodes ND11 and ND12, respectively. The gate terminal of the N-type transistor NM11 is connected to the input node / IN.

[0048] An input terminal and an output terminal of the constant current source CS10 are connected to the node ND12 and the ground node VSS, respectively.

[0049] The source terminal and the drain terminal of the P-type transistor PM12 are connected to the power supply node VDD and the input node / IN, respectively. The gate terminal of the P-type transistor PM12 is connected to the gate terminal of the P-type transistor PM10. The P-type transistor PM12 can be smaller than the P-type transistor PM10. The ratio of the size of the P-type transistor PM12 to the size of the P-type transistor PM10 is, for example, 1:1.2 to 7.

[0050] In the C2C circuit of the first embodiment, the transistor receiving the input signal may also be a P-type transistor. Hereinafter, as a C2C circuit of a variation of the first embodiment, a semiconductor device 1A having a PMOS (Positive-channel Metal Oxide Semiconductor) transistor receiving the input signal will be described.

[0051] Figure 2 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit 1A according to a variation of the first embodiment. Figure 2 As shown, the semiconductor circuit 1A includes, for example, P-type transistors PM13 and PM14 , N-type transistors NM12 - NM14 , a resistor R11 , a constant current source CS11 , and nodes ND13 - ND15 .

[0052] An input terminal and an output terminal of the constant current source CS11 are connected to the power supply node VDD and the node ND13 respectively.

[0053] The source terminal and drain terminal of the P-type transistor PM13 are connected to nodes ND13 and ND14, respectively. The gate terminal of the P-type transistor PM13 is connected to the input node IN. The drain terminal and source terminal of the N-type transistor NM12 are connected to the node ND14 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM12 is connected to the node ND14 via the resistor R11.

[0054] The source terminal and drain terminal of the P-type transistor PM14 are connected to the nodes ND13 and ND15, respectively. The gate terminal of the P-type transistor PM14 is connected to the input node / IN. The node ND15 is connected to the output node OUT. The drain terminal and source terminal of the N-type transistor NM13 are connected to the node ND15 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM13 is connected to the node ND14.

[0055] The drain terminal and the source terminal of the N-type transistor NM14 are connected to the input node / IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM14 is connected to the gate terminal of the N-type transistor NM12. The N-type transistor NM14 can be smaller than the N-type transistor NM12. The ratio of the size of the N-type transistor NM14 to the size of the N-type transistor NM12 is, for example, 1:1.2-7.

[0056] <1-2>Action

[0057] Figure 3 1 is a schematic diagram showing an overview of the operation of the semiconductor circuit 1 according to the first embodiment. Figure 3 As shown, in the semiconductor circuit 1, a parasitic capacitor PC is formed at the gate terminal of the P-type transistor PM10. In addition, in the semiconductor circuit 1, the group of the parasitic capacitor PC and the resistor R10 functions as an RC (Resistor-Capacitance) filter. As a result, the group of the P-type transistor PM10, the parasitic capacitor PC and the resistor R10 functions as an active inductor. Moreover, in the semiconductor circuit 1, the P-type transistor PM12 feeds back the signal of the active inductor to the input node / IN.

[0058] Specifically, the ON / OFF of the N-type transistors NM10 and NM11 varies according to the input signals IN and / IN. In this way, the voltage of the node ND10 varies according to the states of the N-type transistors NM10 and NM11. When a high-frequency signal is input to the input nodes IN and / IN, when the N-type transistor NM10 is in the on state, the parasitic capacitance PC is charged. As a result, at the gate end of the P-type transistor PM10, the high-frequency signal is suppressed and may become a DC signal. Moreover, in the semiconductor circuit 1, the gate end of the P-type transistor PM12 is connected to the gate end of the P-type transistor PM10, and the P-type transistor PM12 is connected between the power supply node VDD and the input node / IN. Thus, the P-type transistor PM12 can feed back a signal based on the voltage of the gate end of the P-type transistor PM10 to the node / IN, and can reduce the gain near the DC of the semiconductor circuit 1.

[0059] In addition, similarly to the semiconductor circuit 1 , the N-type transistor NM14 of the semiconductor circuit 1A can feed back a signal based on the voltage at the gate terminal of the N-type transistor NM12 to the node / IN, and can reduce the gain of the semiconductor circuit 1A near direct current.

[0060] <1-3> Effects of the First Embodiment

[0061] According to the semiconductor circuits 1 and 1A of the first embodiment described above, high-speed signal transmission can be realized. The effects of the first embodiment will be described in detail below.

[0062] The frequency of the signal used for data transmission and reception between two devices tends to increase as data communication speeds up. Therefore, it is expected that the circuit used for signal transmission can handle high-frequency signals. However, if the frequency of the signal becomes higher, the receiving circuit cannot fully swing, and there is a concern that skew will occur.

[0063] As a method of suppressing skew, it is considered to set multiple CMLs on the path of the input node to reduce the gain near DC. By reducing the gain near DC, full swing can be performed in the receiving circuit and high-speed operation can be achieved. However, setting multiple CMLs on the path of the input node requires a wider circuit area or a larger current consumption, which may become a major cause of increased cost of semiconductor circuits.

[0064] Therefore, the semiconductor circuit 1 and 1A of the first embodiment includes a transistor that operates based on the voltage of the active inductor. Thus, the semiconductor circuit 1 and 1A can feed back a voltage based on a signal input to the input node IN to the paired input node / IN.

[0065] Figure 4 It is a waveform chart showing the simulation result of the operation of the semiconductor circuit 1 according to the first embodiment. Figure 4 1 shows the change in voltage at the output node of the semiconductor circuit 1 when the signal input to the input node changes from a DC signal to a high-frequency signal. The dotted line shows the change in voltage at the output node of the semiconductor circuit 1 corresponding to the first embodiment. Figure 4 In FIG. 1 , as a comparative example, a simulation result when the P-type transistor PM12 is omitted from the semiconductor circuit 1 is shown by a solid line.

[0066] like Figure 4 As shown, in the comparative example, the difference between the output voltage based on the DC signal and the peak value of the output voltage at the initial swing when the DC signal changes to the high-frequency signal is DX. On the other hand, in the first embodiment, the difference between the output voltage based on the DC signal and the peak value of the output voltage at the initial swing when the DC signal changes to the high-frequency signal is DY which is smaller than DX. That is, in the semiconductor circuit 1 of the first embodiment, the gain of the semiconductor circuit 1 (transmission circuit) near the DC is reduced by the P-type transistor PM12. The semiconductor circuit 1A can also reduce the gain near the DC by the N-type transistor NM14, similarly to the semiconductor circuit 1.

[0067] Figure 5 and Figure 6 It is a waveform diagram showing a specific example of the operation of the semiconductor circuit 1 . Figure 5 and Figure 6 These correspond to the comparative example and the first embodiment, respectively. Figure 5 and Figure 6 The waveform shown in (A) in each of the figures shows the timing at which the signal input to the semiconductor circuit 1 changes between the “L (Low: Low)” level and the “H (High: High)” level. Figure 5 and Figure 6 The waveform shown in (B) in each case represents an output signal of the semiconductor circuit 1 based on the signal shown in (A). Figure 5 and Figure 6 Regions AR1 to AR3 shown in (B) in each of them capture the period of one pulse. Specifically, region AR1 captures the waveform of the output voltage when a signal of "H" level is inputted from a DC signal of "L". Region AR2 captures the waveform of the output voltage when a high-frequency signal is inputted. Region AR3 captures the waveform of the output voltage when a signal of "L" level is inputted from a DC signal of "H".

[0068] like Figure 5As shown in (B) in FIG. 1 , in each of the regions AR1 to AR3 of the comparative example, the output voltage cannot fully swing. Specifically, in the comparative example, the difference (amplitude) between the output voltage based on the DC signal at the "L" level and the output voltage based on the DC signal at the "H" level is represented as "A1". Moreover, in the comparative example, in any of the regions AR1 to AR3, the variation of the output voltage is less than A1. Figure 5 (C) in the figure shows that the waveforms of the regions AR1 and AR3 of the comparative example are overlapped so that the timing of the transition from the "L" level to the "H" level is consistent. Figure 5 As shown in (C) in FIG. 1 , in each of the regions AR1 and AR3 of the comparative example, since full swing cannot be performed, the timing of crossing the threshold value for judging the "H" level and the "L" level when changing from the "L" level to the "H" level is different. In other words, in the comparative example, skew may occur.

[0069] On the other hand, Figure 6 As shown in (B) in the figure, in each of the regions AR1 to AR3 in the first embodiment, the output voltage can fully swing. Specifically, in the first embodiment, the difference (amplitude) between the output voltage based on the DC signal at the "L" level and the output voltage based on the DC signal at the "H" level is represented as "A2". Moreover, in the first embodiment, the variation of the output voltage in any of the regions AR1 to AR3 is the same as A2. Figure 6 (C) in FIG. 1 shows a state where the waveforms of the regions AR1 and AR3 overlap in the first embodiment. Figure 6 As shown in (C), in each of the regions AR1 and AR3 of the first embodiment, since full swing can be performed, when the "L" level changes to the "H" level, the timing of crossing the threshold value for judging the "H" level and the "L" level is substantially the same. In other words, in the first embodiment, skew can be suppressed.

[0070] As described above, the semiconductor circuit 1 and 1A of the first embodiment can improve the output voltage to a state closer to the full swing compared to the case where the voltage of the active inductor is not fed back. As a result, the semiconductor circuit 1 and 1A can improve the skew and realize high-speed operation corresponding to high frequency. In other words, the semiconductor circuit 1 and 1A can realize high-speed signal transmission.

[0071] In addition, in the semiconductor circuit 1 and 1A of the first embodiment, the transistor added to feed back the voltage of the active inductor is one. This one transistor can achieve the same effect as when a plurality of CMLs are provided on the path of the input node. Therefore, compared with the case where a plurality of CMLs are provided on the path of the input node, the semiconductor circuit 1 and 1A of the first embodiment can realize a circuit with a smaller area.

[0072] In addition, in the first embodiment, although the case where the additional transistor for feeding back the voltage of the active inductor is one is illustrated, it is not limited to this. According to the layout of the circuit area around the semiconductor circuit 1 and 1A of the first embodiment, the P-type transistor PM12 or the N-type transistor NM14 can also be composed of a plurality of transistors. Specifically, for example, in the semiconductor circuit 1, the gate terminals of the plurality of P-type transistors PM12 are connected to the gate terminal of the P-type transistor PM10, and the plurality of P-type transistors PM12 are connected between the power supply node VDD and the input node / IN. The total size of the plurality of P-type transistors PM12 can also be smaller than the P-type transistor PM10. The ratio of the total size of the plurality of P-type transistors PM12 to the size of the P-type transistor PM10 is, for example, 1:1.2 to 7. Specifically, for example, in the semiconductor circuit 1A, the drain terminals and source terminals of the plurality of N-type transistors NM14 are connected to the input node / IN and the ground node VSS, respectively. The gate terminals of the plurality of N-type transistors NM14 are connected to the gate terminal of the N-type transistor NM12. The total size of the plurality of N-type transistors NM14 can also be smaller than that of the N-type transistor NM12. The ratio of the total size of the plurality of N-type transistors NM14 to the size of the N-type transistor NM12 is, for example, 1:1.2-7.

[0073] In addition, the semiconductor circuits 1 and 1A of the first embodiment are preferably used in a differentiated manner according to the input signal (input circuit). By using the semiconductor circuit 1 based on NMOS (Negative-channel Metal MxideMemiconductor: negative channel metal oxide semiconductor) and the semiconductor circuit 1A based on PMOS in a differentiated manner according to the characteristics of the input signal, high-speed signal transmission can be achieved with more desired efficiency.

[0074] <2> Second Embodiment

[0075] The semiconductor circuit 2 of the second embodiment is a 2-input 2-output (2in 2out) differential amplifier circuit having a configuration for feeding back a signal of an active inductor. The semiconductor circuit 2 of the second embodiment will be described in detail below.

[0076] <2-1>Composition

[0077] Figure 7 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 2 according to the second embodiment. Figure 7As shown, the semiconductor circuit 2 is a differential amplifier circuit that amplifies the difference between two input voltages input to input nodes IN and / IN, and outputs the difference from output nodes OUT and / OUT. The semiconductor circuit 2 includes, for example, P-type transistors PM20 to PM23, N-type transistors NM20 and NM21, resistors R20 and R21, a constant current source CS20, and nodes ND20 to ND22.

[0078] The source terminal and drain terminal of the P-type transistor PM20 are connected to the power supply node VDD and ND20, respectively. The gate terminal of the P-type transistor PM20 is connected to the node ND20 via the resistor R20. The node ND20 is connected to the output node OUT. The drain terminal and source terminal of the N-type transistor NM20 are connected to the nodes ND20 and ND22, respectively.

[0079] The source terminal and drain terminal of the P-type transistor PM21 are connected to the power supply node VDD and ND21, respectively. The gate terminal of the P-type transistor PM21 is connected to the node ND21 via the resistor R21. The node ND21 is connected to the output node / OUT. The drain terminal and source terminal of the N-type transistor NM21 are connected to the nodes ND21 and ND22, respectively.

[0080] An input terminal and an output terminal of the constant current source CS20 are connected to the node ND22 and the ground node VSS, respectively.

[0081] The source terminal and the drain terminal of the P-type transistor PM22 are connected to the power supply node VDD and the input node / IN, respectively. The gate terminal of the P-type transistor PM12 is connected to the gate terminal of the P-type transistor PM20. The P-type transistor PM22 can be smaller than the P-type transistor PM20. The ratio of the size of the P-type transistor PM22 to the size of the P-type transistor PM20 is, for example, 1:1.2 to 7.

[0082] The source terminal and the drain terminal of the P-type transistor PM23 are connected to the power supply node VDD and the input node IN, respectively. The gate terminal of the P-type transistor PM23 is connected to the gate terminal of the P-type transistor PM21. The P-type transistor PM23 can be smaller than the P-type transistor PM21. The ratio of the size of the P-type transistor PM23 to the size of the P-type transistor PM21 is, for example, 1:1.2-7.

[0083] In the differential amplifier circuit of the second embodiment, the transistor that receives the input signal may also be a P-type transistor. Hereinafter, as a differential amplifier circuit of a modified example of the second embodiment, a semiconductor device 2A having a PMOS transistor that receives the input signal will be described.

[0084] Figure 8 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit 2A according to a variation of the second embodiment. Figure 8As shown, the semiconductor circuit 2A includes, for example, P-type transistors PM24 and PM25 , N-type transistors NM22 - NM25 , resistors R22 and R23 , a constant current source CS21 , and nodes ND23 - ND25 .

[0085] An input terminal and an output terminal of the constant current source CS21 are connected to the power supply node VDD and the node ND23 respectively.

[0086] The source terminal and drain terminal of the P-type transistor PM24 are connected to the node ND23 and the node ND24, respectively. The gate terminal of the P-type transistor PM24 is connected to the input node IN. The node ND24 is connected to the output node OUT. The drain terminal and source terminal of the N-type transistor NM22 are connected to the node ND24 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM22 is connected to the node ND24 via the resistor R22.

[0087] The source terminal and drain terminal of the P-type transistor PM25 are connected to the node ND23 and the node ND25, respectively. The gate terminal of the P-type transistor PM25 is connected to the input node / IN. The node ND25 is connected to the output node / OUT. The drain terminal and source terminal of the N-type transistor NM23 are connected to the node ND25 and the ground node VSS, respectively. The gate terminal of the N-type transistor NM23 is connected to the node ND25 via the resistor R23.

[0088] The drain terminal and the source terminal of the N-type transistor NM24 are connected to the input node / IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM24 is connected to the gate terminal of the N-type transistor NM22. The N-type transistor NM24 can be smaller than the N-type transistor NM22. The ratio of the size of the N-type transistor NM24 to the size of the N-type transistor NM22 is, for example, 1:1.2-7.

[0089] The drain terminal and the source terminal of the N-type transistor NM25 are connected to the input node IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM25 is connected to the gate terminal of the N-type transistor NM23. The N-type transistor NM25 can be smaller than the N-type transistor NM23. The ratio of the size of the N-type transistor NM25 to the size of the N-type transistor NM23 is, for example, 1:1.2-7.

[0090] <2-2> Effects of the Second Embodiment

[0091] In the semiconductor circuit 2, the P-type transistor PM22 feeds back a signal based on the voltage at the gate terminal of the P-type transistor PM20 corresponding to the active inductor to the node / IN. In addition, in the semiconductor circuit 2, the P-type transistor PM23 feeds back a signal based on the voltage at the gate terminal of the P-type transistor PM21 corresponding to the active inductor to the node IN. As a result, the semiconductor circuit 2 can reduce the gain near the DC.

[0092] Similarly, in the semiconductor circuit 2A, the N-type transistor NM24 feeds back a signal based on the voltage at the gate terminal of the N-type transistor NM22 corresponding to the active inductor to the node / IN. In addition, in the semiconductor circuit 2A, the N-type transistor NM25 feeds back a signal based on the voltage at the gate terminal of the N-type transistor NM23 corresponding to the active inductor to the node IN. As a result, the semiconductor circuit 2 can reduce the gain near the DC.

[0093] Therefore, the semiconductor circuits 2 and 2A of the second embodiment can improve the output voltage to a state close to the full swing, as in the first embodiment. As a result, the semiconductor circuits 2 and 2A can improve the skew and can achieve high-speed operation corresponding to the high frequency. In addition, the semiconductor circuits 2 and 2A of the second embodiment can be implemented by a circuit with a smaller area, as in the first embodiment. In addition, by using the semiconductor circuits 2 and 2A of the second embodiment according to the input signal, high-speed signal transmission can be achieved with more desired efficiency.

[0094] <3> Third Embodiment

[0095] The semiconductor circuit 3 of the third embodiment is a 2-input 2-output (2in 2out) continuous time linear equalizer (CTLE) having a configuration of feeding back signals of operating nodes similar to an active inductor. The semiconductor circuit 3 of the third embodiment will be described in detail below.

[0096] <3-1>Composition

[0097] Fig. 9 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 3 according to the third embodiment. Fig. 9 As shown, the semiconductor circuit 3 is a CTLE that amplifies two input voltages input to the input nodes IN and / IN respectively and outputs them from the output nodes OUT and / OUT. The semiconductor circuit 3 can amplify a specified frequency band of the signal. The semiconductor circuit 3 includes, for example, P-type transistors PM30 and PM31, N-type transistors NM30 and NM31, resistors R30 to R32, a capacitive element (capacitor) CP30, constant current sources CS30 and CS31, and nodes ND30 to ND33.

[0098] The node ND30 is connected to the output node OUT. The node ND30 is connected to the power supply node VDD via the resistor R30. The drain terminal and the source terminal of the N-type transistor NM30 are connected to the nodes ND30 and ND32, respectively. The input terminal and the output terminal of the constant current source CS30 are connected to the node ND32 and the ground node VSS, respectively.

[0099] Node ND31 is connected to output node / OUT. Node ND31 is connected to power supply node VDD via resistor R31. The drain terminal and source terminal of N-type transistor NM31 are connected to nodes ND31 and ND33, respectively. The input terminal and output terminal of constant current source CS31 are connected to node ND33 and ground node VSS, respectively.

[0100] A resistor R32 and a capacitor CP30 are connected in parallel between nodes ND32 and ND33 . The resistor R32 and the capacitor CP30 function as an RC filter.

[0101] The source terminal and the drain terminal of the P-type transistor PM30 are connected to the power supply node VDD and the input node / IN, respectively. The gate terminal of the P-type transistor PM30 is connected to the node ND30.

[0102] The source terminal and the drain terminal of the P-type transistor PM31 are respectively connected to the power supply node VDD and the input node IN. The gate terminal of the P-type transistor PM31 is connected to the node ND31.

[0103] In the CTLE of the third embodiment, the transistor that receives the input signal may also be a P-type transistor. Hereinafter, as a CTLE of a modified example of the third embodiment, a semiconductor device 3A having a PMOS transistor that receives the input signal will be described.

[0104] Fig.10 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit 3A according to a variation of the third embodiment. Fig.10 As shown, the semiconductor circuit 3A includes, for example, P-type transistors PM32 and PM33, N-type transistors NM32 and NM33, resistors R33 to R35, a capacitor CP31, constant current sources CS32 and CS33, and nodes ND34 to ND37.

[0105] The input and output terminals of the constant current source CS32 are connected to the power supply node VDD and the node ND34, respectively. The source terminal and the drain terminal of the P-type transistor PM32 are connected to the nodes ND34 and ND36, respectively. The node ND36 is connected to the output node OUT. The node ND36 is connected to the ground node VSS via the resistor R34.

[0106] The input and output terminals of the constant current source CS33 are connected to the power supply node VDD and the node ND35, respectively. The source terminal and the drain terminal of the P-type transistor PM33 are connected to the nodes ND35 and ND37, respectively. The node ND37 is connected to the output node / OUT. The node ND37 is connected to the ground node VSS via the resistor R35.

[0107] A resistor R33 and a capacitor CP31 are connected in parallel between nodes ND34 and ND35. The resistor R33 and the capacitor CP31 function as an RC filter.

[0108] The drain terminal and the source terminal of the N-type transistor NM32 are connected to the input node / IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM32 is connected to the node ND36.

[0109] The drain terminal and the source terminal of the N-type transistor NM33 are connected to the input node IN and the ground node VSS, respectively. The gate terminal of the N-type transistor NM33 is connected to the node ND37.

[0110] Furthermore, the resistance values ​​of the resistors R32 and R33 included in the semiconductor circuits 3 and 3A, the capacitance values ​​of the capacitors CP30 and CP31, and the like can also be configured to be adjustable based on a control signal input from the outside.

[0111] <3-2> Effects of the third embodiment

[0112] In the semiconductor circuit 3, the P-type transistor PM30 feeds back a signal based on the voltage of the node ND30 that operates in the same manner as an active inductor to the node / IN. In addition, in the semiconductor circuit 3, the P-type transistor PM31 feeds back a signal based on the voltage of the node ND31 that operates in the same manner as an active inductor to the node IN. As a result, the semiconductor circuit 3 can reduce the gain near the DC.

[0113] Similarly, in the semiconductor circuit 3A, the N-type transistor NM32 feeds back a signal based on the voltage of the node ND36 that operates in the same manner as an active inductor to the node / IN. In addition, in the semiconductor circuit 3A, the N-type transistor NM33 feeds back a signal based on the voltage of the node ND37 that operates in the same manner as an active inductor to the node IN. As a result, the semiconductor circuit 3 can reduce the gain near the DC.

[0114] Therefore, the semiconductor circuits 3 and 3A of the third embodiment can improve the output voltage to a state close to the full swing, as in the first embodiment. As a result, the semiconductor circuits 3 and 3A can improve the skew and can achieve high-speed operation corresponding to the high frequency. In addition, the semiconductor circuits 3 and 3A of the third embodiment can be implemented by a circuit with a smaller area, as in the first embodiment. In addition, by using the semiconductor circuits 3 and 3A of the third embodiment according to the input signal, high-speed signal transmission can be achieved with more desired efficiency.

[0115] <4> Fourth embodiment

[0116] The semiconductor circuit of the fourth embodiment has a configuration in which a circuit is added to each of the semiconductor circuits 1, 1A, 2, 2A, 3, and 3A of the first to third embodiments, and the circuit can switch whether to use a transistor for feeding back a signal of an active inductor. The semiconductor circuit of the fourth embodiment will be described in detail below.

[0117] <4-1>Composition

[0118] Hereinafter, the semiconductor device 1 to which the fourth embodiment is applied is referred to as a semiconductor circuit 1B of the first configuration example of the fourth embodiment. The semiconductor device 1A to which the fourth embodiment is applied is referred to as a semiconductor circuit 1C of the second configuration example of the fourth embodiment. The semiconductor device 2 to which the fourth embodiment is applied is referred to as a semiconductor circuit 2B of the third configuration example of the fourth embodiment. The semiconductor device 2A to which the fourth embodiment is applied is referred to as a semiconductor circuit 2C of the fourth configuration example of the fourth embodiment. The semiconductor device 3 to which the fourth embodiment is applied is referred to as a semiconductor circuit 3B of the fifth configuration example of the fourth embodiment. The semiconductor device 3A to which the fourth embodiment is applied is referred to as a semiconductor circuit 3C of the sixth configuration example of the fourth embodiment.

[0119] <Configuration Example 1: C2C Circuit (NMOS-based)>

[0120] Fig.11 1 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit 1B according to a first configuration example of the fourth embodiment. Fig.11 As shown, the semiconductor circuit 1B has a configuration in which, for example, P-type transistors PM15 and PM16 and P-type transistors PT10 to PT12 are added to the semiconductor circuit 1 .

[0121] In the semiconductor circuit 1B, a circuit similar to the semiconductor circuit 1 is formed by P-type transistors PM10 to PM12 , N-type transistors NM10 and NM11 , a resistor R10 , a constant current source CS10 , and nodes ND10 to ND12 corresponding to the semiconductor circuit 1 .

[0122] The drain terminal of each of the P-type transistors PM15 and PM16 is connected to the input node / IN. The gate terminal of each of the P-type transistors PM15 and PM16 is connected to the gate terminal of the P-type transistor PM10.

[0123] The P-type transistor PT10 is connected between the power supply node VDD and the source terminal of the P-type transistor PM12. The P-type transistor PT11 is connected between the power supply node VDD and the source terminal of the P-type transistor PM15. The P-type transistor PT12 is connected between the power supply node VDD and the source terminal of the P-type transistor PM16.

[0124] In other words, the source terminals of the P-type transistors PT10 to PT12 are connected to the power supply node VDD. The drain terminal of the P-type transistor PT10 is connected to the source terminal of the P-type transistor PM12. The drain terminal of the P-type transistor PT11 is connected to the source terminal of the P-type transistor PM15. The drain terminal of the P-type transistor PT12 is connected to the source terminal of the P-type transistor PM16.

[0125] A control signal EN10 is input to the gate terminal of the P-type transistor PT10. A control signal EN11 is input to the gate terminal of the P-type transistor PT11. A control signal EN12 is input to the gate terminal of the P-type transistor PT12. The control signals EN10 to EN12 are signals that can be individually controlled by an external control circuit. Based on the control signals EN10 to EN12, the on / off of each of the P-type transistors PT10 to PT12 can be controlled.

[0126] In addition, in the first configuration example of the fourth embodiment, the number of groups of P-type transistors PM and PT (for example, P-type transistors PM12 and PT10) connected in series between the power supply node VDD and the input node / IN only needs to be 1 or more. In the first configuration example of the fourth embodiment, the plurality of P-type transistors PT included in the plurality of groups of P-type transistors PM and PT connected in series between the power supply node VDD and the input node / IN only needs to be individually controlled to be turned on / off.

[0127] <Second configuration example: C2C circuit (based on PMOS)>

[0128] Fig.12 1 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit 1C according to the second configuration example of the fourth embodiment. Fig.12 As shown, the semiconductor circuit 1C has a configuration in which N-type transistors NM15 and NM16 and N-type transistors NT10 to NT12 are added to the semiconductor circuit 1A, for example.

[0129] In the semiconductor circuit 1C, a circuit similar to that of the semiconductor circuit 1A is formed by P-type transistors PM13 and PM14 , N-type transistors NM12 to NM14 , a resistor R11 , a constant current source CS11 , and nodes ND13 to ND15 .

[0130] The drain terminals of the N-type transistors NM15 and NM16 are connected to the input node / IN. The gate terminals of the N-type transistors NM15 and NM16 are connected to the gate terminal of the N-type transistor NM12.

[0131] N-type transistor NT10 is connected between N-type transistor NM14 and ground node VSS. N-type transistor NT11 is connected between N-type transistor NM15 and ground node VSS. N-type transistor NT12 is connected between N-type transistor NM16 and ground node VSS. Specifically, the source terminals of each of N-type transistors NT10 to NT12 are connected to ground node VSS. The drain terminal of N-type transistor NT10 is connected to the source terminal of N-type transistor NM14. The drain terminal of N-type transistor NT11 is connected to the source terminal of N-type transistor NM15. The drain terminal of N-type transistor NT12 is connected to the source terminal of N-type transistor NM16.

[0132] A control signal EN10 is input to the gate terminal of the N-type transistor NT10. A control signal EN11 is input to the gate terminal of the N-type transistor NT11. A control signal EN12 is input to the gate terminal of the N-type transistor NT12. Based on the control signals EN10 to EN12, the N-type transistors NT10 to NT12 can be controlled to be turned on or off.

[0133] In addition, in the second configuration example of the fourth embodiment, the number of groups of N-type transistors NM and NT (for example, N-type transistors NM14 and NT10) connected in series between the input node / IN and the ground node VSS only needs to be 1 or more. In the second configuration example of the fourth embodiment, the plurality of N-type transistors NT included in the plurality of groups of N-type transistors NM and NT connected in series between the input node / IN and the ground node VSS only needs to be individually controlled to be turned on / off.

[0134] <Configuration Example 3: Differential Amplifier Circuit (NMOS-Based)>

[0135] Fig.13 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 2B of the third configuration example of the fourth embodiment. Fig.13 As shown, the semiconductor circuit 2B has a configuration in which, for example, P-type transistors PM26 and PM27 and P-type transistors PT20 to PT23 are added to the semiconductor circuit 2 .

[0136] In the semiconductor circuit 2B, a circuit similar to that of the semiconductor circuit 2 is formed by P-type transistors PM20 to PM23 , N-type transistors NM20 and NM21 , resistors R20 and R21 , a constant current source CS20 , and nodes ND20 to ND22 .

[0137] The drain terminal of the P-type transistor PM26 is connected to the input node / IN. The gate terminal of the P-type transistor PM26 is connected to the gate terminal of the P-type transistor PM20. The drain terminal of the P-type transistor PM27 is connected to the input node IN. The gate terminal of the P-type transistor PM27 is connected to the gate terminal of the P-type transistor PM21.

[0138] The P-type transistor PT20 is connected between the power supply node VDD and the P-type transistor PM22. The P-type transistor PT21 is connected between the power supply node VDD and the P-type transistor PM26. The P-type transistor PT22 is connected between the power supply node VDD and the P-type transistor PM23. The P-type transistor PT23 is connected between the power supply node VDD and the P-type transistor PM27. Specifically, the source terminals of the P-type transistors PT20 to PT23 are respectively connected to the power supply node VDD. The drain terminal of the P-type transistor PT20 is connected to the source terminal of the P-type transistor PM22. The drain terminal of the P-type transistor PT21 is connected to the source terminal of the P-type transistor PM26. The drain terminal of the P-type transistor PT22 is connected to the source terminal of the P-type transistor PM23. The drain terminal of the P-type transistor PT23 is connected to the source terminal of the P-type transistor PM27.

[0139] A control signal EN20 is input to the gate terminal of the P-type transistor PT20. A control signal EN21 is input to the gate terminal of the P-type transistor PT21. A control signal EN22 is input to the gate terminal of the P-type transistor PT22. A control signal EN23 is input to the gate terminal of the P-type transistor PT23. The control signals EN20 to EN23 are signals that can be individually controlled by an external control circuit. Based on the control signals EN20 to EN23, the on / off of each of the P-type transistors PT20 to PT23 can be controlled.

[0140] In addition, in the third configuration example of the fourth embodiment, the number of groups of P-type transistors PM and PT (for example, P-type transistors PM22 and PT20) connected in series between the power supply node VDD and the input node IN or / IN only needs to be 1 or more. In the third configuration example of the fourth embodiment, the plurality of P-type transistors PT included in the plurality of groups of P-type transistors PM and PT connected in series between the power supply node VDD and the input node IN or / IN only needs to be individually controlled to be turned on / off. As the group of P-type transistors PM and PT, at least one of the group connected to the input node IN and the group connected to the input node / IN only needs to be provided.

[0141] <Configuration Example 4: Differential Amplifier Circuit (Based on PMOS)>

[0142] Fig.14 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor circuit 2C according to a fourth configuration example of the fourth embodiment. Fig.14 As shown, the semiconductor circuit 2C has a configuration in which, for example, N-type transistors NM26 and NM27 and N-type transistors NT20 to NT23 are added to the semiconductor circuit 2A.

[0143] In the semiconductor circuit 2C, a circuit similar to the semiconductor circuit 2A is formed by P-type transistors PM24 and PM25, N-type transistors NM22 and NM25, resistors R22 and R23, a constant current source CS21, and nodes ND23 to ND25.

[0144] The drain terminal of the N-type transistor NM26 is connected to the input node / IN. The gate terminal of the N-type transistor NM26 is connected to the gate terminal of the N-type transistor NM22. The drain terminal of the N-type transistor NM27 is connected to the input node IN. The gate terminal of the N-type transistor NM27 is connected to the gate terminal of the N-type transistor NM23.

[0145] N-type transistor NT20 is connected between N-type transistor NM24 and ground node VSS. N-type transistor NT21 is connected between N-type transistor NM26 and ground node VSS. N-type transistor NT22 is connected between N-type transistor NM25 and ground node VSS. N-type transistor NT23 is connected between N-type transistor NM27 and ground node VSS. Specifically, the source terminals of each of N-type transistors NT20 to NT23 are connected to ground node VSS. The drain terminal of N-type transistor NT20 is connected to the source terminal of N-type transistor NM24. The drain terminal of N-type transistor NT21 is connected to the source terminal of N-type transistor NM26. The drain terminal of N-type transistor NT22 is connected to the source terminal of N-type transistor NM25. The drain terminal of N-type transistor NT23 is connected to the source terminal of N-type transistor NM27.

[0146] A control signal EN20 is input to the gate terminal of the N-type transistor NT20. A control signal EN21 is input to the gate terminal of the N-type transistor NT21. A control signal EN22 is input to the gate terminal of the N-type transistor NT22. A control signal EN23 is input to the gate terminal of the N-type transistor NT23. Based on the control signals EN20 to EN23, the on / off of each of the N-type transistors NT20 to NT23 can be controlled.

[0147] In addition, in the fourth configuration example of the fourth embodiment, the number of groups of N-type transistors NM and NT (for example, N-type transistors NM24 and NT20) connected in series between the input node IN or / IN and the ground node VSS only needs to be 1 or more. In the fourth configuration example of the fourth embodiment, the plurality of N-type transistors NT included in the plurality of groups of N-type transistors NM and NT connected in series between the input node IN or / IN and the ground node VSS only needs to be individually controlled to be turned on / off. As the group of N-type transistors NM and NT, at least one of the group connected to the input node IN and the group connected to the input node / IN can be provided.

[0148] <Fifth Configuration Example: CTLE (NMOS-based)>

[0149] Fig.15 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor circuit 3B according to the fifth configuration example of the fourth embodiment. Fig.15 As shown, the semiconductor circuit 3B has a configuration in which, for example, P-type transistors PM34 and PM35 and P-type transistors PT30 to PT33 are added to the semiconductor circuit 3 .

[0150] In the semiconductor circuit 3B, a circuit similar to the semiconductor circuit 3 is formed by P-type transistors PM30 and PM31, N-type transistors NM30 and NM31, resistors R30 to R32, capacitor CP30, constant current sources CS30 and CS31, and nodes ND30 to ND33.

[0151] The drain terminal of the P-type transistor PM34 is connected to the input node / IN. The gate terminal of the P-type transistor PM34 is connected to the gate terminal of the P-type transistor PM30. The drain terminal of the P-type transistor PM35 is connected to the input node IN. The gate terminal of the P-type transistor PM35 is connected to the gate terminal of the P-type transistor PM31.

[0152] The P-type transistor PT30 is connected between the power supply node VDD and the P-type transistor PM30. The P-type transistor PT31 is connected between the power supply node VDD and the P-type transistor PM34. The P-type transistor PT32 is connected between the power supply node VDD and the P-type transistor PM31. The P-type transistor PT33 is connected between the power supply node VDD and the P-type transistor PM35. Specifically, the source terminals of the P-type transistors PT30 to PT33 are respectively connected to the power supply node VDD. The drain terminal of the P-type transistor PT30 is connected to the source terminal of the P-type transistor PM30. The drain terminal of the P-type transistor PT31 is connected to the source terminal of the P-type transistor PM34. The drain terminal of the P-type transistor PT32 is connected to the source terminal of the P-type transistor PM31. The drain terminal of the P-type transistor PT33 is connected to the source terminal of the P-type transistor PM35.

[0153] A control signal EN30 is input to the gate terminal of the P-type transistor PT30. A control signal EN31 is input to the gate terminal of the P-type transistor PT31. A control signal EN32 is input to the gate terminal of the P-type transistor PT32. A control signal EN33 is input to the gate terminal of the P-type transistor PT33. The control signals EN30 to EN33 are signals that can be individually controlled by an external control circuit. Based on the control signals EN30 to EN33, the on / off of each of the P-type transistors PT30 to PT33 can be controlled.

[0154] In addition, in the fifth configuration example of the fourth embodiment, the number of groups of P-type transistors PM and PT (for example, P-type transistors PM30 and PT30) connected in series between the power supply node VDD and the input node IN or / IN only needs to be 1 or more. In the fifth configuration example of the fourth embodiment, the plurality of P-type transistors PT included in the plurality of groups of P-type transistors PM and PT connected in series between the power supply node VDD and the input node IN or / IN only needs to be individually controlled to be turned on / off. As the group of P-type transistors PM and PT, at least one of the group connected to the input node IN and the group connected to the input node / IN only needs to be provided.

[0155] <Sixth Configuration Example: CTLE (PMOS-based)>

[0156] Fig.16 1 is a circuit diagram showing an example of the circuit configuration of a semiconductor circuit 3C according to a sixth configuration example of the fourth embodiment. Fig.16 As shown, the semiconductor circuit 3C has a configuration in which N-type transistors NM34 and NM35 and N-type transistors NT30 to NT33 are added to the semiconductor circuit 3A, for example.

[0157] In the semiconductor circuit 3C, the same circuit as the semiconductor circuit 3A is formed by P-type transistors PM32 and PM33, N-type transistors NM32 and NM33, resistors R33 to R35, capacitor element CP31, constant current sources CS32 and CS33, and nodes ND34 to ND37.

[0158] The drain terminal of the N-type transistor NM34 is connected to the input node / IN. The gate terminal of the N-type transistor NM34 is connected to the gate terminal of the N-type transistor NM32. The drain terminal of the N-type transistor NM35 is connected to the input node IN. The gate terminal of the N-type transistor NM35 is connected to the gate terminal of the N-type transistor NM33.

[0159] N-type transistor NT30 is connected between N-type transistor NM32 and ground node VSS. N-type transistor NT31 is connected between N-type transistor NM34 and ground node VSS. N-type transistor NT32 is connected between N-type transistor NM33 and ground node VSS. N-type transistor NT33 is connected between N-type transistor NM35 and ground node VSS. Specifically, the source terminals of each of N-type transistors NT30 to NT33 are connected to ground node VSS. The drain terminal of N-type transistor NT30 is connected to the source terminal of N-type transistor NM32. The drain terminal of N-type transistor NT31 is connected to the source terminal of N-type transistor NM34. The drain terminal of N-type transistor NT32 is connected to the source terminal of N-type transistor NM33. The drain terminal of N-type transistor NT33 is connected to the source terminal of N-type transistor NM35.

[0160] A control signal EN30 is input to the gate terminal of the N-type transistor NT30. A control signal EN31 is input to the gate terminal of the N-type transistor NT31. A control signal EN32 is input to the gate terminal of the N-type transistor NT32. A control signal EN33 is input to the gate terminal of the N-type transistor NT33. Based on the control signals EN30 to EN33, the on / off of each of the N-type transistors NT30 to NT33 can be controlled.

[0161] In addition, in the sixth configuration example of the fourth embodiment, the number of groups of N-type transistors NM and NT (for example, N-type transistors NM32 and NT30) connected in series between the input node IN or / IN and the ground node VSS only needs to be 1 or more. In the sixth configuration example of the fourth embodiment, the plurality of N-type transistors NT included in the plurality of groups of N-type transistors NM and NT connected in series between the input node IN or / IN and the ground node VSS only needs to be individually controlled to be turned on / off. As the group of N-type transistors NM and NT, at least one of the group connected to the input node IN and the group connected to the input node / IN can be provided.

[0162] <4-2> Effects of the Fourth Embodiment

[0163] In each configuration example of the fourth embodiment described above, the number of transistors that feed back the voltage of the active inductor to the input node can be changed by the control signal EN. That is, in each configuration example of the fourth embodiment, the adjustment amount of the gain near the DC can be changed according to the input signal. The more the number of transistors that feed back the voltage of the active inductor to the input node is, the more the gain near the DC can be reduced.

[0164] Therefore, the semiconductor circuits 1B, 1C, 2B, 2C, 3B and 3C of the fourth embodiment can improve skew with better settings such as maintaining the amplitude width of the signal and achieving full swing by adjusting the gain near DC with a setting corresponding to the input signal, and can achieve high-speed operation.

[0165] <5> Fifth embodiment

[0166] The fifth embodiment relates to a specific example of a semiconductor device using at least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments. The semiconductor device of the fifth embodiment will be described in detail below.

[0167] <5-1>Composition

[0168] Hereinafter, the first to eighth configuration examples of the fifth embodiment will be described in order.

[0169] <First Configuration Example: NAND (Not-AND) Flash Memory>

[0170] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used in a NAND flash memory. Hereinafter, as an example of such a NAND flash memory, a semiconductor device 100 of a first configuration example of a fifth embodiment will be described.

[0171] (Configuration of Semiconductor Device 100)

[0172] Fig.17 1 is a block diagram showing an example of the configuration of a semiconductor device 100 (NAND flash memory) according to a first configuration example of the fifth embodiment. Fig.17 As shown, semiconductor device 100 is configured to be controllable by memory controller 110. Semiconductor device 100 includes, for example, memory cell array 101, input / output circuit 102, logic controller 103, register circuit 104, sequencer 105, driver circuit 106, row decoder module 107, and sense amplifier module 108.

[0173] The memory cell array 101 is a collection of multiple memory cells (memory cell transistors) MC that can store data non-volatilely. The memory cell array 101 is divided into multiple blocks BLK. For example, the block BLK is used as a unit for erasing data. The block BLK includes multiple pages. The page is composed of multiple memory cells MC and is used as a unit for writing and reading data. Multiple bit lines BL and multiple word lines WL are set in the memory cell array 101. Each memory cell MC is associated with one bit line BL and one word line WL. In the case where multiple memory cells MC are associated with a group of the same bit line BL and word line WL, these memory cells MC can be independently selected by using multiple selection transistors connected between the bit line BL and each memory cell MC. Each memory cell MC is a field effect transistor with a stack gate structure having a charge storage layer. The charge storage layer can be a floating gate electrode or a charge capture film. Multiple memory cells MC are arranged in a two-dimensional array or a three-dimensional array.

[0174] The input-output circuit 102 is, for example, a semiconductor integrated circuit configured to transmit and receive an 8-bit width signal DQ<7:0> and signals DQS and / DQS with the storage controller 110. The signal DQ can include data, status information, address information, instructions, etc. The signals DQS and / DQS are signals that specify the timing of transmitting and receiving the signal DQ. The signals DQS and / DQS are a pair of signals with opposite phases to each other. The input-output circuit 102 can transmit the received address information or instruction to the register circuit 104. The input-output circuit 102 can transmit and receive data DAT with the sense amplifier module 58.

[0175] The input-output circuit 102 can also be referred to as a storage interface circuit of the semiconductor device 100. The plurality of pads PD included in the semiconductor device 100 are connected to the interface circuit of the storage controller 110. The plurality of pads PD are used for input and output of the signals DQ<7:0>, DQS and / DQS. In addition, the signal DQ<7:0> can also be referred to as a "data signal". The signals DQS and BDQS can be referred to as a "data gate signal and its inversion signal". The signals DQS and / or BDQS can also be referred to as a "clock signal", "action clock signal", "gate signal", or "timing control signal".

[0176] In addition, the signal DQ is, for example, a pulse signal. Each pulse included in the signal DQ corresponds to modulated data. As a data modulation method, for example, pulse amplitude modulation (Pulse-Amplitude Modulation) is used. Pulse amplitude modulation is a modulation method that transmits data through the voltage (amplitude) of pulses at a constant interval. In the case of using pulse amplitude modulation as a data modulation method, the voltage level of each pulse of the signal DQ corresponds to 1 bit of data or multiple bits of data. In addition, the storage controller 110MC can operate as a receiving device, and the semiconductor device 100 can operate as a transmitting device.

[0177] The logic controller 103 controls the input / output circuit 102 and the sequencer 105 based on a control signal received from the memory controller 110 .

[0178] The register circuit 104 holds state information, address information, and instructions. The state information is updated according to the state of the semiconductor device 100. The state information is output to the memory controller 110 based on an instruction from the memory controller 110. The address information can include a block address, a page address, a column address, etc. The instruction includes commands related to various operations of the semiconductor device 100.

[0179] The sequencer 105 controls the overall operation of the semiconductor device 100. For example, the sequencer 105 can execute a read operation, a write operation, an erase operation, etc. based on the command and address information held in the register circuit 104.

[0180] The driver circuit 106 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 106 supplies the generated voltages to the memory cell array 101, the row decoder block 107, the sense amplifier block 108, and the like.

[0181] The row decoder module 107 is a circuit connected to the wiring (word line WL, etc.) provided in the row direction of the memory cell array 101. The row decoder module 108 includes a plurality of row decoders associated with a plurality of blocks BLK, respectively. Each row decoder includes a block decoder capable of decoding a block address. The row decoder module 108 selects a block BLK based on the decoding result of the block decoder of each row decoder. The row decoder module 108 transmits the voltage supplied from the driver circuit 106 to the word line WL, etc. in the selected block BLK, for example, via the associated row decoder RD.

[0182] The sense amplifier module 108 is a circuit connected to the wiring (bit line BL) provided in the column direction of the memory cell array 101. The sense amplifier module 108 includes a plurality of sense amplifier units respectively associated with the plurality of bit lines BL. Each sense amplifier unit has a function of applying a voltage to the associated bit line BL, a function of determining data based on the voltage of the bit line BL, and a function of temporarily storing data. In a read operation, the sense amplifier module 108 reads data from the memory cell array 101 and transmits the read data to the input-output circuit 102. In addition, in a write operation, the sense amplifier module 108 applies a desired voltage to the bit line BL based on the data received from the input-output circuit 102.

[0183] (Configuration of Input / Output Circuit 102)

[0184] Fig.18 This is a block diagram showing an example of the configuration of an input / output circuit 102 included in a semiconductor device 100 (NAND flash memory) according to a first configuration example of the fifth embodiment. Fig.18 FIG. 2 shows a case where the memory controller 110 operates as a transmitting device and the semiconductor device 100 operates as a receiving device. Fig.18 As shown, the semiconductor device 100 includes, for example, an input receiver (IREC: Input RECeiver) 111 , a driver circuit 112 , a write duty cycle adjustment circuit (WDCA: Write Duty Cycle Adjuster) 113 , a plurality of data input circuits 114 - 0 to 114 - 7 , and a processing circuit 115 .

[0185] IREC111 is a circuit for transmitting signals within the chip. IREC111 is connected to pad PD for input signal DQS and pad PD for input signal BDQS. The output signal of IREC111 is input to driver circuit 112. Since IREC111 directly receives small external signals (DQS and BDQS), a wide circuit area is required.

[0186] The driver circuit 112 is a circuit for transmitting signals in the input / output circuit 102 after the IREC 111. The driver circuit 112 amplifies the signal input from the IREC 111 and inputs it to the WDCA 113. The circuit area of ​​the driver circuit 112 is smaller than each of the IREC 111 and the WDCA, for example.

[0187] WDCA113 is, for example, a circuit that adjusts the duty cycle of the signals DQS and BDQS received from the storage controller 110 during a write operation. That is, WDCA113 compensates for the duty cycle deviation of the signals DQS and BDQS. Moreover, WDCA113 distributes the signals DQS and BDQS compensated for the duty cycle deviation as the clock signal CLK to each data input circuit 114. In addition, since WDCA113 transmits signals via long-distance wiring in the input / output circuit 102, a wider circuit area is required. The length of the wiring connecting WDCA113 and the data input circuit 114 varies depending on the position of the data input circuit 114.

[0188] A plurality of data input circuits 114-0 to 114-7 are connected to a plurality of pads PD, respectively. Each data input circuit 114 is a circuit that converts an electrical signal input via the pad PD into a digital signal. Specifically, each data input circuit 114 samples data contained in the signal DQ input to the pad PD based on the clock signal CLK input from the WDCA 113 and the inverted signal / CLK of the clock signal CLK (not shown). Furthermore, each data input circuit 114 inputs the sampled data to the processing circuit 115. The data input circuits 114-0 to 114-7 are associated with the signals DQ<0> to DQ<7>, respectively.

[0189] The processing circuit 115 is a circuit that processes data input from the data input circuits 114 - 0 to 114 - 7 , etc. The processing circuit 115 is, for example, the register circuit 104 or the sense amplifier module 108 .

[0190] When the semiconductor device 100 exchanges the signal DQ, the device on the transmitting side (e.g., the memory controller 110) transmits the signals DQS and / DQS to the device on the receiving side. The device on the receiving side samples the signal DQ at the timing based on the clock signal generated from the received signals DQS and / DQS. For example, when the device on the receiving side is the semiconductor device 100, the data sampled by the data input circuit 114 is stored in the memory cell array 101.

[0191] In addition, each of IREC111, driver circuit 112, and WDCA113 is constituted by, for example, a differential amplifier circuit. In other words, at least one of semiconductor circuits 2, 2A to 2C can be applied to each of IREC111, driver circuit 112, and WDCA113.

[0192] (Configuration of Data Input Circuit 113)

[0193] Fig.19 The block diagram shows an example of the configuration of the data input circuit 114 of the semiconductor device 100 (NAND flash memory) according to the first configuration example of the fifth embodiment. The data input circuit 114 includes, for example, a C2C circuit 120, a full scale amplifier (FS: Full Scale Amplifier) ​​121, a CTLE 122, and a sampler 123.

[0194] The C2C circuit 120 amplifies the clock signal CLK input from the WDCA 113 and the inverted signal / CLK of the clock signal CLK (not shown). The C2C circuit 120 corresponds to any of the semiconductor circuits 1 and 1A described in the first embodiment. Since the C2C circuit 120 is a circuit connected via long-distance wiring from the WDCA 113, it tends to have a small area.

[0195] FS121 is a circuit that converts the signal amplified by C2C circuit 120 into a CMOS level. FS121 inputs the clock signal CLK converted into the CMOS level to sampler 123. In addition, in this specification, the CMOS level is a logic level corresponding to "0" data or "1" data. Hereinafter, the voltage of the logic level corresponding to "0" data is referred to as "L" level, and the voltage of the logic level corresponding to "1" data is referred to as "H" level.

[0196] The CTLE 122 is an equalizer circuit that receives an electrical signal input to the data input circuit 114. The CTLE 122 compensates for the input signal DQ and inputs it to the sampler 123. A plurality of CTLEs 122 can be provided in series between the pad PD that receives the signal DQ and the sampler 123. In this case, the wiring length connecting the plurality of CTLEs 122 can be long. As the CTLE 122, the semiconductor circuit 3, 3A, 3B, or 3C can be used.

[0197] The sampler 123 samples the data of the signal DQ based on the timing indicated by the clock signal CLK, and transmits the sampling result (data DAT, etc.) of the signal DQ to the processing circuit 115.

[0198] (Configuration of C2C Circuit 120)

[0199] Fig. 201 is a circuit diagram showing an example of the configuration of a C2C circuit 120 included in a data input circuit 114 of a semiconductor device (NAND flash memory) 100 according to a first configuration example of the fifth embodiment. Fig. 20 As shown, the C2C circuit 120 includes, for example, semiconductor circuits 1H and 1L. Except for the connection relationship between the input nodes IN and / IN, the semiconductor circuits 1H and 1L have the same circuit configuration as the semiconductor circuit 1 described in the first embodiment. For example, a clock signal CLK is input to the input node IN, and an inverted signal / CLK of the clock signal is input to the input node / IN.

[0200] Specifically, the gate terminal of the N-type transistor NM10 of the semiconductor circuit 1H is connected to the input node IN. The gate terminal of the N-type transistor NM11 of the semiconductor circuit 1H is connected to the input node / IN. The gate terminal of the N-type transistor NM10 of the semiconductor circuit 1L is connected to the input node / IN. The gate terminal of the N-type transistor NM11 of the semiconductor circuit 1L is connected to the input node IN. That is, the N-type transistor NM10 of the semiconductor circuit 1H and the N-type transistor NM11 of the semiconductor circuit 1H are connected to the input node IN. The N-type transistor NM11 of the semiconductor circuit 1H and the N-type transistor NM10 of the semiconductor circuit 1L are connected to the input node / IN.

[0201] Thus, the semiconductor circuits 1H and 1L output complementary signals. For example, when a HIGH level signal is output from the node ND11 of the semiconductor circuit 1H, a LOW level signal is output from the node ND11 of the semiconductor circuit 1L. The other structures of the semiconductor circuits 1H and 1L are the same as those of the semiconductor circuit 1. In addition, when the semiconductor circuits 1H and 1L are used in combination, a constant current source CS can be added to suppress the influence of process unevenness.

[0202] Fig.21 1 is a circuit diagram showing an example of the configuration of a C2C circuit 120A included in the data input circuit 114 of the semiconductor device 100 according to the first configuration example of the fifth embodiment. Fig.21 As shown, the C2C circuit 120A includes semiconductor circuits 1H and 1L, and a constant current source CS12.

[0203] The constant current source CS12 is connected between the power supply node VDD and the P-type transistor PM12 of the semiconductor circuit 1H, and is connected between the power supply node VDD and the P-type transistor PM12 of the semiconductor circuit 1L. That is, the input end of the constant current source CS12 is connected to the power supply node VDD. The output end of the constant current source CS12 is connected to the source of the P-type transistor PM12 of the semiconductor circuit 1H and the source of the P-type transistor PM12 of the semiconductor circuit 1L. Thus, the C2C circuit 120A can reduce the sensitivity to process unevenness and realize a compensation circuit with higher accuracy.

[0204] <Second configuration example: NOR flash memory>

[0205] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can also be used in a non-volatile semiconductor memory device (e.g., a NOR flash memory) that can be accessed randomly. Hereinafter, as an example of such a NOR flash memory, a semiconductor device 200 of the second configuration example of the fifth embodiment will be described.

[0206] Fig. 22 1 is a block diagram showing an example of the configuration of a semiconductor device 200 (NOR flash memory) according to a second configuration example of the fifth embodiment. Fig. 22 As shown, the semiconductor device 200 includes, for example, a memory cell array 201 , a row control circuit 202 , a column control circuit 203 , an address register 204 , a data buffer 205 , an input / output shift register 206 , a voltage generating circuit 207 , and a sequencer 208 .

[0207] The memory cell array 201 includes a plurality of memory cells (memory cell transistors) MTx. In the semiconductor device 200, the gate terminal of each memory cell MTx is connected to a corresponding one of a plurality of word lines WL. One end of the current path of each memory cell MTx is connected to a corresponding one of a plurality of bit lines BL. The other end of the current path of each memory cell MTx is connected to a source line, for example, grounded. A plurality of memory cells MTx are arranged in a two-dimensional array or a three-dimensional array. The memory cell MTx is a field effect transistor having a stack gate structure with a charge storage layer. The charge storage layer can be a floating gate electrode or a charge capture film.

[0208] The row control circuit 202 selects a word line corresponding to address information from a plurality of word lines WL. The row control circuit 202 applies a specified voltage to the selected word line (and non-selected word lines) in accordance with a write operation, a read operation, an erase operation, and the like.

[0209] The column control circuit 203 selects a bit line corresponding to the address information from the plurality of bit lines BL and applies a specified voltage to the selected bit line (and unselected bit lines) in accordance with a write operation, a read operation, an erase operation, and the like.

[0210] The address register 204 temporarily stores the address information from the input / output shift register 206. The address register 204 sends the address information to the row control circuit 202 and the column control circuit 203.

[0211] The data buffer 205 temporarily stores the read data from the memory cell array 201 and the write data from the input / output shift register 206 .

[0212] The input-output shift register 206 temporarily stores the signal DQ transmitted between the memory cell array 201 and the outside of the semiconductor device 200. The input-output shift register 206 sends address information to the address register 204. The input-output shift register 206 sends write data to the data buffer 205. The input-output shift register 206 sends read data supplied from the memory cell array 201 to the outside of the semiconductor device 200. The input-output shift register 206 can perform parallel-serial conversion of the data DQ.

[0213] The voltage generating circuit 207 generates a plurality of voltages for each of a write operation, a read operation, and an erase operation. The voltage generating circuit 207 supplies the generated voltages to the row control circuit 202, the column control circuit 203, and the like.

[0214] The sequencer 208 controls the overall operation of the semiconductor device 200 based on various control signals such as a reset signal RESETn, a hold signal HOLDn, and a write protection signal Wn.

[0215] The configuration of the semiconductor device 200 (NOR flash memory) is not limited thereto. The semiconductor device 200 may include other components such as a status register. The status register temporarily stores a status signal indicating the operation status inside the semiconductor device 200 and the execution result of the operation sequence.

[0216] In the semiconductor device 200 of the second configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1 , 1A, 1B, and 1C) described in the above embodiment can be applied to the sequencer 208 and the input / output shift register 206 .

[0217] <Third Configuration Example: DRAM (Dynamic Random Access Memory)>

[0218] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used in a volatile semiconductor memory device (e.g., DRAM). Hereinafter, as an example of such a DRAM, a semiconductor device 300 of the third configuration example of the fifth embodiment will be described.

[0219] Fig.23 1 is a block diagram showing an example of the configuration of a semiconductor device 300 (DRAM) according to the third configuration example of the fifth embodiment. Fig.23 As shown, the semiconductor device 300, for example, includes a memory cell array 301, a row decoder 302, a column decoder 303, a command decoder 304, an address decoder 305, a command / address input circuit 306, a sense amplifier circuit 307, a transmission gate 308, a read / write amplifier circuit (RWAMP: Read / Write Amplifier) ​​309, an input / output circuit 310, a clock input circuit 311, an internal clock generating circuit 312, and a voltage generating circuit 313.

[0220] The memory cell array 301 includes a plurality of memory cells MC. The memory cells MC of the semiconductor device 300 each include a cell capacitor CC and a cell transistor CT. The gate of the cell transistor CT is connected to a corresponding one of a plurality of word lines WL. One end of the current path of the cell transistor CT is connected to the bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is connected to a ground node. The cell capacitor CC can store an amount of charge corresponding to the data to be stored. The cell transistor CT switches the conduction / non-conduction between the memory cell MC and the bit line BL (selection / non-selection of the memory cell). The plurality of memory cells MC are arranged in a two-dimensional array or a three-dimensional array in the memory cell array 301. For example, the memory cell array 201 includes a plurality of storage libraries. Each storage library is a control unit including a plurality of memory cells MC. The plurality of storage libraries can operate independently of each other.

[0221] The row decoder 302 controls selection / non-selection of wiring (for example, word lines WL) in the row direction of the memory cell array 301 based on the decoding result of the address information and the decoding result of the command.

[0222] The column decoder 303 controls selection / non-selection of wiring (eg, bit lines BL) in the column direction of the memory cell array 301 based on the decoding result of the address information and the decoding result of the command.

[0223] The instruction decoder 304 decodes the instruction received from the instruction / address input circuit 306. The instruction decoder 304 sends the decoding result of the instruction to each of the row decoder 302 and the column decoder 303.

[0224] The address decoder 305 decodes the address information received from the command / address input circuit 306. The address decoder 305 transmits the decoded result of the address information to each of the row decoder 302 and the column decoder 303.

[0225] The command / address input circuit 306 receives a command / address signal CA supplied from the outside. The command / address signal CA includes command and address information. The command / address input circuit 306 sends the command and address information to the command decoder 304 and the address decoder 305, respectively.

[0226] The sense amplifier circuit 307 senses and amplifies the signal from the memory cell MC during the read operation. The sense amplifier circuit 307 transmits the signal from the memory cell MC as read data to the input / output circuit 310 via the transmission gate 308 and the RWAMP 309. The sense amplifier circuit 307 receives the write data from the input / output circuit 310 via the transmission gate 308 and the RWAMP 309. The sense amplifier circuit 307 outputs a signal corresponding to the write data to the bit line BL.

[0227] The transmission gate 308 controls the data transmission between the sense amplifier circuit 307 and the RWAMP 309 .

[0228] RWAMP 309 amplifies the level (signal value) of a signal corresponding to read data and the level of a signal corresponding to write data.

[0229] The input-output circuit 310 functions as an interface circuit for the signal DQ transmitted between the memory cell array 301 and the outside of the semiconductor device 300. The input-output circuit 310 transmits write data to the memory cell array 301 at a timing synchronized with the internal clock CLK2. The input-output circuit 310 transmits read data to an external device of the semiconductor device 300 at a timing synchronized with the internal clock CLK2. For example, the input-output circuit 310 receives a data mask signal DM. The input-output circuit 310 performs mask processing on the signal DQ (data) based on the data mask signal DM.

[0230] The clock input circuit 311 receives a clock (hereinafter referred to as an external clock) CLK1 from the outside and transmits the external clock CLK1 to the internal clock generation circuit 312 .

[0231] The internal clock generation circuit 312 generates the internal clock CLK2 based on the external clock CLK1. The internal clock generation circuit 312 sends the generated internal clock CLK2 to the input / output circuit 310 and the like.

[0232] The voltage generating circuit 313 uses external power supply voltage (voltage applied to the power supply node VDD and voltage applied to the ground node VSS) to generate a plurality of voltages for each of various operation sequences of the semiconductor device 300. The voltage generating circuit 313 transmits the generated voltage to other circuits (for example, RWAMP 309).

[0233] In the third configuration example of the fifth embodiment, the semiconductor device 300 is exemplified as a DRAM, but the present invention is not limited thereto. The semiconductor device 300 may be a random access memory other than a DRAM. For example, the semiconductor device 300 may be an SRAM (Static RAM).

[0234] In the semiconductor device 300 of the third configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the embodiment can be applied to the input / output circuit 310, the clock input circuit 311, and the internal clock generation circuit 312.

[0235] <Fourth Configuration Example: Cross-Point Memory>

[0236] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used in a cross-point memory. Hereinafter, a semiconductor device 400 of a fourth configuration example of a fifth embodiment will be described as an example of such a cross-point memory.

[0237] Fig.24 1 is a block diagram showing an example of the configuration of a semiconductor device 400 (cross-point memory) according to the fourth configuration example of the fifth embodiment. Fig.24 As shown, the semiconductor device 400 operates based on the control of the storage controller 410. The storage controller 410 can respond to commands from an external host machine and instruct the semiconductor device 400 to execute read operations, write operations, etc. The semiconductor device 400 is a memory device that uses MTJ (Magnetic Tunnel Junction) elements for storage cells, that is, a type of resistive memory. The MTJ element utilizes the magnetoresistance effect of the magnetic tunnel junction. The MTJ element is also called a magnetoresistance effect element. The semiconductor device 400 includes, for example, a storage cell array 401, an input-output circuit 402, a control circuit 403, a row selection circuit 404, a column selection circuit 405, a write circuit 406, and a read circuit 407.

[0238] The memory cell array 401 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Fig.24 A group of memory cells MC, word lines WL, and bit lines BL are shown. The memory cells MC can store data in a non-volatile manner. The memory cells MC are connected between a word line WL and a bit line BL, and correspond to a group of rows and columns. A row address is assigned to the word line WL. A column address is assigned to the bit line BL. One or more memory cells MC can be specified by selecting a row and one or more columns.

[0239] The input-output circuit 402 is connected to the memory controller 410, and manages the communication between the semiconductor device 400 and the memory controller 410. The input-output circuit 402 transmits the control signal CNT and the command CMD received from the memory controller 410 to the control circuit 403. The input-output circuit 402 transmits the row address and the column address included in the address signal ADD received from the memory controller 410 to the row selection circuit 404 and the column selection circuit 405, respectively. The input-output circuit 402 transmits the data DAT received from the memory controller 410 to the write circuit 406. The input-output circuit 402 transmits the data DAT received from the read circuit 407 to the memory controller 2.

[0240] The control circuit 403 controls the overall operation of the semiconductor device 400. For example, the control circuit 403 performs a read operation or a write operation based on the control and command CMD indicated by the control signal CNT. For example, in a write operation, the control circuit 403 generates a voltage used for writing data and supplies it to the write circuit 406. In addition, in a read operation, the control circuit 403 generates a voltage used for reading data and supplies it to the read circuit 407.

[0241] The row selection circuit 404 is connected to a plurality of word lines WL. The row selection circuit 404 selects one word line WL specified by a row address. The selected word line WL is electrically connected to a driver circuit (not shown).

[0242] The column selection circuit 405 is connected to a plurality of bit lines BL. The column selection circuit 405 selects one or more bit lines BL specified by a column address. The selected bit line BL is electrically connected to a driver circuit (not shown).

[0243] The write circuit 406 supplies a voltage used for writing data to the column selection circuit 405 based on the control of the control circuit 403 and the data DAT (data required to be written) received from the input / output circuit 402. When a current based on the data DAT flows through the memory cell MC, the desired data is written to the memory cell MC.

[0244] The read circuit 407 includes a sense amplifier. The read circuit 407 supplies a voltage used for data read to the column selection circuit 405 based on the control of the control circuit 403. The sense amplifier determines the data stored in the memory cell MC based on the voltage or current of the selected bit line BL. Then, the read circuit 407 sends the data DAT (data read from the memory cell array 401) corresponding to the determination result to the input / output circuit 402.

[0245] In addition, in the fourth configuration example of the fifth embodiment, although the semiconductor device 400 is illustrated as an MRAM, it is not limited to this. The semiconductor device 400 can also be other resistive memory. For example, the semiconductor device 400 can be a memory device that uses a transition metal oxide element with a variable resistance characteristic as a memory element (for example, a resistive memory such as ReRAM (Resistive Random Access Memory)), a memory device that uses a phase change element as a memory element (for example, a phase change memory such as PCRAM (Phase Change Random Access Memory)), or a memory device that uses a ferroelectric element as a memory element (for example, a ferroelectric memory such as FeRAM (Ferroelectric Random Access Memory)).

[0246] In the semiconductor device 400 of the fourth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3 , 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output circuit 402 and the control circuit 403 .

[0247] <Fifth Configuration Example: Image Sensor>

[0248] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used in an image sensor. Hereinafter, as an example of such an image sensor, a semiconductor device 500 of a fifth configuration example of a fifth embodiment will be described.

[0249] Fig.25 FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device 500 (image sensor) according to a fifth configuration example of the fifth embodiment. Fig.25 As shown, the semiconductor device 500 includes, for example, a pixel array 501 , a row scanning circuit 502 , a column processing circuit 503 , a column scanning circuit 504 , a system control circuit 505 , and a signal processing circuit 506 .

[0250] The pixel array 501 has a plurality of pixels PX. The plurality of pixels PX are arranged in a two-dimensional grid shape along the row direction and the column direction. Each pixel PX has a photoelectric conversion element. The photoelectric conversion element generates a charge corresponding to the amount of light received and accumulates the generated charge. A filter can be set in the pixel array 501 for the light incident surface of each pixel PX. For example, the arrangement pattern of the plurality of filters is, for example, a Bayer pattern. In the pixel array 501, the plurality of pixels PX arranged in the row direction are connected in common to the pixel drive line PDL. In the pixel array 501, the plurality of pixels PX arranged in the column direction are connected in common to a corresponding one of the plurality of vertical signal lines VSL.

[0251] The row scanning circuit 502 is connected to one end of a plurality of pixel drive lines PDL. The row scanning circuit 502 generates a drive signal for performing signal readout drive from the pixel PX. The row scanning circuit 502 drives all pixels PX of the pixel array 501 simultaneously or in row units via the plurality of pixel drive lines PDL. The signals output from the plurality of pixels PX driven by the row scanning circuit 502 are supplied to the column processing circuit 903 via the corresponding vertical signal line VSL for each pixel PX arranged in the row direction.

[0252] The column processing circuit 503 performs a designated signal processing on the signal supplied via the vertical signal line VSL. Thus, the column processing circuit 503 can generate a pixel signal. In addition, the column processing circuit 503 can temporarily store the generated pixel signal. The column processing circuit 503 can perform, for example, noise removal processing or analog-to-digital conversion (AD (Analog / Digital) conversion) processing. The digital signal obtained by the AD conversion is output to the signal processing circuit 506.

[0253] The column scanning circuit 504 sequentially selects readout circuits corresponding to the arrangement of pixel signals of the column processing circuit 503. Through the selective scanning by the column scanning circuit 504, the column processing circuit 503 outputs pixel signals subjected to signal processing for each pixel based on a specified order.

[0254] The system control circuit 505 receives a system clock signal and the like via a controller (not shown) outside the semiconductor device 500. The system control circuit 505 includes a timing generator and the like. The timing generator generates various timing signals based on the system clock signal. Thus, the system control circuit 505 drives the row scanning circuit 502, the column processing circuit 503, the column scanning circuit 504, and the like based on the generated various timing signals.

[0255] The signal processing circuit 506 has at least an arithmetic processing function and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing circuit 503 .

[0256] The digital signal output from the signal processing circuit 506 is output to the image processing circuit 507 outside the semiconductor device 500. The image processing circuit 507 performs a predetermined process on the digital signal and generates an image signal for displaying an image on a predetermined display device.

[0257] In the semiconductor device 500 of the fifth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3 , 3A, 3B, and 3C) described in the above embodiment can be applied to the system control circuit 505 that receives the system clock signal.

[0258] <Sixth Configuration Example: Communication Interface>

[0259] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used for a communication interface. Hereinafter, as an example of such a communication interface, a semiconductor device 600 of the sixth configuration example of the fifth embodiment will be described. In addition, the communication interface can be a circuit corresponding to a wired connection such as light or Ethernet (registered trademark), or a circuit corresponding to a wireless connection such as RF (Radio Frequency).

[0260] Fig.26 1 is a block diagram showing an example of the configuration of a semiconductor device 600 (communication interface) according to a sixth configuration example of the fifth embodiment. Fig.26 As shown, the semiconductor device 600 is a differential transmission type input / output interface circuit (e.g., a transceiver). Specifically, the semiconductor device 600 includes input / output terminals 601A and 601B, resistor-capacitor (RC) circuits 602A and 602B, an analog-to-digital (AD) conversion circuit 603, capacitor circuits 604A and 604B, a digital-to-analog (DA) conversion circuit 605, a current sink circuit 606, a clock phase adjustment circuit 607, a control clock generation circuit 608, an input monitor 609, an input / output monitor 610, a PVT (Process Voltage Temperature) monitor 611, a global bias generation circuit 612, bias generation circuits 613 and 614, and an input / output control circuit 615.

[0261] The input / output terminals 601A and 601B are paired differential input / output terminals. The semiconductor device 600 can transmit and receive differential signals IO+ and IO- via the input / output terminals 601A and 601B, respectively. The two differential signals IO+ and IO- have a complementary relationship. In addition, the two input / output terminals 601A and 601B paired for differential transmission can also be called a differential input / output terminal pair. The pair of signal lines used for differential transmission in the semiconductor device 600 can also be called a differential transmission line.

[0262] RC circuits 602A and 602B are provided corresponding to input / output terminals 601A and 601B, respectively. RC circuit 602A is connected to the signal path of input / output terminal 601A. RC circuit 602B is connected to the signal path of input / output terminal 601B. RC circuits 602A and 602B control the time constant associated with the supplied signal. RC circuits 602A and 602B are circuits that include resistors and capacitors and can be designed (programmed) after installation. RC circuits can be called RC networks.

[0263] The AD conversion circuit 603 receives differential signals IO+ and IO- input to the semiconductor device 600 via the RC circuits 602A and 602B. The AD conversion circuit 603 receives reference signals IOMVR+ and IOMVR- from the bias generation circuit 613. The AD conversion circuit 603 converts the signals IO+ and IO- from analog signals to digital signals based on the reference signals IOMVR+ and IOMVR-.

[0264] The capacitor circuit 604A is provided between the RC circuit 602A and the DA conversion circuit 605. The capacitor circuit 604B is provided between the RC circuit 602B and the DA conversion circuit 605. The capacitor circuit 604A is connected to the RC circuit 602A. The capacitor circuit 604B is connected to the RC circuit 602B. The capacitor circuits 604A and 604B include a plurality of capacitors. The capacitor circuits 604A and 604B smooth the signal.

[0265] The DA conversion circuit 605 receives a digital signal. The DA conversion circuit 605 receives reference signals IOMVR+ and IOMVR- from the bias generation circuit 613. The DA conversion circuit 605 generates analog signals DACOUT+ and DACOUT- based on the received digital signal and the reference signals IOMVR+ and IOMVR-. The analog signals DACOUT+ and DACOUT- are signals having a complementary relationship. The DA conversion circuit 605 sends the generated analog signal DACOUT+ to the input-output terminal 601A via the capacitor circuit 604A and the RC circuit 602A. The DA conversion circuit 605 sends the generated analog signal DACOUT- to the input-output terminal 601B via the capacitor circuit 604B and the RC circuit 602B. As a result, the signals DACOUT+ and DACOUT- are output to the outside of the semiconductor device 600 as differential signals IO+ and IO-, respectively. In addition, the DA conversion circuit 605 sends the analog signals DACOUT+ and DACOUT- to the current sink circuit 606.

[0266] The current sink circuit 606 controls the magnitude of the current flowing through the input / output terminal 601 and the signal line to be within a range permitted based on the standards of the communication interface.

[0267] The clock phase adjustment circuit 607 adjusts the phase of the reference clock signal to generate various clock signals used in the semiconductor device 600 .

[0268] The control clock generation circuit 608 adjusts the phase of the reference clock signal and generates various clock signals used in the semiconductor device 600 .

[0269] The input monitor 609 monitors each of the signal IO+ of the input / output terminal 601A and the signal IO- of the input / output terminal 601B.

[0270] The input / output monitor 610 monitors a plurality of clock signals received from the control clock generation circuit 608 .

[0271] The PVT monitor 611 monitors various bandgap voltages and bias voltages in the semiconductor device 600. The bandgap voltage is a voltage (reference voltage) that serves as a reference for the voltage amplitude of a signal. The bias voltage is a voltage used for the operation of each circuit block in the semiconductor device 600.

[0272] The global bias generating circuit 612 generates a main bias voltage for each circuit block in the semiconductor device 600 .

[0273] The bias generating circuit 613 generates a voltage that serves as a reference for the bias voltage (bias signal) of the AD conversion circuit 603 and the DA conversion circuit 605 .

[0274] The bias generating circuit 614 generates a bias voltage for the AD conversion circuit 603 and the input / output control circuit 615 .

[0275] The input / output control circuit 615 generates a control signal for each circuit block in the semiconductor device 600. The input / output control circuit 615 supplies the generated control signal to each circuit block.

[0276] In the semiconductor device 600 of the sixth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the control clock generation circuit 608. In addition, in the semiconductor device 600 of the sixth configuration example of the fifth embodiment, the differential amplifier circuit (semiconductor circuits 2, 2A, 2B, and 2C) described in the above embodiment can be applied to circuits that process differential signals (for example, the AD conversion circuit 603, the DA conversion circuit 605, the current sink circuit 606, the input monitor 609, and the bias generation circuit 613).

[0277] <Seventh Configuration Example: Wireless Device>

[0278] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used in a wireless device. Hereinafter, a semiconductor device 700 according to a seventh configuration example of the fifth embodiment will be described as an example of such a wireless device.

[0279] Fig. 27 1 is a block diagram showing an example of the configuration of a semiconductor device 700 (wireless device) according to a seventh configuration example of the fifth embodiment. Fig. 27 As shown, the semiconductor device 700 includes, for example, an upper layer 710 , a transmission unit 720 , a switching unit 730 , a reception unit 740 , a reference clock generation circuit 750 , and a clock generation circuit 760 .

[0280] The upper layer 710 is a functional block that processes frames sent and received by the semiconductor device 700. The upper layer 710 can perform, for example, MAC (Media Access Control) layer processing. For example, the upper layer 710 generates frames using the traffic generated by the application of the wireless device, and inputs the generated frames to the transmission unit 720. In addition, the upper layer 710 extracts data from the frames received by the receiving unit 740, and inputs the extracted data to the application.

[0281] The transmitting unit 720 converts the frame input from the upper layer 710 into a wireless signal and transmits it via the antenna. The transmitting unit 720 includes, for example, a modulator 721, a frequency converter 722, and an amplifier 723. The modulator 721 inputs the signal modulated by the input frame to the frequency converter 722. The frequency converter 722 converts the frequency of the input signal into a desired frequency and inputs it to the amplifier 723. The amplifier 723 is an SSPA (Solid State Power Amplifier) ​​that amplifies the input signal. The amplifier 723 includes, for example, an amplifier circuit, an isolator, and a low-pass filter. The signal output from the amplifier 723 is radiated from the antenna via the switch 730.

[0282] The switch unit 730 is a circuit that can switch the connection with the antenna between the transmission unit 720 and the reception unit 740 .

[0283] The receiving unit 740 extracts a frame from the wireless signal received via the antenna and inputs it to the upper layer 710. The receiving unit 740 includes, for example, an amplifier 741, a frequency converter 742, and a demodulator 743. The amplifier 741 amplifies the signal received via the antenna and inputs it to the frequency converter 742. The amplifier 741 includes, for example, a bandpass filter and an amplifier circuit. The frequency converter 742 converts the frequency of the input signal to a desired frequency and inputs it to the demodulator 743. The demodulator 743 demodulates the input signal and extracts the frame included in the wireless signal. Furthermore, the demodulator 743 inputs the extracted frame to the upper layer 710.

[0284] The reference clock generation circuit 750 generates a reference clock signal used by the semiconductor device 700 .

[0285] The clock generation circuit 760 generates a plurality of clock signals used by the semiconductor device 700 based on the reference clock signal. The clock generation circuit 760 inputs the generated clock signals to the modulator 721, the frequency converters 722 and 742, and the demodulator 743, for example.

[0286] In the semiconductor device 700 according to the seventh configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1 , 1A, 1B, and 1C) described in the above embodiment can be applied to the demodulator 743 .

[0287] <Configuration Example No. 8: Micro Controller>

[0288] At least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C described in the first to fourth embodiments can be used in a microcontroller. Hereinafter, a semiconductor device 800 according to an eighth configuration example of the fifth embodiment will be described as an example of such a microcontroller.

[0289] Fig.28 1 is a block diagram showing an example of the configuration of a semiconductor device 800 (microcontroller) according to an eighth configuration example of the fifth embodiment. Fig.28As shown, the semiconductor device 800 includes, for example, a processor 801, a bus control circuit 802, a flash memory 803, a RAM (Random Access Memory) 804, a DA conversion circuit 805, an AD conversion circuit 806, a timer 807, an input / output (I / O) port 808, an oscillator 809, and an insertion controller 810. The bus of the semiconductor device 800 is connected to the processor 801, the bus control circuit 802, the flash memory 803, the RAM 804, the DA conversion circuit 805, the AD conversion circuit 806, the timer 807, and the input / output port 808. The bus of the semiconductor device 800 is a transmission path for signals and data within the semiconductor device 800.

[0290] The processor 801 executes various processes in the semiconductor device 800. The processor 801 performs various processes on supplied data. The processor 801 is, for example, a CPU (Central Processing Unit).

[0291] The bus control circuit 802 controls the bus of the semiconductor device 800. The bus control circuit 802 can be provided in the processor 801.

[0292] The flash memory 803 is a storage device capable of storing data in a nonvolatile manner. The flash memory 803 is, for example, a NOR flash memory. Alternatively, the flash memory 803 may be a NAND flash memory.

[0293] The RAM 804 is a storage device for temporarily storing data and is, for example, a random access memory such as an SRAM or a DRAM.

[0294] The DA conversion circuit 805 converts a digital signal (digital value) into an analog signal (analog value).

[0295] The AD conversion circuit 806 converts the analog signal into a digital signal.

[0296] The timer 807 manages the time (operation timing) within the semiconductor device 800 .

[0297] The input / output port 808 functions as an interface circuit in the semiconductor device 800. The input / output port 808 includes, for example, four ports P1, P2, P3, and P4. The number of ports provided by the input / output port 808 may be three or less, or five or more. The input / output port 808 receives a signal including data or an address from the outside of the semiconductor device 800 via each of the ports P1, P2, P3, and P4. The input / output port 808 transmits a signal including data or the like to the outside of the semiconductor device 800 via each of the ports P1, P2, P3, and P4. The input / output port 808 complies with, for example, the GPIO (General purpose input / output) standard, the USART (Universal synchronous / asynchronous receiver transmitter) standard, or the I2C (Inter-integrated circuit) standard.

[0298] The oscillator 809 outputs a clock signal as a synchronization signal to the processor 801. The clock signal has a certain period (number of clocks). Thus, the processor 801 performs various processes in synchronization with the clock signal. The period of the clock signal is, for example, 4 MHz, 8 MHz, 12 MHz, or 24 MHz.

[0299] The insertion controller 810 receives an external insertion command. For example, the insertion controller 810 has a register for managing the state of the insertion request. Based on the received external insertion command, the insertion controller 810 sends various insertion requests to the processor 801. According to the insertion request, the processor 801 temporarily interrupts the processing being executed and executes the processing of the insertion request. After the processing of the insertion request is completed, the processor 801 resumes the interrupted processing.

[0300] In addition, in the semiconductor device 800 of the eighth configuration example of the fifth embodiment, the microcontroller 1C of this embodiment can also be a system on chip (SoC), a system in package (SIP), or a system on package (SoP). The semiconductor device 800 is used, for example, in an integrated system. The semiconductor device 800 is used, for example, in vehicle-mounted devices, home appliances, computers, industrial machinery, railway vehicles, airplanes, and ships.

[0301] In addition, the semiconductor device 800 can also be classified based on bus width, memory structure, and command group. The bus width shows the size of the data bus. For example, the semiconductor device 800 is classified as an 8-bit microcontroller, a 16-bit microcontroller, or a 32-bit microcontroller based on the bus width. The semiconductor device 800 can obtain better performance through a higher bus width.

[0302] In the semiconductor device 800 of the eighth configuration example of the fifth embodiment, for example, the CTLE (semiconductor circuits 3, 3A, 3B, and 3C) described in the above embodiment can be applied to the input / output port 808. In addition, in the semiconductor device 800 of the eighth configuration example of the fifth embodiment, for example, the C2C circuit (semiconductor circuits 1, 1A, 1B, and 1C) described in the above embodiment can be applied to the processor 801.

[0303] <5-2> Effects of the Fifth Embodiment

[0304] As the storage capacity of NAND flash memory increases, the frequency of signals sent and received between the semiconductor storage device and the storage controller increases, making it difficult to transfer data in the signal transmission circuit within the input / output circuit 102. For example, since the wiring lengths from the WDCA 113 to each data input circuit 114 are different, skew may be uneven in each of the multiple data input circuits 114 that receive different signals DQ.

[0305] Therefore, in the first configuration example of the fifth embodiment, the input / output circuit 102 of the semiconductor device 100 (NAND flash memory) includes the C2C circuit described in the above embodiment. As a result, the input / output circuit 102 can reduce the gain near the DC, and can suppress the unevenness of the skew in each data input circuit 114. As a result, the semiconductor device 100 of the first configuration example of the fifth embodiment can use a high-frequency signal and can achieve high-speed transmission of data and the like with the storage controller 110.

[0306] In addition, the second to eighth configuration examples of the fifth embodiment are the same as the first configuration example of the fifth embodiment, and can achieve high-speed signal transmission by utilizing at least one of the C2C circuit, differential amplifier circuit, and CTLE described in the first to fourth embodiments, that is, at least one of the semiconductor circuits 1, 1A to 1C, 2, 2A to 2C, 3, and 3A to 3C.

[0307] <6>Others

[0308] In this specification, a voltage of "H" level corresponds to a voltage above the threshold when judging data as binary values. A voltage of "L" level corresponds to a voltage below the threshold when judging data as binary values. In this specification, "logic level" corresponds to either "H" level or "L" level. In this specification, "connection" means electrical connection, for example, it does not exclude the presence of other elements in between. "Electrically connected" can also be separated by an insulator as long as it can operate in the same way as the electrically connected.

[0309] In this specification, each of one end and the other end of a transistor corresponds to a source terminal or a drain terminal of the transistor. In this specification, "conductivity type" corresponds to "N-type" or "P-type". For example, the first conductivity type transistor corresponds to one of the N-type transistor and the P-type transistor, and the second conductivity type transistor corresponds to the other of the N-type transistor and the P-type transistor. One end and the other end can also be referred to as "the first end" and "the second end". The ground node VSS can also be referred to as a power supply node. The input end and the output end of the constant current source CS correspond to one end and the other end of the current path of the constant current source CS, respectively. One end of the constant current source CS corresponds to one of the input end and the output end, and the other end of the constant current source CS corresponds to the other of the input end and the output end.

[0310] In the embodiment, each of the constant current sources CS10, CS20, CS30 and CS31 is, for example, composed of one N-type MOS transistor. Each of the constant current sources CS11, CS12, CS21, CS32 and CS33 is, for example, composed of one P-type MOS transistor. In addition, the constant current source CS can also be composed of a plurality of transistors. For example, the constant current source CS can also have a current mirror circuit including two transistors. In this case, each of the constant current sources CS10, CS20, CS30 and CS31 has a current mirror circuit composed of an N-type MOS transistor, and each of the constant current sources CS11, CS12, CS21, CS32 and CS33 has a current mirror circuit composed of a P-type MOS transistor.

[0311] Fig.29 1 is a circuit diagram showing an example of a circuit configuration of a constant current source CS (hereinafter referred to as a constant current source CSN) composed of N-type transistors. Fig.29As shown, the constant current source CSN has, for example, N-type transistors NM90 and NM91, and nodes ND90 to ND92. The drain terminal and gate terminal of the N-type transistor NM90 are connected to the node ND90. The drain terminal of the N-type transistor NM91 is connected to the node ND91. The gate terminal of the N-type transistor NM91 is connected to the node ND90. The source terminal of each of the N-type transistors NM90 and NM91 is connected to the node ND92. The node ND92 is connected to the ground node VSS, for example. In the constant current source CSN, the voltage of the node ND90 is controlled in such a way that the current flowing through the N-type transistor NM91 is constant. That is, the input terminal of the constant current source CSN corresponds to the node ND91. The output terminal of the constant current source CSN corresponds to the node ND92.

[0312] Fig.30 1 is a circuit diagram showing an example of a circuit configuration of a constant current source CS (hereinafter referred to as a constant current source CSP) composed of a P-type transistor. Fig.30 As shown, the constant current source CSP has, for example, P-type transistors PM90 and PM91, and nodes ND93 to ND95. Node ND93 is connected to the power supply node VDD. The source terminal of each of the P-type transistors PM90 and PM91 is connected to the node ND93. The gate terminal and the drain terminal of the P-type transistor PM90 are connected to the node ND94. The gate terminal of the P-type transistor PM91 is connected to the node ND94. The drain terminal of the P-type transistor PM91 is connected to the node ND95. In the constant current source CSP, the voltage of the node ND94 is controlled in such a way that the current flowing through the P-type transistor PM91 is constant. That is, the input terminal of the constant current source CSP corresponds to the node ND93. The output terminal of the constant current source CSP corresponds to the node ND95.

[0313] In this specification, for example, in the case of a planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the size of the transistor is compared using the gate width. In this specification, for example, in the case of a FinFET (Fin Field Effect Transistor), the size of the transistor is compared using the number of fins. In this specification, for example, in the case of a Nanosheet transistor, the size of the transistor is compared using the number of semiconductor layers, i.e., the number of stacked layers of the Nanosheet.

[0314] In FinFET, the gate electrode faces more than two sides of the channel region. The channel region is formed in a convex shape formed on the surface of the semiconductor substrate, and the convex semiconductor region is called a fin. It is also possible to have multiple fins in a transistor. When the number of fins in one transistor is less than the number of fins in another transistor, one transistor is smaller than the other transistor. When the ratio of the size of one transistor (for example, P-type transistor PM12) to the size of another transistor (for example, P-type transistor PM10) is 1:1.2~7, for example, if the number of fins of one transistor is set to 1, the number of fins of the other transistor is 2~7, and if the number of fins of one transistor is set to 2, the number of fins of the other transistor is 3~14.

[0315] In the Nanosheet, the gate electrodes face each other in a manner of surrounding the channel region. The channel region is formed in a flat-plate-shaped semiconductor layer (Nanosheet). The flat-plate-shaped semiconductor layer can also be stacked separately in multiple layers. When the number of semiconductor layers in one transistor is less than the number of semiconductor layers in another transistor, one transistor is smaller than the other transistor. When the ratio of the size of one transistor (for example, a P-type transistor PM12) to the size of another transistor (for example, a P-type transistor PM10) is 1:1.2 to 7, for example, if the semiconductor layer of one transistor is set to 1 layer, then the semiconductor layer of the other transistor is 2 to 7 layers, and if the semiconductor layer of one transistor is set to 2 layers, then the number of semiconductor layers of the other transistor is 3 to 14 layers.

[0316] In this specification, "NMOS-based" means that the transistor receiving the input signal is an N-type transistor. "PMOS-based" means that the transistor receiving the input signal is a P-type transistor. CML (Current Mode Logic) is a circuit that transmits small analog signals. CMOS strictly means a CMOS inverter and a circuit that transmits large digital signals. A C2C circuit corresponds to a circuit that converts small analog signals to large digital signals. A fixed pattern of continuous "L" level signals or a pattern of continuous "H" level signals can be regarded as a DC signal.

[0317] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or purpose of the invention, and are included in the invention described in the scope of the patent application and its equivalent.

Claims

1. A semiconductor circuit comprising: 1st to 3rd transistors of the first conductivity type; first and second second conductivity type transistors; and a constant current source; and One end and the other end of the first first-conductivity-type transistor are connected to a first power supply node and a first node, respectively, and a gate end of the first first-conductivity-type transistor is connected to the first node via a resistor; One end and the other end of the second first-conductivity-type transistor are connected to the first power supply node and the second node respectively, the second node is connected to the output node, and the gate end of the second first-conductivity-type transistor is connected to the first node; One end and the other end of the first second conductivity type transistor are connected to the first node and the third node respectively, and the gate end of the first second conductivity type transistor is connected to the first input node; One end and the other end of the second second-conductivity-type transistor are connected to the second node and the third node respectively, and a gate end of the second second-conductivity-type transistor is connected to a second input node; One end and the other end of the constant current source are connected to the third node and the second power supply node respectively; One end and the other end of the third first-conductivity-type transistor are connected to the first power supply node and the second input node, respectively, and a gate end of the third first-conductivity-type transistor is connected to a gate end of the first first-conductivity-type transistor.

2. The semiconductor circuit according to claim 1, wherein The first conductivity type is P type; The second conductivity type is N type; and A voltage higher than a voltage of the second power supply node is applied to the first power supply node.

3. The semiconductor circuit according to claim 1, wherein The first conductivity type is N type; The second conductivity type is P type; and A voltage lower than a voltage of the second power supply node is applied to the first power supply node.

4. The semiconductor circuit according to claim 1, further comprising: 4th to 6th transistors of the first conductivity type; and One end and the other end of the fourth first-conductivity-type transistor are connected to the first power supply node and the second input node respectively, and the gate end of the fourth first-conductivity-type transistor is connected to the gate end of the first first-conductivity-type transistor; The fifth first-conductivity-type transistor is connected between the first power supply node and the third first-conductivity-type transistor; The sixth transistor of the first conductivity type is connected between the first power supply node and the fourth transistor of the first conductivity type; Different control signals are input to the gate terminal of the fifth first-conductivity-type transistor and the gate terminal of the sixth first-conductivity-type transistor.

5. The semiconductor circuit according to claim 1, wherein The third first conductivity type transistor is smaller than the first first conductivity type transistor.

6. The semiconductor circuit according to claim 1, wherein inputting a first clock signal to the first input node; and The second input node receives an inverted signal of the first clock signal, that is, a second clock signal.

7. A semiconductor device comprising: A data input circuit comprising the semiconductor circuit according to claim 6; A first pad connected to the data input circuit to receive a first signal from the outside; A second pad receives a second signal from the outside; The third pad receives a third signal from the outside; an amplifier circuit, generating the first clock signal based on the second signal and the third signal; and a processing circuit that processes the data output from the data input circuit; and The data input circuit samples the first signal based on the first clock signal, and outputs the sampled data to the processing circuit.

8. The semiconductor device according to claim 7, wherein The data input circuit has: a conversion circuit, converting the first clock signal amplified by the semiconductor circuit into a CMOS level; a continuous time linear equalizer, compensating the first signal and outputting the same; and The sampler samples the output signal of the continuous time linear equalizer based on the first clock signal converted into a CMOS level by the conversion circuit, and outputs the sampled data to the processing circuit.

9. A semiconductor circuit comprising: 1st to 4th transistors of the first conductivity type; first and second second conductivity type transistors; and a constant current source; and One end and the other end of the first first-conductivity-type transistor are connected to a first power supply node and a first node respectively, a gate end of the first first-conductivity-type transistor is connected to the first node via a first resistor, and the first node is connected to a first output node; One end and the other end of the second first-conductivity-type transistor are connected to the first power supply node and the second node, respectively; a gate end of the second first-conductivity-type transistor is connected to the second node via a second resistor different from the first resistor; and the second node is connected to a second output node; One end and the other end of the first second conductivity type transistor are connected to the first node and the third node respectively, and the gate end of the first second conductivity type transistor is connected to the first input node; One end and the other end of the second second-conductivity-type transistor are connected to the second node and the third node respectively, and a gate end of the second second-conductivity-type transistor is connected to a second input node; One end and the other end of the constant current source are connected to the third node and the second power supply node respectively; One end and the other end of the third first-conductivity-type transistor are connected to the first power supply node and the second input node respectively, and the gate end of the third first-conductivity-type transistor is connected to the gate end of the first first-conductivity-type transistor; One end and the other end of the fourth first-conductivity-type transistor are connected to the first power supply node and the first input node, respectively, and a gate end of the fourth first-conductivity-type transistor is connected to the gate end of the second first-conductivity-type transistor.

10. The semiconductor circuit according to claim 9, wherein The first conductivity type is P type; The second conductivity type is N type; and A voltage higher than a voltage of the second power supply node is applied to the first power supply node.

11. The semiconductor circuit according to claim 9, wherein The first conductivity type is N type; The second conductivity type is P type; and A voltage lower than a voltage of the second power supply node is applied to the first power supply node.

12. The semiconductor circuit according to claim 9, further comprising: The fifth to seventh transistors of the first conductivity type; and One end and the other end of the fifth first-conductivity-type transistor are connected to the first power supply node and the second input node respectively, and the gate end of the fifth first-conductivity-type transistor is connected to the gate end of the first first-conductivity-type transistor; The sixth first-conductivity-type transistor is connected between the first power supply node and the third first-conductivity-type transistor; The seventh first-conductivity-type transistor is connected between the first power supply node and the fifth first-conductivity-type transistor; Different control signals are input to the gate terminal of the sixth first-conductivity-type transistor and the gate terminal of the seventh first-conductivity-type transistor.

13. The semiconductor circuit according to claim 12, further comprising: 8th to 10th transistors of the first conductivity type; and One end and the other end of the eighth first-conductivity-type transistor are connected to the first power supply node and the first input node, respectively, and a gate end of the eighth first-conductivity-type transistor is connected to the gate end of the second first-conductivity-type transistor; The ninth transistor of the first conductivity type is connected between the first power supply node and the fourth transistor of the first conductivity type; The tenth first-conductivity-type transistor is connected between the first power supply node and the eighth first-conductivity-type transistor; Different control signals are input to the gate terminal of the ninth first-conductivity-type transistor and the gate terminal of the tenth first-conductivity-type transistor.

14. A semiconductor circuit comprising: first and second transistors of the first conductivity type; first and second second conductivity type transistors; 1st to 3rd resistors; capacitors; and a first and a second constant current source; and The first resistor is connected between a first power supply node and a first node, and the first node is connected to a first output node; The second resistor is connected between the first power supply node and a second node, and the second node is connected to a second output node; One end and the other end of the first second conductivity type transistor are connected to the first node and the third node respectively, and the gate end of the first second conductivity type transistor is connected to the first input node; One end and the other end of the second second-conductivity-type transistor are connected to the second node and the fourth node respectively, and the gate end of the second second-conductivity-type transistor is connected to the second input node; One end and the other end of the first constant current source are connected to the third node and the second power supply node respectively; One end and the other end of the second constant current source are connected to the fourth node and the second power supply node respectively; The third resistor and the capacitor are connected in parallel between the third node and the fourth node; One end and the other end of the first first-conductivity-type transistor are connected to the first power supply node and the second input node respectively, and a gate end of the first first-conductivity-type transistor is connected to the first node; One end and the other end of the second first-conductivity-type transistor are connected to the first power supply node and the first input node, respectively, and a gate end of the second first-conductivity-type transistor is connected to the second node.

15. The semiconductor circuit according to claim 14, wherein The first conductivity type is P type; The second conductivity type is N type; and A voltage higher than a voltage of the second power supply node is applied to the first power supply node.

16. The semiconductor circuit according to claim 14, wherein The first conductivity type is N type; The second conductivity type is P type; and A voltage lower than a voltage of the second power supply node is applied to the first power supply node.

17. The semiconductor circuit according to claim 14, further comprising: third to fifth transistors of the first conductivity type; and One end and the other end of the third first-conductivity-type transistor are connected to the first power supply node and the second input node respectively, and the gate end of the third first-conductivity-type transistor is connected to the gate end of the first first-conductivity-type transistor; The fourth first-conductivity-type transistor is connected between the first power supply node and the first first-conductivity-type transistor; The fifth first-conductivity-type transistor is connected between the first power supply node and the third first-conductivity-type transistor; Different control signals are input to the gate terminal of the fourth first-conductivity-type transistor and the gate terminal of the fifth first-conductivity-type transistor.

18. The semiconductor circuit according to claim 17, further comprising: The sixth to eighth transistors of the first conductivity type; and One end and the other end of the sixth first-conductivity-type transistor are connected to the first power supply node and the first input node, respectively, and a gate end of the sixth first-conductivity-type transistor is connected to the gate end of the second first-conductivity-type transistor; The seventh first-conductivity-type transistor is connected between the first power supply node and the second first-conductivity-type transistor; The eighth first-conductivity-type transistor is connected between the first power supply node and the sixth first-conductivity-type transistor; Different control signals are input to the gate terminal of the seventh first-conductivity-type transistor and the gate terminal of the eighth first-conductivity-type transistor.

19. A semiconductor device comprising: A data input circuit comprising the semiconductor circuit according to claim 14; A first pad connected to the first input node to receive a first signal from the outside; A second pad receives a second signal from the outside; The third pad receives a third signal from the outside; an amplifier circuit that generates a clock signal based on the second signal and the third signal; and a processing circuit that processes the data output from the data input circuit; and The data input circuit includes a sampler that samples an output signal of the semiconductor circuit generated based on the first signal based on the clock signal, and outputs the sampled data to the processing circuit.

20. The semiconductor device according to claim 19, wherein The data input circuit includes a plurality of the semiconductor circuits; and The plurality of semiconductor circuits are connected in series between the first pad and the sampler.

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