Light detection element and electronic device

Abstract

The light detection element includes: a plurality of pixels arranged in a planar direction; and a partition portion extending between adjacent pixels in a direction intersecting the planar direction to partition the adjacent pixels among the plurality of pixels from each other, in which the plurality of pixels includes a photoelectric conversion element and a plurality of transistors, respectively, and in a plan view, the photoelectric conversion element is electrically connected to the plurality of transistors. Gate electrodes of respective specific transistors among the plurality of transistors of respective adjacent pixels are provided facing each other with a partition therebetween, and are connected to each other across the partition.

Description

Technical Field

[0001] The present invention relates to a light detecting element and an electronic device. Background Art

[0002] For example, Patent Document 1 discloses an image pickup device provided with a partition that partitions adjacent pixels from each other. Citation list Patent Literature

[0003] Patent Document 1: JP 2020-194912 Summary of the invention Technical problem to be solved by the invention

[0004] The presence of the partition limits the arrangement of the photoelectric conversion elements and transistors within the pixel and reduces layout efficiency.

[0005] One aspect of the present invention improves layout efficiency. Technical means to solve technical problems

[0006] According to one aspect of the present invention, a light detection element includes: a plurality of pixels arranged along a planar direction; and a partition portion extending between adjacent pixels among the plurality of pixels along a direction intersecting the planar direction to separate the adjacent pixels from each other, wherein each of the plurality of pixels includes a photoelectric conversion element and a plurality of transistors, and in a plan view, gate electrodes of specific transistors among the plurality of transistors of each of the adjacent pixels are arranged opposite to each other across the partition portion and are connected to each other across the partition portion.

[0007] An electronic device according to one aspect of the present invention includes a light detection element, wherein the light detection element includes: a plurality of pixels arranged along a planar direction; and a partition extending between adjacent pixels among the plurality of pixels along a direction intersecting with the planar direction to separate the adjacent pixels from each other, each of the plurality of pixels includes a photoelectric conversion element and a plurality of transistors, and in a plan view, gate electrodes of specific transistors among the plurality of transistors of each of the adjacent pixels are arranged opposite to each other across the partition and are connected to each other across the partition. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing an example of a schematic configuration of an electronic device including a light detection element according to the embodiment. Figure 2 is a circuit diagram showing an example of a schematic configuration of a pixel. Figure 3 is a diagram showing an operation example of a pixel. Figure 4is a diagram showing a first configuration example of a light detecting element. Figure 5 is a diagram showing a first configuration example of a light detecting element. Figure 6 is a diagram showing a first configuration example of a light detecting element. Figure 7 is a diagram showing a second configuration example of the light detecting element. Figure 8 is a diagram showing a second configuration example of the light detecting element. Fig. 9 is a diagram showing a third configuration example of the light detecting element. Fig.10 is a diagram showing a third configuration example of the light detecting element. Fig.11 is a diagram showing a fourth configuration example of the light detecting element. Fig.12 is a diagram showing a fourth configuration example of the light detecting element. Fig.13 is a diagram showing a fifth configuration example of the light detecting element. Fig.14 is a diagram showing a fifth configuration example of the light detecting element. Fig.15 is a diagram showing a sixth configuration example of the light detecting element. Fig.16 is a diagram showing a sixth configuration example of the light detecting element. Fig.17 is a diagram showing a seventh configuration example of the light detecting element. Fig.18 is a diagram showing a seventh configuration example of the light detecting element. Fig.19 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 20 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that in the following embodiments, the same elements are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0010] The present invention will be described in the order of the following items. 0. Preface 1. Implementation Plan 1.1 First construction example 1.2 Second construction example 1.3 Example of the third construction 1.4 Fourth construction example 1.5 Fifth construction example 1.6 Sixth Construction Example 1.7 Seventh construction example 2. Effect examples 3. Application examples for mobile objects

[0011] 0. Preface As devices and electronic devices including light detection elements, CMOS image sensors (CMOS type solid-state imaging devices) and the like are known. Miniaturization technology associated with CMOS processes helps to easily create an active structure having an amplification function for each pixel. In addition, peripheral circuit units such as a signal processing circuit that processes signals output from each pixel of a pixel array unit can be integrated on the same chip (substrate) as the pixel array unit. Many technologies related to CMOS image sensors have been proposed.

[0012] For example, various technologies for extending the dynamic range have been proposed. In a technology also known as lateral overflow integration capacitor (LOFIC), a capacitor is set in a pixel to directly increase the amount of charge processed. There is also a technology that includes large and small photoelectric conversion elements with different light receiving sensitivities in one pixel. As disclosed in patent document 1, it is also known that the technology of a global shutter system in which the exposure of all pixels starts at the same time and the exposure of all pixels ends at the same time. With the advancement of technology, the pixel architecture has become complex, and the number of elements such as transistors in the pixel has also increased.

[0013] In recent years, deep insulators such as deep trench isolation (DTI) are generally provided as partitions for separating elements between pixels. The presence of partitions surrounding pixels limits the arrangement of photoelectric conversion elements and transistors and reduces layout efficiency. The gate electrode is arranged away from the partition to avoid the risk of short circuit. As a result, the size of the transistor becomes smaller, and a reduction in the amount of saturated signals and transmission failures may occur. With the miniaturization and high functionality of pixels, such problems become more obvious due to the increase in the number of elements such as transistors.

[0014] The technology disclosed in the present invention solves at least part of the above problems. The elements of each adjacent pixel are arranged symmetrically, for example, with a partition between them. The transistors of the adjacent pixels located near the partition share a gate electrode. Therefore, wasted space is eliminated and layout efficiency is improved.

[0015] 1. Implementation Plan Figure 11 is a diagram showing an example of a schematic configuration of an electronic device including a light detecting element according to an embodiment. The electronic device 100 shown is a CMOS image sensor and includes a pixel array section 1 and a peripheral section. These elements are formed on a semiconductor substrate such as silicon. As the peripheral section, Figure 1 A vertical drive section 5 , a column signal processing section 6 , a horizontal drive section 7 , a signal processing section 8 , and a system control section 9 are shown.

[0016] Figure 1 Also shown is an XYZ coordinate system of the pixel array section 1. The X-axis direction is also referred to as the horizontal direction (lateral direction), etc. The Y-axis direction is also referred to as the vertical direction (longitudinal direction), etc. The Z-axis direction is a direction orthogonal to the XY plane direction, and corresponds to, for example, the thickness direction of the semiconductor substrate.

[0017] The pixel array section 1 includes a plurality of pixels 2. The plurality of pixels 2 are arranged two-dimensionally along the X-axis direction and the Y-axis direction. Each pixel 2 generates and outputs a voltage signal corresponding to the amount of light received. This signal is also referred to as a pixel signal.

[0018] At least some of the plurality of pixels 2 constitute the light detecting element 3. The light detecting element 3 includes at least two adjacent pixels of the plurality of pixels 2. The light detecting element 3 and the plurality of pixels 2 may be replaced as appropriate within a range without contradiction.

[0019] The vertical drive section 5 drives the plurality of pixels 2 of the pixel array section 1 , for example, all at once or for each pixel row. The drive includes selectively scanning the plurality of pixels 2 row by row to read pixel signals. The pixel signals of the selectively scanned pixels 2 are sent to the column signal processing section 6 .

[0020] The vertical drive section 5 is connected to the pixel array section 1 via a plurality of control lines HL for each pixel row, for example. Each control line HL extends in the row direction and connects each pixel 2 of the corresponding pixel row and the vertical drive section 5. The vertical drive section 5 includes, for example, a shift register, an address decoder, and the like.

[0021] In the present invention, connection can be understood as electrical connection. Electrical connection can include connection with another element interposed therebetween, as long as the functions of the connected elements are not hindered.

[0022] The column signal processing section 6 processes the pixel signals of each pixel 2 in the row selected by the vertical drive section 5 for each pixel column. For example, the column signal processing section 6 includes a plurality of unit circuits corresponding to the pixel columns. The processing of the column signal processing section 6 includes noise removal processing, correlated double sampling (CDS) processing, double data sampling (DDS) processing, analog pixel signal analog / digital (A / D) conversion processing, etc. The pixel signal is digitized and sent to the signal processing section 8.

[0023] The column signal processing section 6 is connected to the pixel array section 1 via a plurality of signal lines VL. Each signal line VL extends in the column direction and connects each pixel 2 of a corresponding pixel column and the column signal processing section 6. The column signal processing section 6 includes, for example, a shift register, an address decoder, and the like.

[0024] The horizontal driving section 7 sequentially selects unit circuits of the column signal processing section 6. The horizontal driving section 7 selectively scans, and the pixel signals for each pixel column processed by the column signal processing section 6 are sequentially output to the signal processing section 8. The horizontal driving section 7 includes, for example, a shift register, an address decoder, and the like.

[0025] The signal processing section 8 processes the pixel signal from the column signal processing section 6, and generates and outputs an image signal based on the pixel signal. Note that data and the like most necessary for processing may be temporarily stored in, for example, a memory (not shown).

[0026] The system control section 9 controls the vertical drive section 5, the column signal processing section 6, and the horizontal drive section 7. For example, the system control section 9 includes a timing generator and the like to generate various timing signals and supply the timing signals to the corresponding sections.

[0027] Will refer to Figure 2 The pixels 2 of the pixel array section 1 will be described.

[0028] Figure 2 is a circuit diagram showing an example of a schematic configuration of a pixel. In this example, the pixel 2 includes a photoelectric conversion element PD, a floating diffusion region FD, a capacitor FC, and a plurality of transistors. Examples of the plurality of transistors include a transistor TGL, a transistor FDG, a transistor FCG, a transistor OFG, a transistor RST, a transistor AMP, and a transistor SEL.

[0029] An example transistor is a FET, and has a drain and a source as current terminals and a gate electrode as a control terminal. Unless otherwise specified, "connecting a transistor between two elements" means that one current terminal (drain or source) of the transistor is connected to one element, and the other current terminal of the transistor is connected to the other element.

[0030] The gate electrode of transistor TGL is referred to as gate electrode TGLG in the figure. The gate electrode of transistor FDG is referred to as gate electrode FDGG in the figure. The gate electrode of transistor FCG is referred to as gate electrode FCGG in the figure. The gate electrode of transistor OFG is referred to as gate electrode OFGG in the figure. The gate electrode of transistor RST is referred to as gate electrode RSTG in the figure. The gate electrode of transistor AMP is referred to as gate electrode AMPG in the figure. The gate electrode of transistor SEL is referred to as gate electrode SELG in the figure. The gate of transistor AMP is connected to floating diffusion region FD.

[0031] Among the multiple control lines HL connected to a pixel 2, the control line HL connected to the gate electrode TGLG of the transistor TGL is referred to as the control line HL_TGL in the figure. The control line HL connected to the gate electrode FDGG of the transistor FDG is referred to as the control line HL_FDG in the figure. The control line HL connected to the gate electrode FCGG of the transistor FCG is referred to as the control line HL_FCG in the figure. The control line HL connected to the gate electrode OFGG of the transistor OFG is referred to as the control line HL_OFG in the figure. The control line HL connected to the gate electrode RSTG of the transistor RST is referred to as the control line HL_RST in the figure. The control line HL connected to the gate electrode SELG of the transistor SEL is referred to as the control line HL_SEL in the figure. The on / off state (conducting state or non-conducting state) of each transistor is controlled by a control signal from the corresponding control line HL.

[0032] The photoelectric conversion element PD generates and accumulates electric charge corresponding to the amount of light received. Examples of the photoelectric conversion element PD are photodiodes and the like.

[0033] The transistor TGL is a transfer transistor for transferring the charge of the photoelectric conversion element PD to the floating diffusion region FD. The transistor TGL is connected between the photoelectric conversion element PD and the floating diffusion region FD.

[0034] The floating diffusion region FD accumulates the charge from the photoelectric conversion element PD transferred via the transfer transistor TGL and converts the charge into a voltage. A voltage corresponding to the accumulated charge amount is generated. The floating diffusion region FD is formed to have a floating diffusion capacitance at least between the transistor TGL, the transistor AMP, and the transistor FDG.

[0035] Transistor FDG is a conversion efficiency switching transistor that switches the conversion efficiency of charge to voltage in the floating diffusion region FD. Transistor FDG is connected between the floating diffusion region FD and the transistor RST and the transistor FCG. When transistor FDG is turned on, the area of ​​the floating diffusion region FD extends across FDG to the area on the opposite side of the floating diffusion region FD, and the capacitance of the floating diffusion region FD increases accordingly. When the capacitance of the floating diffusion region FD increases, the voltage change caused by the change in the amount of accumulated charge becomes gentle accordingly, and the conversion efficiency decreases. Conversely, when transistor FDG is turned off, the capacitance of the floating diffusion region FD decreases, and the conversion efficiency increases accordingly.

[0036] The transistor FCG is a capacitance connection transistor for connecting the capacitor FC to the floating diffusion region FD. The transistor FCG is connected between the transistor FDG and the transistor RST and the capacitor FC and the transistor OFG.

[0037] The transistor OFG is an overflow transistor (overflow gate) for transferring the charge overflowing from the photoelectric conversion element PD to the capacitor FC. The transistor OFG is connected between the photoelectric conversion element PD and the capacitor FC and the transistor FCG.

[0038] The capacitor FC is used to accumulate the charge overflowing from the photoelectric conversion element PD. The capacitor FC is connected between (the node of) the power supply voltage FCVDD and the transistor OFG and the transistor FCG. The capacitor FC has, for example, a MIM (metal-insulator-metal) structure, and in this case, the capacitor FC is a MIM capacitor.

[0039] The transistor RST is a reset transistor for discharging the charge accumulated in the floating diffusion region FD. The transistor RST is connected between (the node of) the power supply voltage VDD and the transistors FDG and FCG.

[0040] The transistor AMP is an amplifier transistor that outputs a voltage signal corresponding to the voltage of the floating diffusion region FD. The transistor AMP is connected between the power supply voltage VDD and the transistor SEL. The voltage signal output from the transistor AMP can correspond to a pixel signal.

[0041] The transistor SEL is a selection transistor for selectively outputting a voltage signal output from the transistor AMP to the signal line VL. The transistor SEL is connected between the transistor AMP and the signal line VL.

[0042] Will refer to Figure 3 An operation example of the pixel 2 having the above-described configuration is described.

[0043] Figure 3 is a diagram showing an example of the operation of a pixel. An example of a timing diagram when reading a pixel signal is shown. The power supply voltage FCVDD is controlled to 2.4V or 3.3V. Although the power supply voltage FCVDD can be constant, the lower the power supply voltage FCVDD, the higher the possibility that the dark current can be suppressed. Therefore, in this example, the power supply voltage FCVDD is controlled to 3.3V only after the LOFIC period to be described later. Each gate electrode (such as the gate electrode SELG, etc.) is controlled to a low voltage for turning off the corresponding transistor or a high voltage for turning on the transistor.

[0044] The period from time t1 to time t3 is a period for reading the pixel signal (reset voltage signal) when the floating diffusion area FD is reset. This period is also called the P phase (precharge phase) period. The gate electrode SELG is maintained at a high voltage. The gate electrode RSTG and the gate electrode FDGG have a high voltage, and the floating diffusion area FD is reset. The period from time t1 to time t2 is a period in which the conversion efficiency is low (conversion efficiency L) and the gate electrode FDGG has a high voltage, that is, the transistor FDG is turned on. The pixel signal in the state of expanding the capacitance of the floating diffusion area FD is sent to the column signal processing unit 6 via the signal line VL. The period from time t2 to time t3 is a period in which the conversion efficiency is high (conversion efficiency H) and the gate electrode FDGG has a low voltage and the transistor FDG is turned off. The pixel signal in the state in which the capacitance of the floating diffusion area FD is not expanded is sent to the column signal processing unit 6 via the signal line VL.

[0045] The period from time t3 to time t5 is a period for reading out the pixel signal corresponding to the charge accumulated in the photoelectric conversion element PD. This period is also called the D phase (data phase) period. The period from time t3 to time t4 is a period of high conversion efficiency (conversion efficiency H), and the gate electrode FDGG is kept at a low voltage, and the gate electrode TGLG has a high voltage. The charge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion area FD, and the pixel signal is sent to the column signal processing unit 6 via the signal line VL. The period from time t4 to time t5 is a period of low conversion efficiency (conversion efficiency L), and the gate electrode FDGG is kept at a high voltage, and the gate electrode TGLG has a high voltage. The charge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion area FD, and the pixel signal is sent to the column signal processing unit 6 via the signal line VL.

[0046] By the CDS processing of the above-described column signal processing section 6 , reset noise and the like are removed based on the pixel signal read in the P-phase period and the pixel signal read out in the D-phase period.

[0047] The period from time t5 to time t7 is a period for reading pixel signals by using capacitor FC. This period is also called the lateral overflow collection capacitance (LOFIC) period. In a state where the gate electrode FDGG is maintained at a high voltage, the gate electrode FCGG also has a high voltage. Not only is the transistor FDG turned on, but the transistor FCG is also turned on. In a state where the capacitor FC is connected to the floating diffusion area FD, the pixel signal is sent to the column signal processing unit 6 via the signal line VL. The period from time t5 to time t6 is the D phase period, and the period from time t6 to time t7 is the P phase period. At the beginning of the P phase period, the gate electrode RSTG has a high voltage, and the floating diffusion area FD is reset. For the pixel signal in the LOFIC period, for example, the DDS processing of the above-mentioned column signal processing unit 6 is performed.

[0048] exist Figure 3 In the example shown, a short period after time t7 is set as a digital overlap (DOL) period. The voltage of the gate electrode SELG is kept at a high voltage only during this period, and the pixel signal is extracted via the signal line VL. This makes it possible to cope with situations where the amount of received light is extremely large.

[0049] For example, as described above, the plurality of pixels 2 operate by controlling the voltages of the gate electrodes of various transistors.

[0050] In this embodiment, layout efficiency is improved by sharing some gate electrodes. Figure 4 and subsequent figures illustrate some examples of specific configurations.

[0051] 1.1 First construction example Figures 4 to 6 2 is a diagram showing a first configuration example of a light detection element. An example in which three pixels 2 are arranged side by side in the X-axis direction is shown. Figure 4 The planar layout of each electrode is schematically shown. Figure 5 Schematically shows the Figure 4 The cross section is taken along line VV in FIG. Figure 6 Schematically shows the Figure 4 In the following description, the so-called top view refers to the photodetection element 3 (ie, the plurality of pixels 2) viewed from above (observed along the Z-axis direction).

[0052] The light detecting element 3 includes a partition 4. The partition 4 separates adjacent pixels 2 from each other. The separation of the partition 4 includes at least one of electrical separation or optical separation. In this example, the partition 4 is arranged to surround each pixel 2 in a plan view (when viewed along the Z-axis direction). The partition 4 extends between adjacent pixels 2 along a direction intersecting the XY plane direction (in this example, the Z-axis direction). The partition 4 can also be said to be a wall that separates adjacent pixels 2. Each element of a pixel 2, such as the above-mentioned photoelectric conversion element PD, the floating diffusion region FD, various transistors and capacitor FC, etc., is formed in an area separated by the partition 4.

[0053] The partition 4 may include, for example, a single-layer film or a multilayer film of an insulator such as silicon oxide (SiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or aluminum oxide (Al2O3). The partition 4 may be formed by a stack of a single-layer film or a multilayer film of an insulator such as tantalum oxide, hafnium oxide or aluminum oxide and a silicon oxide film. There may be a gap inside the partition 4. The partition 4 may include a metal with high light-shielding properties such as tantalum (Ta), aluminum (Al), silver (Ag), gold (Au) or copper (Cu). Polycrystalline silicon (Polycrystalline silicon) may be used as the material of the partition 4.

[0054] In the present embodiment, in a plan view, gate electrodes of specific transistors among a plurality of transistors in each of adjacent pixels 2 are disposed opposite to each other via a partition 4 and connected to each other across the partition 4. Specifically, in Figure 4 In the example shown, the gate electrode FDGG of the transistor FDG, the gate electrode RSTG of the transistor RST, and the gate electrode SELG of the transistor SEL are gate electrodes of specific transistors. The gates of such specific transistors are connected by metal wires extending in the X-axis direction (horizontal direction), for example, and can therefore be connected to each other across the partition 4.

[0055] The gate electrodes of transistors other than the specific transistor are arranged in a region other than a region between the gate electrodes of the specific transistors of the adjacent pixels 2. Figure 4 In the example shown, the gate electrode TGLG of the transistor TGL, the gate electrode FCGG of the transistor FCG, the gate electrode OFGG of the transistor OFG, and the gate electrode AMPG of the transistor AMP are gate electrodes of transistors other than the specific transistors. The gate electrode TGLG, the gate electrode FCGG, the gate electrode OFGG, and the gate electrode AMPG are provided in an area other than the area between the gate electrodes FDGG of the adjacent pixels 2, an area other than the area between the gate electrodes RSTG, and an area other than the area between the gate electrodes SELG.

[0056] exist Figure 4 In the example shown, the gate electrodes of the transistors of each of the adjacent pixels 2 are arranged symmetrically with respect to each other across the partition 4. This arrangement can also be referred to as a mirror arrangement in the X-axis direction (mirror arrangement across the Y-axis). This can facilitate layout design, etc. Not only the gate electrodes, but also the transistors themselves and the elements of other circuits can be arranged symmetrically. Note that other patterns (not shown) such as ground patterns, etc. can also be provided.

[0057] Figure 5 A cross section of a portion including the gate electrode FDGG and the gate electrode SELG across the partition 4 is schematically shown. Elements other than the partition 4 and the gate electrode are not shown. The same applies to other cross-sectional views.

[0058] The gate electrode FDGG includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 of the gate electrode FDGG is a portion located in one of the pixels 2 adjacent in the X-axis direction (in this example, the pixel 2 on the negative side of the X-axis). The second portion P2 is a portion located in another pixel (in this example, the pixel 2 on the positive side of the X-axis). The third portion P3 is a portion located on the partition 4 and connected between the first portion P1 and the second portion P2.

[0059] The portions of the gate electrode SELG are also referred to as a first portion P1, a second portion P2, and a third portion P3 in the figure. These portions are similar to the corresponding portions of the gate electrode FDGG described above.

[0060] Figure 6 The cross section of the portion including the gate electrode RSTG is schematically shown. The portions of the gate electrode RST are also referred to as a first portion P1, a second portion P2, and a third portion P3 in the figure. These portions are also similar to the corresponding portions of the gate electrode FDGG described above.

[0061] In the light detection element 3 having the above-mentioned structure, the gate electrode of a specific transistor shared between adjacent pixels 2 does not need to be set away from the light detection element 3. Therefore, the layout efficiency can be improved. For example, by increasing the area of ​​the gate electrode, the operation can be stabilized and the transmission performance can be improved. Signal saturation can also be suppressed. In the electronic device 100 including the light detection element 3, advantages such as miniaturization and high performance can be obtained.

[0062] 1.2 Second construction example Figure 7 and Figure 8: is a diagram showing a second configuration example of a light detecting element. A plurality of pixels 2 arranged in a Bayer array are illustrated as an example. In this example, it is assumed that pixel signals corresponding to pixels 2 of the same color (red, green, etc.) are read together by alternately reading one row. Figure 7 The planar layout of each electrode is schematically shown. Figure 8 Schematically shows the Figure 7 The cross section is taken along line VIII-VIII in FIG.

[0063] In this example, the transistor OFG of the transistor OFG is also the gate electrode of a specific transistor. Specifically, the gate electrodes OFGG of the transistor OFG of the pixels 2 adjacent in the Y-axis direction are arranged to be opposite to each other across the partition 4, and are connected to each other across the partition 4. The gate electrode TGLG of the transistor TGL, the gate electrode FCGG of the transistor FCG, and the gate electrode AMPG of the transistor AMP are gate electrodes of transistors other than the specific transistor. The gate electrode TGLG, the gate electrode FCGG, and the gate electrode AMPG are arranged in an area other than the area between the gate electrodes FDGG of the adjacent pixels 2, an area other than the area between the gate electrodes RSTG, an area other than the area between the gate electrodes SELG, and an area other than the area between the gate electrodes OFGG. The gate electrodes of the transistors of each of the pixels 2 adjacent in the Y-axis direction can be arranged symmetrically to each other across the partition 4 (mirror arrangement across the X-axis in the Y-axis direction).

[0064] Figure 8 The cross section of the portion including the gate electrode OFGG outside the partition 4 is schematically shown. The portions of the gate electrode OFGG are also referred to as the first portion P1, the second portion P2, and the third portion P3 in the figure. The first portion P1 of the gate electrode OFGG is a portion located in one of the pixels 2 adjacent in the Y-axis direction (in this example, the pixel 2 on the negative side of the Y-axis). The second portion P2 is a portion located in another pixel (in this example, the pixel 2 on the positive side of the Y-axis). The third portion P3 is a portion located on the partition 4 and connected between the first portion P1 and the second portion P2.

[0065] In the above configuration, the control line HL_OFG ( Figure 2 ) are shared. Therefore, the number of control lines HL_OFG for two pixels can be reduced from two to one. By reducing the number of control lines HL, the degree of freedom of wiring layout is improved. For example, the possibility of improving the RC time constant or reducing the reduction in yield due to dust is also increased. This can also be applied to the case of reading four pixels of the same color at the same time.

[0066] 1.3 Example of the third construction Fig. 9 and Fig.10 2 is a diagram showing a third configuration example of a light detecting element. Figure 7 and Figure 8 Here, it is assumed that the pixel signals of the pixels 2 adjacent to each other in the Y-axis direction and corresponding to different colors are read together. In this case, the gate electrodes RSTG of the pixels 2 adjacent to each other in the Y-axis direction are also shared. This is because it is possible to perform a reset at the same time for simultaneous reading. Fig. 9 The planar layout of each electrode is schematically shown. Fig.10 Schematically shows the Fig. 9 The cross section is taken along line XX in FIG.

[0067] Fig.10 The cross section of the portion of the gate electrode RSTG outside the insulator 4 along the Y-axis direction is schematically shown. The portions of the gate electrode RSTG are also referred to as the first portion P1, the second portion P2, and the third portion P3 in the figure. These portions are similar to the gate electrode OFGG ( Figure 8 ) of the corresponding part.

[0068] In the above configuration, it is also possible to connect the control line HL_RST ( Figure 2 As described above, the number of control lines HL can be reduced and the degree of freedom of wiring can be improved.

[0069] 1.4 Fourth construction example Fig.11 and Fig.12 is a diagram showing a fourth configuration example of the light detecting element. Fig.11 A circuit example of the pixel 2 is shown. Fig.12 The planar layout of each electrode is schematically shown. The transistor FDG is connected between the floating diffusion region FD and the transistor RST and the transistor FCG. The power supply voltage (node) connected to the transistor RST is referred to as the power supply voltage VDD1 in the figure. The transistor AMP is connected between the power supply voltage VDD2 different from the power supply voltage VDD1 and the signal line VL.

[0070] The power supply voltage VDD1 is controlled to be switchable between a high voltage and a low voltage. By controlling the power supply voltage VDD1 to change the input voltage of the transistor AMP, the transistor AMP can have the function of the above-mentioned transistor SEL. For example, the power supply voltage VDD1 is switched between a high voltage and a low voltage by a control signal of the transistor SEL. Since the pixel 2 does not include the transistor SEL, the circuit configuration is simplified, and advantages such as improved layout efficiency can be obtained.

[0071] Since there is no transistor SEL, the planar layout does not include a gate electrode SELG. The gate electrode FDGG, the gate electrode FCGG, and the gate electrode OFGG of each pixel 2 adjacent to each other in the X-axis direction are shared. These gate electrodes are connected by, for example, metal wiring extending in the X-axis direction (horizontal direction), so they can be connected to each other across the partition 4.

[0072] 1.5 Fifth construction example Fig.13 and Fig.14 is a diagram showing a fifth configuration example of the light detecting element. Fig.13 is a circuit diagram of the pixel 2. The example pixel 2 is different from the above-described configuration in that the transistor FCG, the capacitor FC, and the transistor OFG are not included. Fig.14 The planar layout of each electrode is schematically shown. The gate electrode FDGG, the gate electrode RSTG, and the gate electrode SELG are gate electrodes of a specific transistor. The gate electrodes FDGG of the pixels 2 adjacent in the X-axis direction are arranged opposite to each other on the opposite sides with the partition 4 therebetween, and are connected to each other across the partition 4. The same applies to the gate electrode RSTG and the gate electrode SELG.

[0073] 1.6 Sixth Construction Example Fig.15 and Fig.16 is a diagram showing a sixth configuration example of the light detecting element. Fig.15 is a circuit diagram of pixel 2. Example pixel 2 and Fig.13 The difference in the configuration is that pixel 2 does not include transistor FDG. Fig.16 The planar layout of each electrode is schematically shown. The gate electrode RSTG and the gate electrode SELG are gate electrodes of specific transistors.

[0074] 1.7 Seventh construction example Fig.17 and Fig.18 is a diagram showing a seventh configuration example of the light detecting element. Fig.17 is the circuit diagram of pixel 2. Figure 2 Compared with the structure in , the example pixel 2 also includes a photoelectric conversion element PD2, a transistor TGL2 and a floating diffusion area FD2. The transistor TGL2 is a second transfer transistor for transferring the charge of the photoelectric conversion element PD2 to the floating diffusion area FD2. The transistor FCG is connected between the floating diffusion area FD2 and the transistor RST and the transistor FDG. The gate electrode of the transistor TGL2 is referred to as the gate electrode TGLG2 in the figure. The control line HL connected to the gate electrode TGLG2 is referred to as the control line HL_TGL2 in the figure.

[0075] The photoelectric conversion element PD and the photoelectric conversion element PD2 have different light receiving sensitivities. The photoelectric conversion element PD2 is designed to be smaller than the photoelectric conversion element PD, specifically, its area is smaller than the light receiving area of ​​the photoelectric conversion element PD. It can be said that the pixel 2 includes a large pixel having the photoelectric conversion element PD and a small pixel having the photoelectric conversion element PD2. By using the two light receiving elements, the photoelectric conversion element PD and the photoelectric conversion element PD2 in combination, a wide range of received light amounts can be processed, and the dynamic range can be extended accordingly.

[0076] In a plan view of the light detection element 3 , the gate electrode of the transistor connected to the photoelectric conversion element PD2 is closer to the center of the pixel 2 than the gate electrode of the transistor connected to the photoelectric conversion device PD. Fig.18 The planar layout of each electrode is schematically shown. The area of ​​the central part of the pixel 2 is indicated by a dotted line. The photoelectric conversion element PD2, the gate electrode TGLG2 of the transistor TGL2 connected to the photoelectric conversion element PD2, the floating diffusion region FD2, the gate electrode FCGG of the transistor FCG, etc. are arranged inside the area shown by the dotted line. The photoelectric conversion element PD, the gate electrode TGLG of the transistor TGL connected to the photoelectric conversion element PD, the gate electrode FDGG of the transistor FDG, the gate electrode RSTG of the transistor RST, the transistor AMP of the transistor AMP, the gate electrode SELG of the transistor SEL, etc. are arranged outside the area shown by the dotted line. The gate electrode FDGG, the gate electrode RSTG and the gate electrode SELG are gate electrodes of specific transistors.

[0077] 2. Effect examples The above technology is specifically described as follows. One of the disclosed technologies is a light detection element 3. Figures 1 to 6 As described above, the light detection element 3 includes a plurality of pixels 2 arranged along the XY plane direction, and a partition 4 extending between adjacent pixels 2 in a direction intersecting the XY plane direction (e.g., the Z-axis direction) to isolate adjacent pixels 2 in the plurality of pixels 2. Each of the plurality of pixels 2 includes a photoelectric conversion element PD and a plurality of transistors. In a plan view (when viewed along the Z-axis direction), gate electrodes of specific transistors in the plurality of transistors of each of the adjacent pixels 2 are arranged opposite to each other across the partition 4, and are connected to each other across the partition 4.

[0078] In the light detection element 3, for example, the gate electrode of a specific transistor does not need to be disposed away from the light detection element 3. Therefore, layout efficiency can be improved.

[0079] As reference Figure 5 , Figure 6As described above, the gate electrode of the specific transistor includes a first portion P1 located in one pixel 2 among the adjacent pixels 2, a second portion P2 located in another pixel 2 among the adjacent pixels 2, and a third portion P3 located on the partition 4 and connected between the first portion P1 and the second portion P2. For example, in this way, the gate electrodes of the specific transistors of the adjacent pixels 2 can be connected to each other across the partition 4.

[0080] As reference Figures 4 to 6 As described above, among a plurality of transistors, the gate electrodes of transistors other than a specific transistor can be arranged in a region other than a region between gate electrodes of specific transistors of adjacent pixels 2. For example, by arranging the gate electrodes of each transistor in this manner, the gate electrodes can be shared.

[0081] As reference Figure 4 As described above, in a plan view (when viewed in the Z-axis direction), the gate electrodes of the plurality of transistors of the respective adjacent pixels 2 can be arranged symmetrically with respect to each other via the partition 4. Therefore, layout design and the like can be facilitated.

[0082] As reference Figure 2 , Figures 4 to 6 As described above, the adjacent pixel 2 may include two pixels 2 arranged side by side along the X-axis direction (horizontal direction), and the X-axis direction is the extension direction of the control line HL of each of the multiple transistors. The gate electrode of a specific transistor may include the gate electrode FDGG of the transistor FDG, the gate electrode RSTG of the transistor RST, and at least one of the gate electrode SELG of the transistor SEL and the gate electrode RSTG of the transistor RST. The transistor FDG is a conversion efficiency switching transistor for switching the conversion efficiency of the floating diffusion area FD, and the floating diffusion area FD accumulates the charge generated in the photoelectric conversion element PD and converts the charge into a voltage. The transistor RST is a reset transistor for discharging the charge accumulated in the floating diffusion area FD. The transistor SEL is a selection transistor for selectively outputting a voltage signal (pixel signal) corresponding to the charge accumulated in the floating diffusion area FD. For example, the gate electrodes of specific transistors of adjacent pixels 2 can be shared.

[0083] As reference Figure 2 , Figure 4 , Figures 6 to 10As described above, adjacent pixels 2 may include two pixels 2 arranged side by side along the Y-axis direction (vertical direction). The gate electrode of a specific transistor may include at least one of the gate electrode RSTG of the transistor RST or the gate electrode OFGG of the transistor OFG. The transistor OFG is an overflow transistor for transferring the charge overflowing from the photoelectric conversion element PD to, for example, a capacitor FD having a MIM structure. For example, the gate electrodes of specific transistors of adjacent pixels 2 may be shared. In this case, the number of control lines HL_RST connected to the shared gate electrode RSTG can be reduced from two to one. Similarly, the number of control lines HL_OFG connected to the shared gate electrode OFGG can be reduced from two to one. The layout efficiency can be further improved.

[0084] As reference Fig.17 and Fig.18 As described above, each of the plurality of pixels 2 may include a photoelectric conversion element PD2 (a second photoelectric conversion element) that is smaller than the photoelectric conversion element PD, and the gate electrode of the transistor connected to the photoelectric conversion element PD2 of each of the plurality of pixels 2 (the gate electrode TGLG2 of the transistor TGL2, etc.) may be arranged closer to the center of the pixel 2 in a plan view (when viewed in the Z-axis direction) than the gate electrode of the transistor connected to the photoelectric conversion element PD (the gate electrode TGLG of the transistor TGL, etc.). In this way, for example, the photoelectric conversion element PD1 and the photoelectric conversion element PD2 may be used in combination to improve the layout efficiency of the configuration corresponding to the expansion of the dynamic range.

[0085] With reference Figure 1 The electronic device 100 including the light detecting element 3 described above is also one of the disclosed techniques. By providing the light detecting element 3 with higher layout efficiency, the electronic device 100 can be made smaller and more functional.

[0086] Note that the effects described in the present disclosure are merely examples, and are not limited to the disclosed contents, but other effects can be obtained.

[0087] 3. Application examples for mobile objects The technology according to the embodiment of the present invention (the present technology) can be applied to various products. For example, the technology according to the embodiment of the present invention can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0088] Fig.19 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present invention can be applied.

[0089] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.19 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0090] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force.

[0091] The body system control unit 12020 controls the operation of various types of devices provided on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal light, or a fog light. In this case, a radio wave transmitted from a mobile device that replaces the key or a signal of various types of switches may be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, or a light, etc. of the vehicle.

[0092] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a detection process of an object such as a person, a vehicle, an obstacle, a sign, or characters on the road surface, or can perform a process of detecting the distance to the above-mentioned object.

[0093] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays.

[0094] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that takes a picture of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0095] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information outside or inside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning or vehicle lane departure warning, etc.

[0096] In addition, by controlling the driving force generating device, steering mechanism or braking device, etc. based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform collaborative control aimed at achieving automatic driving, etc., wherein the automatic driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0097] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam, for example, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0098] The audio and video output unit 12052 sends an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the vehicle's passengers or the outside of the vehicle of the information. Fig.19 In the example of , as the output device, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0099] Fig. 20 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0100] exist Fig. 20 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0101] The camera units 12101, 12102, 12103, 12104 and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper and rear door of the vehicle 12100 and at the upper part of the windshield in the vehicle compartment. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly obtain images on both sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect the vehicle in front, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0102] By the way, Fig. 20 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from above is obtained.

[0103] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0104] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can determine the distance of each three-dimensional object within the camera ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100), thereby extracting the nearest three-dimensional object as the front vehicle, in particular, the three-dimensional object exists on the driving path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be maintained with the front vehicle, and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control) and the like. Therefore, cooperative control such as automatic driving that aims to make the vehicle travel autonomously without relying on the driver's operation can be performed.

[0105] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, telephone poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 is difficult to visually identify. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collisions.

[0106] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 is capable of identifying pedestrians, for example, by determining whether there are pedestrians in the camera images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following steps: a step of extracting feature points in the camera images of the camera units 12101 to 12104 as infrared cameras; and a step of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that there are pedestrians in the camera images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0107] An example of a vehicle control system to which the technology according to an embodiment of the present invention can be applied has been described above. The technology according to an embodiment of the present invention can be applied to, for example, the camera unit 12031 in the above-mentioned configuration. By applying the technology according to an embodiment of the present invention to the camera unit 12031, etc., it is possible to achieve miniaturization and high performance of the camera unit 12031, etc.

[0108] Although the embodiments of the present invention have been described, the technical scope of the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Constituent elements of different embodiments and modifications can be appropriately combined.

[0109] Note that the present technology may also have the following configurations. (1) A light detection element comprising: a plurality of pixels arranged along a planar direction; and A partition extending between adjacent pixels among the plurality of pixels in a direction intersecting with the planar direction to separate the adjacent pixels from each other, wherein Each of the plurality of pixels comprises: A photoelectric conversion element, and multiple transistors, and Gate electrodes of specific transistors among the plurality of transistors of each of the adjacent pixels are arranged opposite to each other across the partition in a plan view and are connected to each other across the partition. (2) The light detection element according to (1), wherein The gate electrode of the specific transistor includes: a first portion located in a pixel among the neighboring pixels, a second portion located in another pixel among the adjacent pixels, and A third portion is located on the partition and connected between the first portion and the second portion. (3) The light detection element according to (1) or (2), wherein Among the plurality of transistors, gate electrodes of transistors other than the specific transistor are provided in a region other than a region between the gate electrodes of the specific transistors of each of the adjacent pixels. (4) The light detection element according to any one of (1) to (3), wherein The gate electrodes of the plurality of transistors of each of the adjacent pixels are symmetrically arranged across the partition in a plan view. (5) The light detection element according to any one of (1) to (4), wherein The adjacent pixels include two pixels arranged side by side in a horizontal direction, the horizontal direction being an extending direction of a control line of each of the plurality of transistors. (6) The light detection element according to (5), wherein The gate electrode of the specific transistor includes at least one of the following gate electrodes: a gate electrode of a conversion efficiency switching transistor for switching a conversion efficiency of a floating diffusion region that accumulates charges generated in the photoelectric conversion element and converts the charges into a voltage; a gate electrode of a reset transistor for discharging charges accumulated in the floating diffusion region which accumulates charges generated in the photoelectric conversion element and changes the charges into a voltage, or A gate electrode of a selection transistor for selectively outputting a voltage signal corresponding to the charges accumulated in the floating diffusion region that accumulates the charges generated in the photoelectric conversion element and changes the charges into a voltage. (7) The light detection element according to any one of (1) to (6), wherein The adjacent pixels include two pixels arranged side by side in a vertical direction that is orthogonal to a horizontal direction that is an extending direction of a control line of each of the plurality of transistors. (8) The light detection element according to (7), wherein The gate electrode of the specific transistor includes at least one of the following transistors: a gate electrode of a reset transistor for discharging charges accumulated in a floating diffusion region that accumulates charges generated in the photoelectric conversion element and changes the charges into a voltage, or A gate electrode of an overflow transistor for transferring the charge overflowing from the photoelectric conversion element to a capacitor. (9) The light detection element according to (8), wherein The capacitor has a metal-insulator-metal (MIM) structure. (10) The light detection element according to any one of (1) to (9), wherein Each of the plurality of pixels includes a second photoelectric conversion element that is smaller than the photoelectric conversion element, and A gate electrode of a transistor of the second photoelectric conversion element connected to each of the plurality of pixels is disposed closer to a center of each of the pixels in a plan view than a gate electrode of a transistor connected to the photoelectric conversion element. (11) An electronic device, comprising: A light detection element, wherein The light detection element comprises: A plurality of pixels arranged along a plane direction, and a partition extending between adjacent pixels among the plurality of pixels in a direction intersecting with the planar direction to separate the adjacent pixels from each other, Each of the plurality of pixels comprises: A photoelectric conversion element, and multiple transistors, and Gate electrodes of specific transistors among the plurality of transistors of each of the adjacent pixels are arranged opposite to each other across the partition in a plan view and are connected to each other across the partition. Reference numerals list

[0110] 100 electronic devices 1Pixel array section 2 pixels 3 Light detection element 4 Divider 5Vertical drive unit 6-column signal processing unit 7Horizontal drive unit 8Signal Processing Unit 9System Control Unit AMP Transistor AMPG gate electrode FC Capacitors FCG transistor FCGG gate electrode FCVDD supply voltage FD floating diffusion area FD2 floating diffusion area FDG transistor FDGG gate electrode HL control line HL_FCG control line HL_FDG control line HL_OFG control line HL_RST control line HL_SEL control line HL_TGL control line HL_TGL2 control line OFG transistor OFGG gate electrode P1 Part 1 P2 Part 2 P3 Part 3 PD photoelectric conversion element PD2 photoelectric conversion element RST transistor RSTG gate electrode SEL transistor SELG gate electrode TGL Transistor TGL2 Transistor VDD supply voltage VDD1 supply voltage VDD2 supply voltage VL signal line

Claims

1. A light detection element, comprising: A plurality of pixels arranged along a plane direction; as well as A partition extending between adjacent pixels among the plurality of pixels in a direction intersecting with the planar direction to separate the adjacent pixels from each other, wherein Each of the plurality of pixels comprises: A photoelectric conversion element, and multiple transistors, and Gate electrodes of specific transistors among the plurality of transistors of each of the adjacent pixels are arranged opposite to each other across the partition in a plan view and are connected to each other across the partition.

2. The light detecting element according to claim 1, wherein The gate electrode of the specific transistor includes: a first portion located in a pixel among the neighboring pixels, a second portion located in another pixel among the adjacent pixels, and A third portion is located on the partition and connected between the first portion and the second portion.

3. The light detecting element according to claim 1, wherein Among the plurality of transistors, gate electrodes of transistors other than the specific transistor are provided in a region other than a region between the gate electrodes of the specific transistors of each of the adjacent pixels.

4. The light detecting element according to claim 1, wherein The gate electrodes of the plurality of transistors of each of the adjacent pixels are arranged symmetrically across the partition in a plan view.

5. The light detecting element according to claim 1, wherein The adjacent pixels include two pixels arranged side by side in a horizontal direction, the horizontal direction being an extending direction of a control line of each of the plurality of transistors.

6. The light detecting element according to claim 5, wherein The gate electrode of the specific transistor includes at least one of the following gate electrodes: a gate electrode of a conversion efficiency switching transistor for switching a conversion efficiency of a floating diffusion region that accumulates charges generated in the photoelectric conversion element and converts the charges into a voltage; a gate electrode of a reset transistor for discharging charges accumulated in the floating diffusion region which accumulates charges generated in the photoelectric conversion element and changes the charges into a voltage, and A gate electrode of a selection transistor for selectively outputting a voltage signal corresponding to the charges accumulated in the floating diffusion region that accumulates the charges generated in the photoelectric conversion element and changes the charges into a voltage.

7. The light detecting element according to claim 1, wherein The adjacent pixels include two pixels arranged side by side in a vertical direction that is orthogonal to a horizontal direction that is an extending direction of a control line of each of the plurality of transistors.

8. The light detecting element according to claim 7, wherein The gate electrode of the specific transistor includes at least one of the following transistors: a gate electrode of a reset transistor for discharging charges accumulated in a floating diffusion region that accumulates charges generated in the photoelectric conversion element and changes the charges into a voltage, and A gate electrode of an overflow transistor for transferring the charge overflowing from the photoelectric conversion element to a capacitor.

9. The light detecting element according to claim 8, wherein The capacitor has a metal-insulator-metal (MIM) structure.

10. The light detecting element according to claim 1, wherein Each of the plurality of pixels includes a second photoelectric conversion element that is smaller than the photoelectric conversion element, and A gate electrode of a transistor of the second photoelectric conversion element connected to each of the plurality of pixels is disposed closer to a center of each of the pixels in a plan view than a gate electrode of a transistor connected to the photoelectric conversion element.

11. An electronic device, comprising: A light detection element, wherein The light detection element comprises: A plurality of pixels arranged along a plane direction, and a partition extending between adjacent pixels among the plurality of pixels in a direction intersecting with the planar direction to separate the adjacent pixels from each other, Each of the plurality of pixels comprises: A photoelectric conversion element, and multiple transistors, and Gate electrodes of specific transistors among the plurality of transistors of each of the adjacent pixels are arranged opposite to each other across the partition in a plan view and are connected to each other across the partition.

Images