Low temperature annealing process to improve the quality of silicon wafers in CVD
By adopting a low-temperature annealing process after the LPCVD film formation of the silicon wafer, the problem of silicon wafer warping caused by the stress of polycrystalline silicon thin film is solved, the flatness yield of the product is improved, the defective yield and rework cost are reduced, and the process convenience and stability are achieved.
Patent Information
- Application Number
- CN202510035486.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-04-08
AI Technical Summary
During the LPCVD film formation process of silicon wafers, the polycrystalline silicon thin film warped due to lattice mismatch and thermal stress, which affected the bow/warp value. The prior art is difficult to effectively reduce stress, resulting in high defective yield and increased rework costs.
A low-temperature annealing process is adopted, which includes annealing under a vacuum, nitrogen or inert gas atmosphere. The annealing temperature is 630±10°C, and the temperature is maintained for 25-30 minutes, and then cooled to 25°C to reduce the stress of the polycrystalline silicon film.
It effectively reduces the stress of the polycrystalline silicon film, improves the flatness yield of the curvature and warpage of the silicon wafer, reduces the rework cost of defective products, and is convenient to operate, saves time and labor, and has good stability.
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of silicon wafer processing, and in particular to a low-temperature annealing process for improving the quality of silicon wafers in CVD. Background Art
[0002] When silicon wafers are subjected to LPCVD chemical vapor deposition of polysilicon thin films, there are lattice mismatches and a large number of grain boundaries between polycrystalline grains, so the polysilicon thin film itself has certain stress, and the thermal expansion coefficients of polysilicon and single-crystal silicon are different, so there is also thermal stress between the polysilicon thin film and the silicon wafer. Under the action of the two stresses, a stress field is formed inside. The more commonly used LPCVD vertical furnace deposition method is double-sided film formation and stress balance. After single-sided processing through the polishing process, a certain amount of stress will be released, causing the silicon wafer to have a certain degree of warping, affecting the bow / warp value.
[0003] The LPCVD film forming temperature of CVD products (LP+AP) is generally 650±10℃, and the bow / warp of the processed products cannot fully meet the requirements of the subsequent process. And for the card control standard of a certain product on the production line, the value is too large) is a defective product, and the cost increases if rework is required. There is an obvious disadvantage, so it is necessary to reduce bow / warp by releasing the stress in the CVD film. Bow / warp is the curvature and warping of the wafer. Summary of the invention
[0004] The present invention mainly solves the deficiencies in the prior art and provides a low-temperature annealing process for improving the quality of silicon wafers in CVD, which has the advantages of convenient operation, time-saving, labor-saving and good stability. It effectively reduces the stress of polysilicon film, obtains products with good curvature and warpage, effectively improves the flatness yield of curvature and warpage, and reduces the rework cost of defective products.
[0005] The above technical problems of the present invention are mainly solved by the following technical solutions: A low temperature annealing process for improving the quality of silicon wafers in CVD, comprising the following steps: Step 1: Place the silicon wafer to be LPCVD film-formed on the silicon carbide boat.
[0006] Step 2: Place the silicon carbide boat carrying the silicon wafers into the reactor, seal the reactor and evacuate it.
[0007] Step 3: Deposition is carried out in a low-pressure vertical reactor, and chemical vapor deposition is processed at a film forming temperature of 650±10℃.
[0008] Step 4: After the deposition process is completed, the flow of the film-forming gas is closed, and then the reaction chamber is evacuated, and then N2 is back-flushed to restore the reaction chamber to normal pressure.
[0009] Step 5: Unload the silicon wafers that have completed the low-pressure vapor deposition - LPCVD polysilicon film, and then use the tray transfer equipment to deposit the SiO2 thin film by atmospheric pressure vapor deposition - APCVD.
[0010] Step 6: Deposition is carried out in a normal pressure transfer reactor, and a film forming temperature of 450±20°C is used to deposit a SiO2 thin film on the back of the silicon wafer.
[0011] Step 7: Anneal the silicon wafers that have been processed by LPCVD and APCVD.
[0012] Step 8: After annealing, polishing is performed, and after polishing, the flatness of the curvature and warpage is measured.
[0013] Preferably, the film forming time is 20 to 30 minutes, and the processed film thickness is 3000 to 5000 angstroms; the processing time is 30 to 40 minutes, and the processed film thickness is 5000 to 7000 angstroms; the processing time is 50 to 60 minutes, and the processed film thickness is 7000 to 9000 angstroms.
[0014] Preferably, the low temperature annealing is performed in a vacuum, nitrogen, or inert gas atmosphere.
[0015] Preferably, the single-side polished single crystal silicon substrate is ultrasonically cleaned with acetone and alcohol for 30 minutes respectively, blown dry and placed on a rotating substrate support frame of a vacuum magnetron sputtering device for coating.
[0016] Preferably, the single crystal silicon substrate on the rotating substrate support is rotated, and then the vacuum chamber is evacuated and Ar gas is introduced into the vacuum chamber; co-deposition is started, and the deposition atomic ratio is controlled by changing the sputtering power by adjusting the current and voltage.
[0017] Preferably, in the deposition film forming step in a low-pressure vertical reactor, the introduction of silane gas is divided into two steps. The first step is to pre-introduce silane to make the furnace chamber into a silane atmosphere, and the second step is to continuously introduce silane gas. The thickness of the deposited film varies with the introduction time. The transmission speed of CVD deposition is the same as that of low-pressure vapor deposition, and the thickness of the deposited film varies with the introduction of different amounts of silane.
[0018] Preferably, the annealing step is to first evacuate the furnace chamber, then introduce N2, maintain a constant temperature of 630±10°C for 25-30 minutes under the N2 atmosphere, and then cool down to 25°C; after annealing, the front side of the silicon wafer is processed and modified using physical, mechanical and chemical polishing.
[0019] The present invention can achieve the following effects: The present invention provides a low-temperature annealing process for improving the quality of silicon wafers in CVD, which has the advantages of convenient operation, time-saving, labor-saving and good stability compared with the prior art. It can effectively reduce the stress of polysilicon film, obtain products with good curvature and warpage, effectively improve the flatness yield of curvature and warpage, and reduce the rework cost of defective products. DETAILED DESCRIPTION
[0020] The technical solution of the invention is further specifically described below through embodiments.
[0021] Embodiment: A low temperature annealing process for improving the quality of silicon wafers in CVD, comprising the following steps: Step 1: Place the silicon wafer to be LPCVD film-formed on the silicon carbide boat.
[0022] Step 2: Place the silicon carbide boat carrying the silicon wafers into the reactor, seal the reactor and evacuate it.
[0023] Step 3: Deposition is carried out in a low-pressure vertical reactor, and chemical vapor deposition is processed at a film forming temperature of 650±10℃.
[0024] The film forming time is 20 to 30 minutes, and the processed film thickness is 3000 to 5000 angstroms; the processing time is 30 to 40 minutes, and the processed film thickness is 5000 to 7000 angstroms; the processing time is 50 to 60 minutes, and the processed film thickness is 7000 to 9000 angstroms.
[0025] Step 4: After the deposition process is completed, the flow of the film-forming gas is closed, and then the reaction chamber is evacuated, and then N2 is back-flushed to restore the reaction chamber to normal pressure.
[0026] Step 5: Unload the silicon wafers that have completed the low-pressure vapor deposition - LPCVD polysilicon film, and then use the tray transfer equipment to deposit the SiO2 thin film by atmospheric pressure vapor deposition - APCVD.
[0027] Step 6: Deposition is carried out in a normal pressure transfer reactor, and a film forming temperature of 450±20°C is used to deposit a SiO2 thin film on the back of the silicon wafer.
[0028] In the deposition film forming step in the low-pressure vertical reactor, the introduction of silane gas is divided into two steps. The first step is to pre-introduce silane to make the furnace chamber into a silane atmosphere, and the second step is to continuously introduce silane gas. The thickness of the deposited film varies with the introduction time. The transmission speed of CVD deposition is the same as that of low-pressure vapor deposition, and the thickness of the deposited film varies with the introduction of different amounts of silane.
[0029] Step 7: Anneal the silicon wafers after LPCVD and APCVD processing. Low temperature annealing is performed in a vacuum, nitrogen, or inert gas atmosphere.
[0030] The annealing step is to first evacuate the furnace chamber, then introduce N2, and maintain a constant temperature of 630±10℃ for 25-30min under N2 atmosphere, and then cool down to 25℃; after annealing, the front side of the silicon wafer is processed and modified using physical, mechanical and chemical polishing.
[0031] The single-side polished single-crystal silicon substrate was ultrasonically cleaned with acetone and alcohol for 30 minutes respectively, and then dried and placed on the rotating substrate support frame of the vacuum magnetron sputtering equipment for coating. The single-crystal silicon substrate on the rotating substrate support frame rotates, and then the vacuum chamber is evacuated and Ar gas is introduced into the vacuum chamber; co-deposition begins, and the deposition atomic ratio is controlled by adjusting the current and voltage to change the sputtering power.
[0032] Step 7: After annealing, polishing is performed, and after polishing, the flatness of the curvature and warpage is measured. The curvature and warpage of the polished wafers of the LPCVD and APCVD CVD products after low-temperature annealing are measured to be -5 to 5 μm and 10 to 15 μm respectively.
[0033] In summary, the low-temperature annealing process for improving the quality of silicon wafers in CVD has the advantages of convenient operation, time-saving, labor-saving and good stability. It can effectively reduce the stress of polysilicon film, obtain products with good curvature and warpage, effectively improve the flatness yield of curvature and warpage, and reduce the rework cost of defective products.
[0034] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by any technician in the field of the present invention are included in the patent scope of the present invention.
Claims
1. A low temperature annealing process for improving the quality of silicon wafers in CVD, characterized in that The steps are as follows: Step 1: Place the silicon wafer to be LPCVD-filmed on the silicon carbide boat; Step 2: Place the silicon carbide boat carrying the silicon wafers into the reactor, seal the reactor and evacuate it; Step 3: Deposition is carried out in a low-pressure vertical reactor, and the chemical vapor deposition is processed at a film forming temperature of 650±10℃; Step 4: After the deposition process is completed, the film-forming gas is turned off, and then the reaction chamber is evacuated, and then N2 is back-flushed to restore the reaction chamber to normal pressure; Step 5: Unload the silicon wafer after the low-pressure vapor deposition-LPCVD polysilicon film has been completed, and then use the tray transfer equipment to deposit the SiO2 thin film by atmospheric pressure vapor deposition-APCVD on the silicon wafer; Step 6: Deposition is performed in a normal pressure transfer reactor, and a SiO2 thin film is deposited on the back of the silicon wafer at a film forming temperature of 450±20°C; Step 7: Anneal the silicon wafers that have been processed by LPCVD and APCVD; Step 8: After annealing, polishing is performed, and after polishing, the flatness of the curvature and warpage is measured.
2. The low temperature annealing process for improving the quality of silicon wafers in CVD according to claim 1, characterized in that: The film forming time is 20 to 30 minutes, and the processed film thickness is 3000 to 5000 angstroms; the processing time is 30 to 40 minutes, and the processed film thickness is 5000 to 7000 angstroms; the processing time is 50 to 60 minutes, and the processed film thickness is 7000 to 9000 angstroms.
3. The low temperature annealing process for improving the quality of silicon wafers in CVD according to claim 1, characterized in that: Low temperature annealing is performed in vacuum, nitrogen, or inert gas atmosphere.
4. The low temperature annealing process for improving the quality of silicon wafers in CVD according to claim 1, characterized in that: The single-side polished single crystal silicon substrate was ultrasonically cleaned with acetone and alcohol for 30 minutes respectively, blown dry and placed on a rotating substrate support frame of a vacuum magnetron sputtering device for coating.
5. The low temperature annealing process for improving the quality of silicon wafers in CVD according to claim 4, characterized in that: The single crystal silicon substrate on the rotating substrate support is rotated, and then the vacuum chamber is evacuated and Ar gas is introduced into the vacuum chamber; co-deposition begins, and the deposition atomic ratio is controlled by changing the sputtering power by adjusting the current and voltage.
6. The low temperature annealing process for improving the quality of silicon wafers in CVD according to claim 1, characterized in that: In the deposition film forming step in the low-pressure vertical reactor, the introduction of silane gas is divided into two steps. The first step is to pre-introduce silane to make the furnace chamber into a silane atmosphere, and the second step is to continuously introduce silane gas. The thickness of the deposited film varies with the introduction time. The transmission speed of CVD deposition is the same as that of low-pressure vapor deposition, and the thickness of the deposited film varies with the introduction of different amounts of silane.
7. The low temperature annealing process for improving the quality of silicon wafers in CVD according to claim 1, characterized in that: The annealing step is to first evacuate the furnace chamber, then introduce N2, and maintain a constant temperature of 630±10℃ for 25-30min under N2 atmosphere, and then cool down to 25℃; after annealing, the front side of the silicon wafer is processed and modified using physical, mechanical and chemical polishing.