Parallel real-time three-dimensional waveform mapping method of digital oscilloscope

Abstract

The invention discloses a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope, and the method comprises the steps: collecting a measured signal through a collection system of the digital oscilloscope, converting the collected parallel sampling data into serial data through a parallel-serial conversion module, and sequentially writing the serial data into K parallel FIFOs (First In First Out), one sampling point is read from the K parallel FIFOs in each clock period, so that parallel real-time three-dimensional waveform mapping from the sampling point to the three-dimensional database is realized; finally, the mapping results are connected end to end in sequence to be spliced into a whole piece of three-dimensional waveform data, and then the whole piece of three-dimensional waveform data is uploaded to an upper computer to be displayed in real time.

Description

Technical Field

[0001] The invention belongs to the technical field of digital oscilloscopes, and more specifically, relates to a parallel real-time three-dimensional waveform mapping method of a digital oscilloscope. Background Art

[0002] Digital oscilloscopes are developing towards high bandwidth, high sampling rate, high capture, deep storage, and low dead time. Display mapping speed has become an obvious constraint. Improving mapping speed is the most economical way to increase capture rate and reduce dead time. Due to the limitations of storage hardware (such as DDR), it is not possible to simultaneously collect and write data during the reading of data during drawing. Therefore, acquisition and drawing can only be performed serially. Therefore, the period during which the drawing data is read is within the dead time of the oscilloscope acquisition. Only by reducing the drawing time can the capture rate be increased and the acquisition dead time be reduced.

[0003] Traditional 3D waveform mapping mainly consists of three basic steps: Figure 1 As shown, firstly, the address corresponding to the sampling point in the three-dimensional database is calculated according to the sampling value size and time sequence; then the original waveform data information at the address in the three-dimensional database is read out, that is, the data is obtained; finally, the original waveform information is added by 1, that is, the data operation is updated, and it is written back to the same address. If one step is completed per clock according to this process to perform waveform three-dimensional mapping, first one clock beat is used to obtain the three-dimensional data, the next clock beat is used to update the operation to obtain the three-dimensional data information, and the next clock beat is used to write the data into the storage unit. Then each sampling point requires 3 clock cycles, the overall mapping consumes a lot of time, and the drawing time is long.

[0004] Since FPGA is a parallel architecture, in order to give full play to its advantages, the drawing process can be implemented in a pipeline manner, such as Figure 2 As shown; pipeline mapping requires that the video memory must be a dual-port read-write storage device, but even a dual-port storage device cannot achieve the same continuous or alternating repeated correct mapping because Figure 2 It can be seen that the data of D1 performs the UR1 data storage operation at T4, and the result of UR1 can be read at T5; if the address mapped by D2 is the same as that of D1, then the operation result of UR1 cannot be read at T3, that is, the real result of UR1 can only be read at A4 (the data corresponding to D4); similarly, D3 cannot read the result of UR1. The final phenomenon is that the results of three mappings of D1, D2, and D3 are the same as the result of one mapping of D1, and only 1 / 3 of the operations of multiple continuous mappings are valid.

[0005] Because of the error of continuous identical address mapping, full data mapping cannot accurately map the waveform brightness when deep storage (such as mapping tens of megabytes of data to the screen, there is a high probability of repeated mapping of continuous addresses). The pipeline mapping function of non-dual-end external video memory is completely invalid, and the storage device data reading and writing alternating operations may require multiple read and write clocks, and the cost of synchronous single-cycle synchronous RAM is higher. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope, which utilizes a mapping address conflict management mechanism to map sampling points in a cache to ensure that multiple sampling points under the same mapping address can be mapped at one time.

[0007] To achieve the above-mentioned object of the invention, the present invention provides a parallel real-time three-dimensional waveform mapping method of a digital oscilloscope, characterized in that it comprises the following steps:

[0008] (1) Deploy K parallel FIFOs and a three-dimensional database with S columns and T rows in the FPGA of the digital oscilloscope;

[0009] (2) Power on the digital oscilloscope and connect the measured signal; collect the measured signal through the acquisition system of the digital oscilloscope to obtain parallel sampling data; and then convert it into serial data through the parallel-to-serial conversion module;

[0010] (3) Write the serial data into K parallel FIFOs in sequence;

[0011] (4) Complete parallel real-time three-dimensional waveform mapping from each sampling point in the K parallel FIFOs to the three-dimensional database;

[0012] (5) The probability data of each storage unit in the K RAMs are connected end to end in sequence to form a complete three-dimensional waveform data, which is then uploaded to the host computer for real-time display.

[0013] The object of the invention of the present invention is achieved in this way:

[0014] The invention discloses a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope. The method collects a measured signal through an acquisition system of the digital oscilloscope, converts the collected parallel sampling data into serial data through a parallel-to-serial conversion module, writes the serial data into K parallel FIFOs in sequence, reads a sampling point from the K parallel FIFOs in each clock cycle, and realizes parallel real-time three-dimensional waveform mapping from the sampling point to a three-dimensional database. Finally, the mapping results are connected end to end in sequence to form a whole three-dimensional waveform data, which is then uploaded to a host computer for real-time display.

[0015] At the same time, the parallel real-time three-dimensional waveform mapping method of a digital oscilloscope of the present invention also has the following beneficial effects:

[0016] (1) Mapping of sampling points with address conflicts is completed through one write operation, avoiding the disadvantage of multiple read and write operations required in traditional methods, achieving speed optimization, and achieving the effect of "mapping one point at a time".

[0017] (2) A parallel mapping method is used to enable each mapping module to draw the same waveform data at the same time, solving the problem of mismatch between high sampling rate and FPGA single-channel data throughput and processing capability.

[0018] (3) The present invention supports the mapping speed-up of a single-port external cache, and a non-dual-port external memory can normally implement the pipeline mapping function. The mapping address conflict management mechanism realizes the transformation from alternating read and write operations to batch read and write operations.

[0019] (4) The present invention ensures real-time one-shot mapping under any disordered repetition conditions and supports deep storage of full data point mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a traditional three-dimensional waveform mapping block diagram;

[0021] Figure 2 It is a traditional three-dimensional waveform mapping timing diagram;

[0022] Figure 3 This is a schematic diagram of the three-dimensional database address division

[0023] Figure 4 It is a parallel real-time three-dimensional waveform mapping flow chart;

[0024] Figure 5 It is a parallel real-time three-dimensional waveform mapping timing diagram. DETAILED DESCRIPTION

[0025] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0026] Example

[0027] In this embodiment, a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope includes the following steps:

[0028] (1) Deploy the hardware structure in the digital oscilloscope;

[0029] Deploy K parallel FIFOs in the FPGA of a digital oscilloscope;

[0030] According to the resolution S*T of the display screen, a three-dimensional database with S columns and T rows corresponding to the display screen is deployed in the FPGA of the digital oscilloscope; the three-dimensional database is divided into K sub-three-dimensional databases in the order of storage time, and each sub-three-dimensional database is composed of a dual-port RAM, each RAM contains Q storage units, and each storage unit is set with an initial storage probability; where Q = (S / K) × T, and the initial storage probability of the storage unit in the jth column and the kth row in the i-th RAM is p i,jk , i=1,2,…,K, j=1,2,…,S / K, k=1,2,…,T;

[0031] In this embodiment, assuming that the resolution of the display screen is S*T=200*1000, the size of the three-dimensional database is 200 rows and 1000 columns; Figure 3 As shown, the three-dimensional database is divided into K=10 sub-three-dimensional databases, that is, composed of 10 RAMs. The size of each sub-three-dimensional database composed of RAM is 200 rows and 100 columns, and each contains 20,000 storage units. For example, the addresses of the storage units in RAM1 are 0, 1, ..., 199, and the storage units with different addresses store their respective initial probabilities.

[0032] (2) Power on the digital oscilloscope and connect the measured signal; collect the measured signal through the acquisition system of the digital oscilloscope to obtain parallel sampling data; and then convert it into serial data through the parallel-to-serial conversion module;

[0033] (3) Assume that the serial data has a total of MK sampling points, M = S / K; Figure 4 As shown, 1 to M sampling points in the serial data are stored in FIFO1, M+1 to 2M sampling points are stored in FIFO2, and so on, until all the serial data are stored in the corresponding FIFO;

[0034] In this embodiment, there are 10 FIFOs that cache 10 parallel data at the same time, and the data of each FIFO enters the corresponding sub-three-dimensional database composed of RAM for mapping. For example, the data in FIFO1 enters RAM1 for mapping in turn, and so on;

[0035] (4) Parallel real-time three-dimensional waveform mapping;

[0036] (4.1) Set the cache depth of each RAM to N=4; set the cache register and initialize the mapping value of the cache register to ρ=0;

[0037] (4.2) At clock cycle T1, the first sampling point is read from the K parallel FIFOs, denoted as {D1,D M+1 ,D 2M+1 ,…,D (K-1)M+1};

[0038] (4.3) At clock cycle T2, the second sampling point is read from the K parallel FIFOs, denoted as {D2, D M+2 ,D 2M+2 ,…,D (K-1)M+2}, then calculate the address A1 of the first sampling point in the corresponding RAM according to the sampling value of the first sampling point;

[0039] Now we give an arbitrary address A j The general calculation formula is:

[0040] A j =A s +2 n ×(j-1)-Y j

[0041] Where j = 1, 2, ..., M, A s is the mapping base address, Y j is the amplitude of the jth sampling point, and n is the resolution of the ADC.

[0042] Update the storage probability corresponding to the storage unit at address A1 in each RAM to p i,1k +1, and then written back to the memory cell at address A1 after 3 clock cycles;

[0043] (4.4) At clock cycle T3, the third sampling point is read from the K parallel FIFOs, denoted as {D3, D M+3 ,D 2M+3 ,…,D (K-1)M+3}, then calculate the address A2 of the second sampling point in the corresponding RAM according to the sampling value of the second sampling point;

[0044] like Figure 5 As shown, compare the sizes of A2 and A1. If A2 = A1, add 1 to the mapping value ρ in the cache register, otherwise keep it unchanged.

[0045] Update the storage probability corresponding to the storage unit at address A2 in each RAM to p i,2k +ρ+1, and then after N-1 clock cycles, it is written back to the storage unit at address A2 and the mapping value ρ=0 is reset;

[0046] (4.5) At clock cycle T4, the fourth sampling point is read from the K parallel FIFOs, denoted as {D4, D M+4 ,D 2M+4 ,…,D (K-1)M+4}; Then calculate the address A3 of the third sampling point in the corresponding RAM according to the sampling value of the third sampling point;

[0047] like Figure 5 As shown, compare the size of A3 with A2 and A1. If A3 is equal to any one of A2 and A1, then increase the mapping value ρ in the cache register by 1. If A3 is equal to A2 and A1, then increase the mapping value ρ in the cache register by 2. Otherwise, keep it unchanged.

[0048] Update the storage probability corresponding to the storage unit at address A3 in each RAM to p i,3k +ρ+1, and then after N-1 clock cycles, it is written back to the storage unit at address A3 and the mapping value ρ=0 is reset;

[0049] (4.6) Similarly, repeat the above operation. When the number of sample points read reaches the RAM cache depth of 4, the fifth sample point is read from the K parallel FIFOs at clock cycle T5, which is recorded as {D5, D M+5 ,D 2M+5 ,…,D (K-1)M+5}; Then, the address A4 of the 4th sampling point in the corresponding RAM is calculated according to the sampling value of the 4th sampling point;

[0050] like Figure 5 As shown, compare the size of A4 with A3, A2, and A1. If A4 is equal to any one of them, add 1 to the mapping value ρ in the cache register. If A4 is equal to any two of them, add 2 to the mapping value ρ in the cache register. And so on. If A4 is equal to each of them, add 3 to the mapping value ρ in the cache register. Otherwise, keep it unchanged.

[0051] Update the storage probability corresponding to the storage unit at address A4 in each RAM to p i,4k +ρ+1, and then after 3 clock cycles, it is written back to the storage unit at address A4 and the mapping value ρ=0 is reset;

[0052] (4.7) When the number of sample points read exceeds the RAM cache depth of 4, that is, in the clock cycle T L Read the Lth sampling point from K parallel FIFOs, denoted as {D L ,D M+L ,D 2M+L ,…,D (K-1)M+L}, L>5; then calculate the address A of the L-1th sampling point in the corresponding RAM according to the sampling value of the L-1th sampling point L-1 ;

[0053] Comparison A L-1 With A L-2 ,A L-3 ,…,A L-N If the size of A L-1If A is equal to any of them, the mapping value ρ in the cache register is increased by 1. L-1 If A is equal to any two of them, then the mapping value ρ in the cache register is increased by 2, and so on. L-1 If they are equal to each other, then increase the mapping value ρ in the cache register by N-1, otherwise keep it unchanged;

[0054] Update each RAM address to A L-1 The storage probability corresponding to the storage unit is p i,(L-1)k +ρ+1, and then after N-1 clock cycles, write it back to address A L-1 The storage unit is reset to the mapping value ρ = 0;

[0055] (4.8), in this embodiment, if Figure 5 As shown in FIG. 1 , it is assumed that the sixth sampling point is read from the K parallel FIFOs at clock cycle T6, and then the address is calculated as A5, and the size of A5 is compared with A4, A3, and A2, and address A1 is eliminated; it is assumed that the seventh sampling point is read from the K parallel FIFOs at clock cycle T7, and then the address is calculated as A6, and the size of A6 is compared with A5, A4, and A3, and address A2 is eliminated; and so on, the above operations are repeated until the three-dimensional mapping of the last sampling point in the K parallel FIFOs is completed; it can be found that starting from clock cycle T5, the cache depth has been reached, and at clock cycle T M+1 No longer read sampling points, only calculate the address A of the Mth sampling point M , and then update each RAM address to A L-1 The storage probability corresponding to the storage unit.

[0056] (5) The probability data of each storage unit in the K RAMs are connected end to end in sequence to form a complete three-dimensional waveform data, which is then uploaded to the host computer for real-time display.

[0057] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A parallel real-time three-dimensional waveform mapping method for a digital oscilloscope, characterized in that: The following steps are involved: (1) Deploy the hardware structure in the digital oscilloscope; Deploy K parallel FIFOs in the FPGA of a digital oscilloscope; According to the resolution S*T of the display screen, a three-dimensional database with S columns and T rows corresponding to the display screen is deployed in the FPGA of the digital oscilloscope; the three-dimensional database is divided into K sub-three-dimensional databases in the order of storage time, and each sub-three-dimensional database is composed of a dual-port RAM, each RAM contains Q storage units, and each storage unit is set with an initial storage probability; where Q = (S / K) × T, and the initial storage probability of the storage unit in the jth column and the kth row in the i-th RAM is p i,jk , i=1,2,…,K, j=1,2,…,S / K, k=1,2,…,T; (2) Power on the digital oscilloscope and connect the measured signal; collect the measured signal through the acquisition system of the digital oscilloscope to obtain parallel sampling data; and then convert it into serial data through the parallel-to-serial conversion module; (3) Assume that the serial data has a total of MK sampling points, M = S / K; store 1 to M sampling points of the serial data into FIFO1, store M+1 to 2M sampling points into FIFO2, and so on, until all the serial data are stored in the corresponding FIFO; (4) Parallel real-time 3D waveform mapping; (4.1) Set the cache depth of each RAM to N; set the cache register and initialize the mapping value of the cache register to ρ = 0; (4.2) At clock cycle T1, the first sampling point is read from the K parallel FIFOs, denoted as {D1,D M+1 ,D 2M+1 ,…,D (K-1)M+1 }; (4.3) At clock cycle T2, the second sampling point is read from the K parallel FIFOs, denoted as {D2, D M+2 ,D 2M+2 ,…,D (K-1)M+2 }, then calculate the address A1 of the first sampling point in the corresponding RAM according to the sampling value of the first sampling point; Update the storage probability corresponding to the storage unit at address A1 in each RAM to p i,k +1, and then write it back to the memory cell at address A1 after N-1 clock cycles; (4.4) At clock cycle T3, the third sampling point is read from the K parallel FIFOs, denoted as {D3, D M+3 ,D 2M+3 ,…,D (K-1)M+3 }, then calculate the address A2 of the second sampling point in the corresponding RAM according to the sampling value of the second sampling point; Compare the sizes of A2 and A1. If A2 = A1, add 1 to the mapping value ρ in the cache register, otherwise keep it unchanged. Update the storage probability corresponding to the storage unit at address A2 in each RAM to p i,2k +ρ+1, and then after N-1 clock cycles, it is written back to the storage unit at address A2 and the mapping value ρ=0 is reset; (4.5) At clock cycle T4, the fourth sampling point is read from the K parallel FIFOs, denoted as {D4, D M+4 ,D 2M+4 ,…,D (K-1)M+4 }; Then calculate the address A3 of the third sampling point in the corresponding RAM according to the sampling value of the third sampling point; Compare the size of A3 with A2 and A1. If A3 is equal to any one of A2 and A1, then increase the mapping value ρ in the cache register by 1. If A3 is equal to A2 and A1, then increase the mapping value ρ in the cache register by 2. Otherwise, keep it unchanged. Update the storage probability corresponding to the storage unit at address A3 in each RAM to p i,3k +ρ+1, and then after N-1 clock cycles, it is written back to the storage unit at address A3 and the mapping value ρ=0 is reset; (4.6) and so on. Repeat the above operation. When the number of sample points read reaches the RAM cache depth N, that is, in the clock cycle T N+1 Read the N+1th sampling point from K parallel FIFOs, denoted as {D N ,D M+N ,D 2M+N ,…,D (K-1)M+N }; Then calculate the address A of the N-1th sampling point in the corresponding RAM according to the sampling value of the Nth sampling point N ; Comparison A N With A N-1 ,…,A2,A1, if A N If A is equal to any of them, the mapping value ρ in the cache register is increased by 1. N If A is equal to any two of them, then the mapping value ρ in the cache register is increased by 2, and so on. N If they are equal to each other, then increase the mapping value ρ in the cache register by N-1, otherwise keep it unchanged; Update each RAM address to A N The storage probability corresponding to the storage unit is p i,Nk +ρ+1, and then after N-1 clock cycles, it is written back to address A N The storage unit is reset to the mapping value ρ = 0; (4.7) When the number of sample points read exceeds the RAM cache depth N, that is, in the clock cycle T L Read the Lth sampling point from K parallel FIFOs, denoted as {D L ,D M+L ,D 2M+L ,…,D (K-1)M+L }, L>N+1; then calculate the address A of the L-1th sampling point in the corresponding RAM according to the sampling value of the L-1th sampling point L-1 ; Comparison A L-1 With A L-2 ,A L-3 ,…,A L-N If the size of A L-1 If A is equal to any of them, the mapping value ρ in the cache register is increased by 1. L-1 If A is equal to any two of them, then the mapping value ρ in the cache register is increased by 2, and so on. L-1 If they are equal to each other, then increase the mapping value ρ in the cache register by N-1, otherwise keep it unchanged; Update each RAM address to A L-1 The storage probability corresponding to the storage unit is p i,(L-1)k +ρ+1, and then after N-1 clock cycles, it is written back to address A L-1 The storage unit is reset to the mapping value ρ = 0; (4.8) Repeat the above operations in this way until the three-dimensional mapping of the last sampling point in the K parallel FIFOs is completed; (5) The probability data of each storage unit in the K RAMs are connected end to end in sequence to form a complete three-dimensional waveform data, which is then uploaded to the host computer for real-time display.

2. The parallel real-time three-dimensional waveform mapping method of a digital oscilloscope according to claim 1, characterized in that: The address A j The calculation method is: HAS j =A s +2 n ×(j-1)-Y j Where j = 1, 2, ..., M, A s is the mapping base address, Y j is the amplitude of the jth sampling point, and n is the resolution of the ADC.

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