Scan Chain Fault Location Method and System Based on Dedicated Chain Diagnostic Vectors

Abstract

The present invention discloses a scan chain fault location method and system based on dedicated chain diagnostic vectors. The method first determines the types of faults existing in the scan chains of the functional circuit to be tested through chain testing, and then generates corresponding dedicated chain diagnostic vectors for each flip-flop. Among them, the corresponding positions of the flip-flop and its downstream flip-flops are set to fault values according to the fault type; the input values of the functional circuit are adjusted so that the previous flip-flop of the flip-flop captures the opposite value of the fault value; finally, the dedicated chain diagnostic vectors are used for scan chain fault testing to obtain the positions of the flip-flops where faults occur. By generating dedicated chain diagnostic vectors for each scan flip-flop and combining circuit logic analysis, the present invention can more accurately locate the fault positions in the scan chain.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testability design, in particular to a scan chain fault location method and system based on a dedicated chain diagnostic vector. Background Art

[0002] Scan testing is a method for detecting faults in digital circuits, especially integrated circuits (ICs), and has been widely used to detect defects generated during the manufacturing process of integrated circuits and can achieve a relatively high test coverage rate. This method effectively tests the functions and performance of complex circuits by scanning and controlling the internal states of the circuits and using a scan chain structure. The core principle of the scan chain is to connect multiple flip-flops in series through a specific circuit design, enabling external test vectors to enter the chain sequentially, thereby sequentially exciting and controlling each flip-flop of the circuit. This design allows test signals to be transmitted through the scan chain and set the internal states of the circuit, thereby effectively testing the internal functions of the circuit.

[0003] However, the integrity issue of the scan chain remains a major challenge in scan testing. The scan chain is composed of multiple flip-flops connected in series. In different circuit designs, there are differences in the chip area consumed by scan elements, chain connections, and control circuits. Among them, scan elements and the clock part may occupy approximately 30% of the chip area. More importantly, the occurrence rate of scan chain faults varies with different designs, usually between 10% and 30%, and scan chain faults account for almost 50% of chip faults. Therefore, accurately diagnosing faults in the scan chain is crucial for ensuring the effectiveness of scan testing.

[0004] Currently, methods for implementing scan chain fault location based on simulation and the like usually use traditional test vectors and process the obtained simulation results to locate the positions of scan chain faults. However, traditional test vector generation mainly focuses on fault detection in the functional part of the circuit, and the commonly concerned metrics include fault coverage rate, the number of test vectors, and test time, etc. It is not specifically generated for chain diagnosis, and its generation process does not consider the particularity of the chain structure, resulting in low efficiency and accuracy in scan chain fault location. Summary of the Invention

[0005] Object of the Invention: The object of the present invention is to provide a scan chain fault location method and system based on a dedicated chain diagnostic vector with high accuracy and fast diagnosis speed.

[0006] Technical Solution: The scan chain fault location method based on a dedicated chain diagnostic vector according to the present invention includes the following steps:

[0007] Step 1: Determine the type of fault existing in the scan chain of the functional circuit to be tested through a chain test. The type of fault is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0.

[0008] Step 2: Generate a corresponding dedicated chain diagnostic vector for each flip-flop. Among them, for the corresponding positions of this flip-flop and its downstream flip-flops, set them to the fault value according to the type of fault; adjust the input value of the functional circuit so that the previous flip-flop of this flip-flop captures the opposite value of the fault value.

[0009] Step 3: Use the dedicated chain diagnostic vector to perform a scan chain fault test to obtain the position of the flip-flop where the fault occurs.

[0010] Further, in Step 1, read the circuit netlist file after inserting the scan chain, inject stuck-at-1 and stuck-at-0 faults into each flip-flop in the scan chain to obtain a faulty circuit netlist; use periodic test vectors to perform a chain test to determine the type of fault existing in the scan chain of the functional circuit.

[0011] Further, in Step 2, in the dedicated chain diagnostic vector, the corresponding positions of the upstream flip-flops of this flip-flop are don't care bits, which are randomly set to 0 or 1.

[0012] Further, in Step 2, the method of adjusting the input value of the functional circuit so that the previous flip-flop of this flip-flop captures the opposite value of the fault value includes:

[0013] Set constraint conditions, input ports, and output ports. The constraint condition is that the corresponding positions of this flip-flop and its downstream flip-flops in the dedicated chain diagnostic vector are the fault value. Calculate the output of the functional circuit by traversing all possible input combinations to obtain the input combination that satisfies the constraint condition.

[0014] Further, in Step 2, the capture value of this flip-flop is set to the opposite value of the fault value.

[0015] Further, Step 3 specifically includes saving the chain diagnostic vector and generating its corresponding testbench file, and using the testbench file to perform a scan chain fault test to obtain the position of the flip-flop where the fault occurs.

[0016] The scan chain fault location system based on a dedicated chain diagnostic vector described in the present invention includes:

[0017] A fault type test unit, configured to determine the type of fault existing in the scan chain of the functional circuit to be tested through a chain test. The type of fault is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0.

[0018] A dedicated chain diagnostic vector generation unit for generating a corresponding dedicated chain diagnostic vector for each flip - flop, wherein for the corresponding positions of the flip - flop and its downstream flip - flops, they are set to fault values according to the fault type; adjusting the input value of the functional circuit such that the previous flip - flop of the flip - flop captures the opposite value of the fault value;

[0019] A scan chain fault test unit for performing a scan chain fault test using the dedicated chain diagnostic vector to obtain the position of the flip - flop where a fault occurs.

[0020] Furthermore, in the fault type test unit, after reading the circuit netlist file after inserting the scan chain, injecting stuck - at - 1 and stuck - at - 0 faults into each flip - flop in the scan chain to obtain a faulty circuit netlist; using periodic test vectors for chain testing to determine the fault types existing in the functional circuit scan chain;

[0021] In the dedicated chain diagnostic vector generation unit, in the dedicated chain diagnostic vector, the corresponding positions of the upstream flip - flops of the flip - flop are don't - care bits, randomly set to 0 or 1;

[0022] In the dedicated chain diagnostic vector generation unit, the method of adjusting the input value of the functional circuit such that the previous flip - flop of the flip - flop captures the opposite value of the fault value includes:

[0023] Setting constraint conditions, input ports, and output ports, where the constraint condition is that the corresponding positions of the flip - flop and its downstream flip - flops in the dedicated chain diagnostic vector are fault values, and calculating the output of the functional circuit by traversing all possible input combinations to obtain the input combination that satisfies the constraint condition;

[0024] In the dedicated chain diagnostic vector generation unit, the capture value of the flip - flop is set to the opposite value of the fault value;

[0025] In the scan chain fault test unit, saving the chain diagnostic vector and generating its corresponding testbench file, and performing a scan chain fault test using the testbench file to obtain the position of the flip - flop where a fault occurs.

[0026] The electronic device of the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, it implements the scan chain fault location method based on the dedicated chain diagnostic vector.

[0027] The computer - readable storage medium of the present invention stores a computer program. When the computer program is executed by a processor, it implements the scan chain fault location method based on the dedicated chain diagnostic vector.

[0028] Advantages: Compared with the prior art, the advantages of the present invention are as follows: (1) The traditional method is based on vectors for detecting functional circuit faults generated by ATPG, while the present invention can more accurately locate the fault positions in the scan chain by generating dedicated chain diagnostic vectors for each scan flip-flop and combining circuit logic analysis. Since each dedicated chain diagnostic vector is carefully designed to accurately stimulate different fault types, the diagnostic coverage and accuracy are improved. (2) The present invention first determines the fault types existing in the scan chain through chain diagnosis, and generates corresponding diagnostic vectors for the identified fault types. Different from the traditional method, the present invention does not need to introduce vectors of multiple fault types during the test process, thus effectively reducing the number of required test vectors and significantly shortening the test time. (3) Compared with the hardware-based scan chain diagnosis method, the present invention has significant advantages. Especially without adding additional hardware overhead, it can achieve efficient fault diagnosis. Traditional hardware methods usually need to add additional diagnostic circuits or logic units in the circuit for fault detection and location, which often leads to an increase in chip area and power consumption, and may even affect the performance of the circuit. However, the present invention only relies on the scan chain and the generated diagnostic vectors, and completes fault diagnosis through the simulation process, without changing the hardware structure or introducing additional hardware modules at all. Brief Description of the Drawings

[0029] Figure 1 It is a flowchart of the scan chain fault location method of the present invention.

[0030] Figure 2 It is a circuit structure diagram of the S27 circuit according to an embodiment of the present invention.

[0031] Figure 3 It is a schematic diagram of the stuck-at fault injection circuit according to an embodiment of the present invention.

[0032] Figure 4 It is a schematic diagram of calculating dedicated chain diagnostic vectors according to the circuit structure according to an embodiment of the present invention.

[0033] Figure 5 It is a schematic diagram of the stil format of the dedicated chain diagnostic vector according to an embodiment of the present invention.

[0034] Figure 6 It is a schematic diagram of the waveform of the dedicated chain diagnostic vector according to an embodiment of the present invention.

[0035] Figure 7 It is a schematic diagram of the stil file of the stuck-at-1 fault diagnostic vector according to an embodiment of the present invention.

[0036] Figure 8 It is a schematic diagram of the simulation waveform of the dedicated chain diagnostic vector according to an embodiment of the present invention. Detailed Embodiments

[0037] First, the process of scan testing and test vectors are briefly introduced. In scan testing, the generation of test vectors directly determines the effectiveness and efficiency of testing. A test vector is a set of bit vectors used to stimulate the input signals of a circuit. Each vector corresponds to a certain input configuration of the circuit, and its purpose is to verify whether the circuit can output as expected after receiving specific input signals. Generating high-quality test vectors is the key to ensuring the reliability, performance, and functional correctness of the circuit. Usually, test vectors simulate various input states of the circuit, stimulate the circuit, and detect its response to evaluate whether there are manufacturing defects in the circuit.

[0038] In scan testing, test vectors are first input into the internal circuit through the scan chain, and this process is called test vector shifting in. The scan chain is a series of cascaded flip-flops that allow the test equipment to input test data into the circuit one by one. Next, the circuit performs excitation operations according to the input test vectors, and this process is called the capture operation. After the capture operation, the circuit performs corresponding functional calculations or operations according to the input signals of the excitation, and outputs its state. Finally, test vector shifting out outputs the output or internal state of the circuit through the scan chain. By comparing it with the expected output, it is judged whether the circuit has correctly responded to the input signal. Test vector shifting in is the process of inputting the generated test vectors into the internal circuit through the scan chain. The scan chain is a series of cascaded flip-flops that allow the test equipment to input test data into the circuit flip-flop by flip-flop; the capture operation is the process in which the circuit is excited and performs calculations or operations according to the test vectors after the test vectors are shifted in. This step usually involves the normal functional operation of the circuit, adding excitation at the input end of the functional circuit, and calculating the corresponding output according to the input of the excitation. Test vector shifting out is the process of outputting the output or internal state of the circuit from the flip-flops in the scan chain. Through the shifting out operation, the captured state (i.e., the circuit response) can be extracted and compared with the expected output to determine whether the circuit is correct.

[0039] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings.

[0040] As Figure 1 shown, the scan chain fault location method based on dedicated chain diagnostic vectors of the present invention includes the following steps.

[0041] S1: Read in the circuit netlist file of the inserted scan chain structure, analyze the circuit netlist after inserting the scan chain, and determine the length of the scan chain.

[0042] S2: Inject stuck-at-1 and stuck-at-0 faults into the SI ports of each scan flip-flop (abbreviated as flip-flop) in the scan chain to obtain a faulty circuit netlist.

[0043] S3: Determine the type of fault existing in the scan chain through chain testing.

[0044] In the chain testing, first, the periodic test vector 0011 is shifted into the scan chain to stimulate the internal state of the circuit through each flip-flop. The output state is directly shifted out for comparison and analysis. If all the shifted-out values are 0 or all are 1, it can be determined that the circuit has a stuck-at-0 or stuck-at-1 fault.

[0045] S4: After determining the type of scan chain fault, generate corresponding dedicated chain diagnostic vectors for each flip-flop. The dedicated chain diagnostic vectors need to be designed for each flip-flop. Assuming that the flip-flop has a fault, set the vector downstream of it to the fault value;

[0046] After determining the downstream values of each flip-flop, further analyze the circuit logic to identify the propagation paths of the downstream flip-flops. Analyze these propagation paths to determine the influence range of the faulty flip-flop on the downstream flip-flops. Set the corresponding positions of the downstream flip-flops in the dedicated chain diagnostic vectors to the fault value to reduce the impact of the fault value on the functional circuit, thereby ensuring the controllability of the captured value.

[0047] S5: Generate dedicated chain diagnostic vectors corresponding to different flip-flops.

[0048] To ensure that the influence of the faulty flip-flop is effectively controlled, it is necessary to analyze the circuit logic to clarify the upstream values of the test vectors and the values at the inputs (PI) of the functional circuit. According to the type of the faulty flip-flop, adjust the input of the functional circuit input PI so that the faulty flip-flop and the previous flip-flop can capture the opposite value (i.e., the fault reverse value) of the faulty flip-flop, thereby determining the complete dedicated chain diagnostic vectors of the scan chain.

[0049] S6: Save the generated dedicated chain diagnostic vectors and generate corresponding testbench files for them to ensure that the diagnostic vectors are correctly verified in the simulation.

[0050] S7: Use the generated testbench files to simulate the faulty circuit. Through the VCS simulation tool, input the generated dedicated chain diagnostic vectors to obtain the simulation results and observe the output of the test_so port.

[0051] S8: Analyze the simulation results to obtain the accurate fault location.

[0052] When there is a fault in the scan chain, the faulty flip-flop will change the shifted-out value of its upstream flip-flop during the shift-out stage. Through the pre-designed dedicated chain diagnostic vectors, it can be ensured that the captured value remains unchanged, and the characteristics of these vectors are used to diagnose the location of the faulty flip-flop.

[0053] The present invention will be described in detail from five aspects below.

[0054] (1) Process of the scan chain fault location method based on dedicated chain diagnostic vectors.

[0055] A complete scan chain fault location process is divided into eight stages, namely reading the circuit file, fault injection, fault type determination, analyzing the circuit structure, generating chain diagnostic vectors, generating testbench, simulation, and obtaining the fault location result. Since the traditional scan chain diagnosis process requires adding additional circuits to the design, which increases the overhead, has low diagnostic efficiency, and limited accuracy in fault identification, to solve this problem, the present invention provides a scan chain fault location method based on dedicated chain diagnostic vectors, which solves the problems of low accuracy and slow diagnostic speed of the traditional method. The specific steps include: analyzing the circuit netlist, determining the scan chain length and injecting stuck-at-1 and stuck-at-0 faults; exciting the scan chain flip-flops with the periodic test vector 0011, and determining the fault type by judging whether the output value is all 0 or all 1; simulating the faults of each flip-flop to generate corresponding dedicated chain diagnostic vectors, and analyzing the propagation path of the downstream flip-flops to reduce the impact of the fault value on the functional circuit; adjusting the input end of the functional circuit to ensure capturing the opposite value of the faulty flip-flop; finally, generating and simulating and verifying the diagnostic vectors.

[0056] The present invention effectively improves the accuracy and speed of scan chain fault location. Compared with the traditional scan chain diagnosis method based on hardware, the present invention has significant advantages. Especially without increasing additional hardware overhead, it can efficiently achieve fault diagnosis. The traditional method usually needs to add additional diagnostic circuits or logic units in the circuit, which not only increases the chip area and power consumption, but also may affect the circuit performance. The present invention only relies on the scan chain and the generated diagnostic vectors, and completes the fault location through the simulation process, without modifying the hardware structure or introducing additional hardware modules, thus effectively avoiding related problems.

[0057] In addition, the present invention designs dedicated diagnostic vectors for each flip-flop, and combined with circuit logic analysis, can more accurately locate the fault position. Each test vector is carefully designed, and can select the corresponding diagnostic vector for precise excitation according to different fault types, thereby reducing the number of chain diagnostic vectors, improving the diagnostic coverage and accuracy, shortening the test cycle, and reducing the test time.

[0058] (2) Scan chain fault injection.

[0059] After reading the circuit netlist file after inserting the scan chain, a stuck at fault injection link is added. According to the scan chain structure of the circuit, stuck at faults are injected at the SI end of each flip-flop.

[0060] Refer to Figure 2, taking the S27 circuit netlist in the standard test circuit ISCAS’85 as an example, the G0, G1, G2, and G3 ports are functional input ports, and the G17 port is the functional output port; tests_si is the scan input port, and tests_so is the scan output port; SE is the scan enable port. When SE = 1, the test vector is shifted into SFF2, SFF1, and SFF0 from tests_si, and at the same time, the previous test vector is shifted out from the test_so port. When SE = 0, the D port of the scan flip-flop captures data from the combinational logic. The blif_clk_net is the clock port, which provides a clock for the scan flip-flop and is connected to the clk port of the flip-flop; rst is the reset port. When rst = 1, all SFFs are set to zero. After analyzing its scan chain structure, stuck-at-0 and stuck-at-1 faults are injected into the SI ports of the flip-flops SFF0, SFF1, and SFF2 in each scan chain, and the generated fault netlist is saved to prepare for subsequent simulation to verify the fault location.

[0061] (3) Chain testing determines the types of faults existing in the scan chain.

[0062] During the chain testing process, first, the periodic test vector 0011 is shifted into the scan chain. The internal state of the circuit is excited by each flip-flop, and its output value is directly shifted out for comparison and analysis. If all the shifted-out values are 0 or all are 1, it can be determined that the circuit has a stuck-at-0 or stuck-at-1 fault.

[0063] Refer to Figure 3 For the S27 circuit chain test, the test vector order is {SFF2, SFF1, SFF0}. The 001 vector is shifted into from the test_si port, and its output value is directly shifted out for comparison and analysis. When the output of the test_so port is 111, it indicates that one or more flip-flops in the scan chain have a stuck-at-1 fault; when the output of the test_so port is SFF2, SFF1, SFF0 = 000, it indicates that one or more flip-flops in the scan chain have a stuck-at-0 fault; when the output of the test_so port is 001, it indicates that the scan chain has no fault.

[0064] (4) Analyze the circuit structure to generate chain diagnostic vectors.

[0065] After determining the types of scan chain faults, corresponding dedicated chain diagnostic vectors are generated for each flip-flop. The flip-flops connected between the faulty flip-flop and the test_so are its downstream flip-flops, and the flip-flops connected between the faulty flip-flop and the test_si are its upstream flip-flops.

[0066] When a fault occurs, the fault flip-flop will change its downstream value, resulting in a change in the captured value. By designing a dedicated chain diagnostic vector, it is assumed that when a fault flip-flop fails, the value of its downstream flip-flop is set to the fault value, thereby ensuring that the dedicated chain diagnostic vector that is moved in is not affected and the captured value of the scan chain is stable.

[0067] The circuit logic is further analyzed to identify the propagation path of the downstream flip-flop and mask it to reduce the impact of the fault. At the same time, during the scan shift-in period, the faulty flip-flop only affects the downstream value and does not change the upstream value. By adjusting the value of the functional circuit input (PI), it is ensured that the flip-flop one bit above the faulty flip-flop captures its fault opposite value, thereby generating a complete chain diagnostic vector.

[0068] The following is an introduction through a case.

[0069] Assume that the result after the chain test is 111, indicating that there is a stuck-at-1 fault in the scan chain. At this time, the corresponding chain diagnostic vectors need to be generated for the three flip-flops. When a stuck-at-1 fault occurs at the SI end of SFF1, the value of SFF0 will be changed when the scan is shifted in, and it will be stuck at 1, thus affecting the capture value of the scan chain. Therefore, when designing the diagnostic vector corresponding to the stuck-at-1 fault of SFF1, the values ​​of SFF1 and SFF0 need to be set to 1 to ensure that the capture value of the scan chain will not be affected regardless of whether the SI port of SFF1 fails. Therefore, the test_si port is shifted into the vector test_si=11X. Among them, X represents a don't care bit.

[0070] During the scan shift-out cycle, the value of the upstream flip-flop in the scan chain will be affected by the fault of the downstream flip-flop. For example, when SFF1 is stuck-at-1, no matter what value SFF2 captures, the value of SFF2 will be stuck at 1 when it is shifted out. In order to make the stuck-at-1 fault of SFF1 intuitively observable, the captured value of SFF2 should be set to 0. Figure 4 As shown in the figure, by analyzing the S27 circuit, we know that the captured value of SFF2 comes from the nor_1 gate, whose signal is controlled by n1 and n2, and n2 is only connected to the G0 port through a NOT gate, which has good controllability. Therefore, setting the G0 port to 0 and n2 to 1 can ensure that the captured value of SFF2 is 0.

[0071] At the same time, the capture value of SFF1 is set to 0. When scanning the output, if the value of SFF1 is 0 and can be shifted out normally, and the value of SFF2 is stuck at 1, it means that the fault occurs at the SI end of SFF1. According to the S27 circuit diagram, the capture value of SFF1 is controlled by the nor_2 gate, and the nor_n2 gate is controlled by the Q end of SFF2. When the output of SFF2 is 1, the capture value of the D end of SFF1 is 0.

[0072] Finally, the chain diagnosis vector when SFF1 has a stuck-at-1 fault is determined as test_si = 111, and PI = G0, G1, G2, G3 = 0X1X.

[0073] Based on the above method, simulations are carried out for the two fixed fault types of each flip-flop. First, when a stuck-at-0 fault occurs in the scan chain, set test_si = 000 to ensure that the value scanned in is not affected by the fault. According to the calculation, when the input PI is G0, G1, G2, G3 = X0X1, the expected captured value test_so = 010. If the actual output value test_so = 000, the 1 captured by SFF1 is stuck at 0, proving that the fault occurs at the SI port of SFF0. If the actual output value test_so = 010 and the 1 captured by SFF1 can be normally output, it means that the fault occurs in the upstream scan unit of SFF0; when test_si = 000 and the input PI is G0, G1, G2, G3 = 1XXX, the expected captured value test_so = 101. If the actual output value test_so = 101 and the 1 captured by SFF2 can be normally output, it proves that the fault occurs at the SI port of SFF2. If the actual output value test_so = 001 and the 1 captured by SFF2 is stuck at 0 by the downstream fault, it means that the fault occurs at the SI port of SFF1;

[0074] Similarly, when a stuck-at-1 fault occurs in the scan chain, set test_si = 111 to ensure that the scan-in process is not affected by the stuck-at-1 fault. After calculation, when PI = G0, G1, G2, G3 = 0011, the expected captured value test_so = 000. Observe the output value. If test_so = 110, the fault occurs in SFF0; if test_so = 100, the fault occurs in SFF1; if test_so = 000, the fault occurs in SFF2.

[0075] In summary, for the fault diagnosis of the S27 circuit chain, the following diagnosis vectors are obtained:

[0076] When stuck-at-1: pattern0: test_si = 111, G0123 = 0X1X, test_so = 000;

[0077] When stuck-at-0: pattern0: test_si = 000, G0123 = X0X1, test_so = 010;

[0078] pattern1: test_si=000, G0123=1XXX, test_so=101;

[0079] For stuck-at-0 faults, only two chain diagnostic vectors are needed, while for stuck-at-1 faults, only one chain diagnostic vector is needed to achieve accurate positioning. These diagnostic vectors can effectively locate the fault and accurately identify the location where the fault occurs.

[0080] (5) Save the chain diagnostic vector to generate a testbench file for simulation.

[0081] After obtaining the chain diagnosis vector of each trigger, its irrelevant bit X is randomly filled, and fault simulation is performed to obtain the capture value corresponding to each vector.

[0082] Reference Figure 5 , the STIL file format of the dedicated chain diagnostic vector is as follows. `pattern 0` indicates the 0th dedicated chain diagnostic vector, which is the dedicated chain diagnostic vector. In the `load_unload` stage, that is, the shift-in stage, the value of `test_si` is 001. In the `multiclock_capture` stage, the value of the `_pi` port is composed of the 11 input ports of the circuit, that is, `_pi= G0 + G1 + G2 + G3 + blif_clk_net + reset + scan_clk + scan_rst + test_mode+ test_se + test_si`. In this stage, by applying one or more clock cycles, the trigger is able to capture the signal in the functional circuit, and the `_po` port value is measured, `_po = G17 + test_so`, where H is high level 1 and L is low level 0. During the chain test process, since the circuit is not captured and the dedicated chain diagnostic vector is only shifted in and out, the `test_se` value is set to 1, which means that the trigger still obtains the value from the previous trigger.

[0083] After the chain diagnostic vector is organized into a stil format file, the corresponding testbench file can be generated and the circuit can be simulated through VCS and the simulation results can be observed through Verdi. After simulating the circuit, the generated `.fsdb` waveform file can be used to observe the simulation results through the Verdi tool. Figure 6 , is the chain test result. After the dedicated chain diagnostic vector `001` is input into the `test_si` port, the result shifted out from the `test_so` port is `111` in the `pattern1` cycle. This result indicates that there is a stuck-at-1 fault in the scan chain.

[0084] Reference Figure 7 , which is the STIL file of the chain diagnosis vector corresponding to the stuck-at-1 fault found after the S27 circuit chain test. In the `load_unload` stage, the value of `test_si` is 111 in the shift-in stage. In the `multiclock_capture` stage, pi=0011P010100 is set, where G0, G1, G2, G3=0011, and blif_clk_net=P means applying a clock pulse. After saving, the testbench file is generated and the simulation results are observed.

[0085] Reference Figure 8 , the value shifted into `test_si` is 111, and when the capture clock is triggered, G0, G1, G2, G3 = 0011, and the result of shifting out of the `test_so` port is 000, so no value is stuck at 1. However, the result of the chain test shows that there is a stuck-at-1 fault in the scan chain, so it can be determined that the stuck-at-1 fault occurs at the SI port of SFF0.

[0086] The scan chain fault location system based on the dedicated chain diagnostic vector of the present invention comprises:

[0087] A fault type test unit, used to determine the fault type existing in the scan chain of the functional circuit to be tested through a chain test, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0;

[0088] A dedicated chain diagnostic vector generating unit is used to generate a corresponding dedicated chain diagnostic vector for each bit of the trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; and adjust the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value;

[0089] The scan chain fault test unit is used to perform a scan chain fault test using the dedicated chain diagnostic vector to obtain a trigger position where a fault occurs.

[0090] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the scan chain fault location method based on the dedicated chain diagnostic vector is implemented.

[0091] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the method for locating a scan chain fault based on a dedicated chain diagnostic vector is implemented.

[0092] The computer-readable storage medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and can be accessed by a computer.

[0093] The processor is configured to execute the computer program stored in the memory to implement the respective steps in the methods involved in the above embodiments.

Claims

1. A scan chain fault location method based on a dedicated chain diagnostic vector, characterized in that: The steps include: Step 1, determining the fault type existing in the scan chain of the functional circuit to be tested through chain testing, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; Step 2, generating a corresponding dedicated chain diagnostic vector for each bit of trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; adjusting the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; Step 3: Perform a scan chain fault test using the dedicated chain diagnostic vector to obtain the location of the trigger where the fault occurs.

2. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 1, read the circuit netlist file after inserting the scan chain, inject stuck-at-1 and stuck-at-0 faults into each trigger in the scan chain, and obtain the faulty circuit netlist; Use periodic test vectors to perform chain testing to determine the type of faults present in the functional circuit scan chain.

3. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 2, in the dedicated chain diagnostic vector, the corresponding position of the upstream trigger of the trigger is a don't care bit, which is randomly set to 0 or 1.

4. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 2, the method of adjusting the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value includes: Set constraints, input ports and output ports. The constraint is that the corresponding positions of the trigger and its downstream triggers in the dedicated chain diagnostic vector are fault values. By traversing all possible input combinations to calculate the output of the functional circuit, an input combination that meets the constraints is obtained.

5. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: In step 2, the capture value of the flip-flop is set to the opposite value of the fault value.

6. The scan chain fault location method based on dedicated chain diagnostic vector according to claim 1, characterized in that: Step 3 specifically includes saving the dedicated chain diagnostic vector and generating its corresponding testbench file, and performing a scan chain fault test using the testbench file to obtain the location of the trigger where the fault occurs.

7. A scan chain fault location system based on a dedicated chain diagnostic vector, characterized in that: include: A fault type test unit, used to determine the fault type existing in the scan chain of the functional circuit to be tested through a chain test, wherein the fault type is a stuck-at-1 fault or a stuck-at-0 fault, and the corresponding fault value is 1 or 0; A dedicated chain diagnostic vector generating unit is used to generate a corresponding dedicated chain diagnostic vector for each bit of the trigger, wherein the corresponding position of the trigger and its downstream trigger is set to a fault value according to the fault type; and adjust the input value of the functional circuit so that the previous trigger of the trigger captures the opposite value of the fault value; The scan chain fault test unit is used to perform a scan chain fault test using the dedicated chain diagnostic vector to obtain a trigger position where a fault occurs.

8. The scan chain fault location system based on dedicated chain diagnostic vector according to claim 7, characterized in that: In the fault type test unit, read the circuit netlist file after inserting the scan chain, inject stuck-at-1 and stuck-at-0 faults into each trigger in the scan chain, and obtain the faulty circuit netlist; Use periodic test vectors to perform chain testing to determine the type of faults present in the functional circuit scan chain; In the dedicated chain diagnostic vector generation unit, in the dedicated chain diagnostic vector, the corresponding position of the upstream flip-flop of the flip-flop is a don't care bit and is randomly set to 0 or 1; In a dedicated chain diagnostic vector generation unit, a method for adjusting a functional circuit input value so that an upper trigger of the trigger captures an opposite value of a fault value includes: Set constraints, input ports and output ports, where the constraints are that the corresponding positions of the trigger and its downstream triggers in the dedicated chain diagnostic vector are fault values, and calculate the output of the functional circuit by traversing all possible input combinations to obtain input combinations that meet the constraints; In the dedicated chain diagnostic vector generation unit, the capture value of the flip-flop is set to the opposite value of the fault value; In the scan chain fault test unit, a dedicated chain diagnostic vector is saved and a corresponding testbench file is generated. The scan chain fault test is performed using the testbench file to obtain the location of the trigger where the fault occurs.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the scan chain fault location method based on a dedicated chain diagnostic vector is implemented according to any one of claims 1 to 6.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the scan chain fault location method based on a dedicated chain diagnostic vector is implemented according to any one of claims 1 to 6.

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