Multichannel acquisition system for ultrasonic echo signals

Abstract

The invention provides a multichannel acquisition system for ultrasonic echo signals, which can be applied to the technical field of ultrasonic echo signal acquisition. The system comprises a logic control module used for generating a sampling control parameter according to a target instruction sent by an upper computer; the multi-channel acquisition module comprises an acquisition sub-module and a synchronous clock sub-module; the acquisition sub-module comprises a plurality of multi-channel acquisition units, the synchronous clock sub-module is used for generating a plurality of clock signals respectively used for the plurality of multi-channel acquisition units according to sampling control parameters, and the plurality of multi-channel acquisition units are used for synchronously acquiring ultrasonic echo signals according to the plurality of clock signals and the sampling control parameters; the ultrasonic echo signals are respectively converted into multi-channel digital signals to be sent to the logic control module, and the logic control module is also used for adjusting return delays respectively corresponding to the plurality of multi-channel acquisition units, so that the logic control module synchronously receives the multi-channel digital signals sent by the plurality of multi-channel acquisition units.

Description

Technical Field

[0001] The present invention relates to the technical field of ultrasonic echo signal acquisition, and more specifically, to a multi-channel acquisition system for ultrasonic echo signals. Background Art

[0002] In recent years, ultrasonic imaging technology has developed rapidly. Among them, ultrasonic synthetic aperture imaging technology, as an imaging technology with higher resolution and contrast in ultrasonic imaging technology, has been widely used in various fields. As the basis of ultrasonic imaging technology, the number of acquisition channels, the effective number of bits of AD conversion, and the acquisition frequency of ultrasonic echo will affect the final imaging accuracy.

[0003] In the process of realizing the concept of the present invention, it was found through research that at least there are sampling channels and effective sampling bit numbers in the relevant technology that are difficult to meet the requirements of ultrasonic echo acquisition, and the sampling and return of data of each channel are difficult to synchronize, resulting in low imaging accuracy. Summary of the invention

[0004] In view of this, the present invention provides a multi-channel acquisition system for ultrasonic echo signals.

[0005] One aspect of the present invention provides a multi-channel acquisition system for ultrasonic echo signals, comprising:

[0006] A logic control module, used to generate sampling control parameters according to the target instructions sent by the host computer; and a multi-channel acquisition module, including an acquisition submodule and a synchronous clock submodule; wherein the acquisition submodule includes multiple multi-channel acquisition units, and the synchronous clock submodule is used to generate multiple clock signals respectively used for the multiple multi-channel acquisition units according to the sampling control parameters, and the multiple multi-channel acquisition units are used to synchronously acquire ultrasonic echo signals according to the multiple clock signals and the sampling control parameters, and convert the ultrasonic echo signals into multi-channel digital signals respectively and send them to the logic control module, wherein the logic control module is also used to adjust the return delays corresponding to the multiple multi-channel acquisition units, so that the logic control module synchronously receives the multi-channel digital signals sent by the multiple multi-channel acquisition units.

[0007] According to an embodiment of the present invention, each multi-channel acquisition unit includes: a sensing subunit, which is used to acquire ultrasonic echo signals according to a clock signal corresponding to the current multi-channel acquisition unit, and convert the acquired ultrasonic echo signals into multi-channel analog signals; an adjusting subunit, which is used to amplify the received multi-channel analog signals and filter out noise signals in the multi-channel analog signals to obtain signals to be converted; and a converting subunit, which is used to convert the signals to be converted into multi-channel digital signals.

[0008] According to an embodiment of the present invention, the logic control module includes: a feedback submodule, which is used to process the multi-channel digital signals obtained by multiple multi-channel acquisition units, cache the obtained target sampling data, and send the target sampling data to the host computer until a transmission instruction from the host computer is received.

[0009] According to an embodiment of the present invention, the feedback submodule includes: a delay setting unit, which is used to adjust the feedback delay corresponding to each of the multiple multi-channel acquisition units according to the phase information of the multi-channel digital signal, so as to ensure that the feedback submodule synchronously receives the multi-channel digital signals sent by the multiple multi-channel acquisition units; a conversion unit, which is used to convert the multiple multi-channel digital signals into serial-to-parallel signals to obtain multiple multi-channel parallel data; an alignment unit, which is used to perform sliding processing on the multiple multi-channel parallel data respectively according to the predetermined calibration parallel data, so as to ensure that the multiple multi-channel parallel data are bit-aligned.

[0010] According to an embodiment of the present invention, a delay setting unit adjusts the return delay corresponding to each of the multiple multi-channel acquisition units according to the phase information of the multi-channel digital signal, including: for each multi-channel acquisition unit, determining the delay adjustment multiple corresponding to each of the multiple multi-channel digital signals according to the phase information of the multi-channel digital signal; adjusting the return delay corresponding to each of the multiple multi-channel digital signals according to the delay adjustment multiple corresponding to each of the multiple multi-channel digital signals and the predetermined delay.

[0011] According to an embodiment of the present invention, the feedback submodule further includes: a merging unit, which is used to merge the multiple multi-channel parallel data after bit alignment to obtain target sampling data; and a buffer unit, which is used to temporarily store the target sampling data until receiving a transmission instruction from the host computer and sending the target sampling data to the host computer.

[0012] According to an embodiment of the present invention, the logic control module further includes: a sampling control submodule, which is used to parse the target instruction sent by the host computer, obtain sampling control parameters, and initialize and configure the multi-channel acquisition module according to the sampling control parameters.

[0013] According to an embodiment of the present invention, the sampling control parameters include enable parameters and clock frequency parameters of a synchronous clock submodule and amplification gain parameters, filter band parameters and sampling parameters of multiple multi-channel acquisition units; the synchronous clock submodule generates multiple clock signals respectively used for multiple multi-channel acquisition units according to the sampling control parameters, including: according to the enable parameters and clock frequency parameters of the synchronous clock submodule, using the sampling control submodule to initialize and configure the synchronous clock submodule; according to the amplification gain parameters, filter band parameters and sampling parameters of the multiple multi-channel acquisition units, using the configured synchronous clock submodule to generate multiple clock signals respectively used for multiple multi-channel acquisition units, so that the multiple multi-channel acquisition units synchronously acquire ultrasonic echo signals within a sampling period.

[0014] According to an embodiment of the present invention, a data transmission module is further included, wherein the data transmission module is used to buffer the target instructions sent to the logic control module and the target sampling data sent to the host computer.

[0015] According to an embodiment of the present invention, the multi-channel acquisition module further includes: an auxiliary circuit submodule, including: an impedance matching circuit for adjusting the sensing subunits in the multiple multi-channel acquisition units to a pure resistive load to achieve impedance matching of the multiple multi-channel acquisition units.

[0016] According to an embodiment of the present invention, the synchronous clock submodule generates multiple clock signals respectively used for multiple multi-channel acquisition units according to the sampling control parameters generated by the logic control module. The multiple multi-channel acquisition units synchronously acquire ultrasonic echo signals according to the multiple clock signals and the sampling control parameters, and convert the ultrasonic echo signals into multi-channel digital signals and send them to the logic control module. The logic control module can also adjust the return delays corresponding to the multiple multi-channel acquisition units, thereby realizing high-precision synchronous acquisition and synchronous return of multi-channel ultrasonic echo signals, and flexibly controlling the sampling rate through the target instructions of the host computer. At the same time, the sampling control parameters can change the various parameters of the multi-channel acquisition unit, so that the multi-channel acquisition system of ultrasonic echo signals is suitable for various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of the architecture of a multi-channel acquisition system for ultrasonic echo signals according to an embodiment of the present invention is shown.

[0019] Figure 2 The output bus timing diagram of the acquisition chip according to the embodiment of the present invention is shown.

[0020] Figure 3A schematic diagram showing the working principle of the backhaul submodule according to an embodiment of the present invention is shown.

[0021] Figure 4 An overall schematic diagram of a multi-channel acquisition system for ultrasonic echo signals according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0022] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0024] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0026] In the embodiments of the present invention, the collection, updating, analysis, processing, use, transmission, provision, disclosure, storage and other aspects of the data involved (for example, including but not limited to user personal information) are in compliance with the provisions of relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. In particular, necessary measures are taken for user personal information to prevent illegal access to user personal information data and maintain the security of user personal information and network security.

[0027] Due to its special physical properties, ultrasound has important applications in the industrial and medical fields. For commonly used ultrasonic data acquisition systems, the acquisition resolution is usually between 12-bit and 16-bit, the number of channels is between 16-32, and the sampling rate is generally not more than 10MSPS. However, when the commonly used data acquisition system is loaded with ultrasonic sensors, the effective acquisition resolution will be greatly reduced. At the same time, ultrasonic synthetic aperture imaging technology usually requires 64 to 128 or even more acquisition channels. When the imaging accuracy is required to be above 0.1mm, the sampling rate should be greater than 50MHz. The current acquisition system is difficult to simultaneously meet the sampling of multi-channel, high-precision and high-effective-bit ultrasonic echo signals.

[0028] In view of this, an embodiment of the present invention provides a multi-channel acquisition system for ultrasonic echo signals, comprising:

[0029] A logic control module, used to generate sampling control parameters according to the target instructions sent by the host computer; and a multi-channel acquisition module, including an acquisition submodule and a synchronous clock submodule; wherein the acquisition submodule includes multiple multi-channel acquisition units, and the synchronous clock submodule is used to generate multiple clock signals respectively used for the multiple multi-channel acquisition units according to the sampling control parameters, and the multiple multi-channel acquisition units are used to synchronously acquire ultrasonic echo signals according to the multiple clock signals and the sampling control parameters, and convert the ultrasonic echo signals into multi-channel digital signals respectively and send them to the logic control module, wherein the logic control module is also used to adjust the return delays corresponding to the multiple multi-channel acquisition units respectively, so that the logic control module synchronously receives the multi-channel digital signals sent by the multiple multi-channel acquisition units.

[0030] Figure 1 FIG. 1 is a schematic diagram showing the architecture of a multi-channel acquisition system for ultrasonic echo signals according to an embodiment of the present invention. It should be noted that: Figure 1 The examples shown are merely examples of system architectures to which the embodiments of the present invention may be applied, to help those skilled in the art understand the technical content of the present invention, but do not mean that the embodiments of the present invention may not be used in other devices, systems, environments or scenarios.

[0031] like Figure 1 As shown, the embodiment 100 includes a host computer 110, a logic control module 120, a multi-channel acquisition module 130 and an ultrasonic probe 140. The multi-channel acquisition module 130 includes an acquisition submodule 132 and a synchronous clock submodule 131, and the acquisition submodule 132 includes a plurality of multi-channel acquisition units 132 (1).

[0032] According to an embodiment of the present invention, the host computer 110 can send a sampling requirement in the form of a target instruction to the logic control module 120. The logic control module 120 is used to generate a sampling control parameter according to the target instruction sent by the host computer 110. The synchronous clock submodule 131 is used to generate a plurality of clock signals respectively used for a plurality of multi-channel acquisition units 132 (1) according to the sampling control parameters. The plurality of multi-channel acquisition units 132 (1) are used to synchronously acquire ultrasonic echo signals according to the plurality of clock signals and the sampling control parameters, and convert the ultrasonic echo signals into multi-channel digital signals and send them to the logic control module 120.

[0033] According to an embodiment of the present invention, the logic control module 120 may adopt a field programmable gate array (FPGA), and the synchronous clock generation module may include a clock regulator and an external filtering circuit. The clock regulator may generate multiple frequency-adjustable clock signals, and the clock jitter is less than 600 fs (femtoseconds), and each clock signal corresponds to a multi-channel acquisition unit 132 (1).

[0034] According to an embodiment of the present invention, the synchronous clock submodule generates multiple clock signals respectively used for multiple multi-channel acquisition units according to the sampling control parameters generated by the logic control module. The multiple multi-channel acquisition units synchronously acquire ultrasonic echo signals according to the multiple clock signals and the sampling control parameters, and convert the ultrasonic echo signals into multi-channel digital signals and send them to the logic control module. The logic control module can also adjust the return delays corresponding to the multiple multi-channel acquisition units, thereby realizing high-precision synchronous acquisition and synchronous return of multi-channel ultrasonic echo signals, and flexibly controlling the sampling rate through the target instructions of the host computer. At the same time, the sampling control parameters can change the various parameters of the multi-channel acquisition unit, so that the multi-channel acquisition system of ultrasonic echo signals is suitable for various application scenarios.

[0035] It should be understood that Figure 1 The number of logic control modules, synchronous clock submodules and multi-channel acquisition units in the embodiment is only . According to the implementation requirements, there can be any number of logic control modules, synchronous clock submodules and multi-channel acquisition units.

[0036] According to an embodiment of the present invention, each multi-channel acquisition unit includes: a sensing subunit, which is used to acquire ultrasonic echo signals according to a clock signal corresponding to the current multi-channel acquisition unit, and convert the acquired ultrasonic echo signals into multi-channel analog signals; an adjusting subunit, which is used to amplify the received multi-channel analog signals and filter out noise signals in the multi-channel analog signals to obtain signals to be converted; and a converting subunit, which is used to convert the signals to be converted into multi-channel digital signals.

[0037] According to an embodiment of the present invention, the regulating subunit includes an LNA (low noise preamplifier), a VGA (adjustable gain amplifier circuit), and an AAF (programmable filter). The conversion subunit can be a 12-bit AD converter. The low noise preamplifier (LNA) is used to amplify the received ultrasonic echo signal to increase the signal strength, the adjustable gain amplifier (VGA) further adjusts the amplified signal amplitude to adapt to ultrasonic echo signals of different strengths, and the programmable filter (AAF) is used to filter out noise in the analog signal to ensure the purity of the signal, thereby obtaining a high-quality signal to be converted.

[0038] According to the embodiment of the present invention, a plurality of acquisition chips and sensors loaded at their front ends constitute a multi-channel acquisition unit of an acquisition submodule.

[0039] For example, the acquisition submodule includes 8 multi-channel acquisition units, each of which includes an 8-channel acquisition chip, and can realize the acquisition of 8×8=64 channels of ultrasonic echo signals.

[0040] According to the embodiment of the present invention, by changing various parameters related to the multi-channel acquisition unit through target instruction control of the host computer, the multi-channel acquisition unit can be adapted to various application scenarios.

[0041] According to an embodiment of the present invention, the system further comprises a data transmission module, wherein the data transmission module is used for buffering target instructions sent to the logic control module and target sampling data sent to the host computer.

[0042] According to the embodiment of the present invention, the data transmission module serves as an intermediate buffer unit between the logic control module and the host computer, and can realize high-bandwidth data transmission with the logic control module and the host computer, and the transmission speed can reach 3Gb / s.

[0043] For example, the data transmission module may be a microcontroller unit (MCU), which is connected via a data bus interface to achieve high-speed data interaction with a host computer and a logic control module.

[0044] According to an embodiment of the present invention, a data transmission module is set between the logic control module and the host computer to buffer the data interaction between the logic control module and the host computer, which improves the real-time performance and throughput of the system, and is also conducive to enhancing the scalability and compatibility of the system, and better meets the requirements of high precision, high sampling rate and multi-channel acquisition.

[0045] According to an embodiment of the present invention, the multi-channel acquisition module further includes: an auxiliary circuit submodule, including: an impedance matching circuit for adjusting the sensing subunits in the multiple multi-channel acquisition units to a pure resistive load to achieve impedance matching of the multiple multi-channel acquisition units.

[0046] According to an embodiment of the present invention, the auxiliary circuit submodule further includes a power supply circuit, which can provide a stable power supply voltage and a reference voltage source, thereby reducing the influence of power supply ripple on multi-channel digital signals.

[0047] According to the embodiment of the present invention, the impedance matching circuit adjusts the sensor to a pure resistive load, so that the impedance of the sensor subunit and the acquisition chip are directly matched, thereby improving the energy conversion efficiency of the conversion subunit.

[0048] According to an embodiment of the present invention, the logic control module includes: a feedback submodule, which is used to process the multi-channel digital signals obtained by multiple multi-channel acquisition units, cache the obtained target sampling data, and send the target sampling data to the host computer until a transmission instruction from the host computer is received.

[0049] According to an embodiment of the present invention, there may be differences in format, timing, etc. between the multi-channel digital signals output by each multi-channel acquisition unit. The feedback sub-module must first process the differences between the multiple multi-channel digital signals, such as performing serial-to-parallel conversion, data alignment, and other operations to obtain target sampling data. The feedback sub-module will cache the target sampling data in order to balance the difference between processing speed and transmission speed, wait for the host computer to issue a transmission instruction, and send the cached target sampling data to the host computer.

[0050] According to the embodiment of the present invention, the feedback submodule can ensure the integrity of the target sampling data by processing and caching the multi-channel digital signal, avoiding loss or error during the transmission and processing. At the same time, the caching of the target sampling data allows the acquisition unit to continuously sample and feedback, improving the working efficiency of the entire system, flexibly transmitting data according to the instructions of the host computer, and enhancing the flexibility and configurability of the system.

[0051] According to an embodiment of the present invention, the logic control module further includes: a sampling control submodule, which is used to parse the target instruction sent by the host computer, obtain sampling control parameters, and initialize and configure the multi-channel acquisition module according to the sampling control parameters.

[0052] According to an embodiment of the present invention, the host computer determines the initialization configuration parameters of each module according to actual conditions such as sampling requirements, echo waveform and waveform propagation medium, and synthesizes the initialization configuration parameters into target instructions by adding a frame header, and sends them to the data transmission module through an interface. The data transmission module transmits the target instructions to the sampling control submodule through the serial communication interface. The sampling control submodule parses the target instructions sent by the host computer and stores the initialization configuration parameters of each module in the corresponding internal register according to the message frame header.

[0053] According to an embodiment of the present invention, in addition to generating sampling control parameters to initialize the configuration of the multi-channel acquisition module, the logic control module also generates corresponding initialization configuration parameters to initialize the configuration of the logic control module itself.

[0054] For example, the initialization configuration parameters corresponding to the logic control module itself include sampling depth (duration), delay number of each channel, etc.

[0055] According to an embodiment of the present invention, the sampling control parameters include enable parameters and clock frequency parameters of a synchronous clock submodule and amplification gain parameters, filter band parameters and sampling parameters of multiple multi-channel acquisition units; the synchronous clock submodule generates multiple clock signals respectively used for multiple multi-channel acquisition units according to the sampling control parameters, including: according to the enable parameters and clock frequency parameters of the synchronous clock submodule, using the sampling control submodule to initialize and configure the synchronous clock submodule; according to the amplification gain parameters, filter band parameters and sampling parameters of the multiple multi-channel acquisition units, using the configured synchronous clock submodule to generate multiple clock signals respectively used for multiple multi-channel acquisition units, so that the multiple multi-channel acquisition units synchronously acquire ultrasonic echo signals within a sampling period.

[0056] According to an embodiment of the present invention, the sampling control parameters are used to initialize the configuration of the multi-channel acquisition module through the connection bus between the logic control module, the synchronous clock submodule and the acquisition chip. After the initialization configuration of each module is completed, the host computer sends a target instruction, and the logic control module receives the target instruction and controls the multi-channel acquisition module to perform synchronous sampling according to the set initialization configuration parameters.

[0057] According to an embodiment of the present invention, the enable parameter is used to control whether the synchronous clock submodule starts working. When the enable parameter is in a valid state, the synchronous clock submodule is activated and starts to generate a clock signal; in an invalid state, it is in a dormant or closed state and does not generate a clock signal. The clock frequency parameter is used to determine the frequency of the clock signal generated by the synchronous clock submodule. Different ultrasonic echo signal acquisition requirements may correspond to different clock frequencies to ensure that accurate and complete signals are acquired.

[0058] According to an embodiment of the present invention, the amplification gain parameter is used to set the amplification factor of the regulating subunit so that the signal strength reaches an appropriate range, which is convenient for subsequent processing and analysis. The filter band parameter is used to set the passband range of the filter circuit such as the filter in the regulating subunit to filter out noise and useless signals and improve the quality of the signal. The sampling parameter is used to determine the sampling method and frequency of the multi-channel acquisition unit for the ultrasonic echo signal, to ensure that the collected signal can accurately reflect the characteristics of the original ultrasonic echo signal, and avoid the problem of insufficient sampling or over-sampling.

[0059] According to an embodiment of the present invention, the multi-channel acquisition module is initialized and configured through sampling control parameters to ensure that the synchronous clock submodule and the acquisition submodule can be controlled collaboratively so that each multi-channel acquisition unit can synchronously acquire the ultrasonic echo signal, further improving the sampling accuracy so that the subsequently transmitted data has a higher quality.

[0060] According to an embodiment of the present invention, the feedback submodule includes: a delay setting unit, which is used to adjust the feedback delay corresponding to each of the multiple multi-channel acquisition units according to the phase information of the multi-channel digital signal, so as to ensure that the feedback submodule synchronously receives the multi-channel digital signals sent by the multiple multi-channel acquisition units; a conversion unit, which is used to convert the multiple multi-channel digital signals into serial-to-parallel signals to obtain multiple multi-channel parallel data; an alignment unit, which is used to perform sliding processing on the multiple multi-channel parallel data respectively according to the predetermined calibration parallel data, so as to ensure that the multiple multi-channel parallel data are bit-aligned.

[0061] To better understand the process of the return submodule receiving the multi-channel digital signal returned by the acquisition submodule, the following takes the AD9278 acquisition chip as an example. Figure 2 Provide further explanation.

[0062] Figure 2 The output bus timing diagram of the acquisition chip according to the embodiment of the present invention is shown.

[0063] like Figure 2 As shown, taking the acquisition chip AD9278 as an example, after the sampling is completed, the ultrasonic echo signal AIN from the N-1th sampling to the Nth sampling is obtained, and the AD9278 chip is respectively based on the first delay t PD , the second delay t FCO and the third delay t CPD , output multi-channel digital signals, calibration digital signals and accompanying clocks through the DOUT, FCO, and DCO differential pins, and transmit them in a double-edge form. Multi-channel digital signals are output in serial communication mode, and each frame of data can consist of 12 bits. The clock frequency of the calibration digital signal is the same as the clock frequency generated by the synchronous clock submodule, and is aligned with the data phase of each frame DOUT+ / DOUT- output. Therefore, the multi-channel digital signal of the DOUT+ / DOUT- serial-to-parallel conversion can be calibrated by the clock of the calibration digital signal. The accompanying clock represents the control clock of the acquisition chip transmission bus. The delay setting unit receives the accompanying clock and uses it to process the DOUT+ / DOUT- and FCO+ / FCO- data.

[0064] For example: When the sampling frequency is F clk (Unit: MHz), the frequency F of the accompanying clock DCO It can be expressed as the following formula (1).

[0065] (1)

[0066] Among them, the delay t of the channel FCO+ / FCO- corresponding to the calibration digital signal relative to the accompanying clock FRAME It can be expressed as the following formula (2).

[0067] (2)

[0068] Among them, the delay t of the channel DOUT+ / DOUT- corresponding to the multi-channel digital signal relative to the accompanying clock DATA It can be expressed as the following formula (3).

[0069] (3)

[0070] In F clk =50MHz, F DCO is 300MHz, with the clock period T DCO =3.33(ns). Since DOUT is transmitted in double-edge form, DOUT transmits 2 bits of data for each clock cycle, and the duration of single bit data is t BIT =1.66(ns). t FRAME With t DATA The range is between 500 ps and 1100 ps.

[0071] Therefore, in order to obtain accurate multi-channel digital signals, the feedback submodule should satisfy the following formula (4) when receiving data.

[0072] (4)

[0073] Due to t FRAME With t DATA Affected by the performance of the device itself, and factors such as subsequent wiring and internal routing of the logic control module will change the delay relationship of each channel. Therefore, a delay setting unit is designed in the sampling data receiving module to adjust the return delay corresponding to each of the multiple multi-channel digital signals to ensure that the return sub-module synchronously receives multiple multi-channel digital signals and avoid the occurrence of metastable phenomena during data reception.

[0074] According to an embodiment of the present invention, the conversion unit is driven by the clock DCO, and performs 12-bit serial-to-parallel conversion on the data output by DOUT+ / DOUT- and FCO+ / FCO- to obtain two groups of 12-bit data.

[0075] According to an embodiment of the present invention, the alignment unit performs a sliding operation on the above two groups of 12-bit data, wherein the 12-bit data converted by FCO+ / FCO- is used as predetermined calibrated parallel data, and is converted into a 111111_000000 format by a sliding operation, and then the obtained 12-bit multi-channel parallel data is subjected to the same sliding operation to ensure that multiple multi-channel parallel data are bit-aligned.

[0076] According to an embodiment of the present invention, the feedback submodule further includes: a merging unit, which is used to merge the multiple multi-channel parallel data after bit alignment to obtain target sampling data; and a buffer unit, which is used to temporarily store the target sampling data until receiving a transmission instruction from the host computer and sending the target sampling data to the host computer.

[0077] The following Figure 3 Take the example to further explain the working principle of the feedback submodule.

[0078] Figure 3 A schematic diagram showing the working principle of the backhaul submodule according to an embodiment of the present invention is shown.

[0079] like Figure 3 As shown, multiple acquisition chips 310 send multi-channel digital signals, calibration digital signals and accompanying clocks to the delay setting unit 320 of the return submodule through their respective pins DOUT, FCO, and DCO. The delay setting unit includes multiple delay setting subunits 321, which respectively adjust the return delays corresponding to the multi-channel digital signals of the multiple acquisition chips, and send the multiple multi-channel digital signals after delay adjustment to the conversion unit 330 for serial-to-parallel conversion. The conversion unit 330 sends the multi-channel parallel data to the alignment unit 340. The merging unit 350 receives the bit-aligned multi-channel parallel data, merges them and sends them to the buffer unit 360 until receiving the transmission instruction of the host computer, and sends the merged target sampling data to the host computer.

[0080] According to an embodiment of the present invention, a delay setting unit adjusts the return delay corresponding to each of the multiple multi-channel acquisition units according to the phase information of the multi-channel digital signal, including: for each multi-channel acquisition unit, determining the delay adjustment multiple corresponding to each of the multiple multi-channel digital signals according to the phase information of the multi-channel digital signal; adjusting the return delay corresponding to each of the multiple multi-channel digital signals according to the delay adjustment multiple corresponding to each of the multiple multi-channel digital signals and the predetermined delay.

[0081] According to an embodiment of the present invention, the process of adjusting the return delay corresponding to each of the plurality of multi-channel digital signals according to the delay adjustment multiple and the predetermined delay corresponding to each of the plurality of multi-channel digital signals can be expressed as the following formula (5).

[0082] (5)

[0083] Where n is the delay multiple, n∈(0~31). T tap Indicates a scheduled delay.

[0084] According to an embodiment of the present invention, the predetermined delay T tap It can be determined according to the following formula (6).

[0085] (6)

[0086] The predetermined delay period T=5ns. Accordingly, to satisfy the above formula (4), the range of the return delay T is 0~2.5ns.

[0087] According to an embodiment of the present invention, the feedback sub-module works in coordination with the delay setting unit, the conversion unit, the alignment unit, the merging unit and the cache unit to perform synchronization, format conversion, data alignment, merging and cache transmission on the multi-channel digital signals output by multiple multi-channel acquisition units, thereby ensuring the accuracy, completeness and orderliness of the target sampling data ultimately transmitted to the host computer, and providing reliable data support for the host computer to perform subsequent analysis, diagnosis and other operations based on these data.

[0088] Figure 4 An overall schematic diagram of a multi-channel acquisition system for ultrasonic echo signals according to an embodiment of the present invention is shown.

[0089] like Figure 4 As shown, the system includes a host computer 110, a data transmission module 410, a logic control module and a multi-channel acquisition module. Among them, the logic control module includes a feedback submodule 122 and a sampling control submodule 121, and the feedback submodule includes a delay setting unit 320, a conversion unit 330, an alignment unit 340, a merging unit 350 and a cache unit 360. The multi-channel acquisition module includes a synchronous clock submodule 131, an acquisition submodule 132, an impedance matching circuit 133 and a power supply circuit 134.

[0090] According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits, or at least part of the functions of any one of them can be implemented in one module. According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits can be split into multiple modules for implementation. According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits can be at least partially implemented as hardware circuits, such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems on chips, systems on substrates, systems on packages, application specific integrated circuits (ASICs), or can be implemented by hardware or firmware in any other reasonable way of integrating or packaging the circuit, or by any one of the three implementation methods of software, hardware, and firmware, or by a proper combination of any of them. Alternatively, according to the embodiments of the present invention, one or more of the modules, submodules, units, and subunits can be at least partially implemented as computer program modules, and when the computer program modules are run, the corresponding functions can be executed.

[0091] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments of the present invention can be combined and / or combined in various ways, even if such a combination or combination is not explicitly recorded in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features recorded in the various embodiments of the present invention can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present invention.

[0092] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination advantageously. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A multi-channel acquisition system for ultrasonic echo signals, characterized in that: include: A logic control module is used to generate sampling control parameters according to the target instructions sent by the host computer; as well as Multi-channel acquisition module, including acquisition submodule and synchronous clock submodule; Among them, the acquisition submodule includes multiple multi-channel acquisition units, the synchronous clock submodule is used to generate multiple clock signals respectively used for the multiple multi-channel acquisition units according to the sampling control parameters, and the multiple multi-channel acquisition units are used to synchronously acquire ultrasonic echo signals according to the multiple clock signals and sampling control parameters, and convert the ultrasonic echo signals into multi-channel digital signals respectively and send them to the logic control module, wherein the logic control module is also used to adjust the return delays corresponding to the multiple multi-channel acquisition units respectively, so that the logic control module synchronously receives the multi-channel digital signals sent by the multiple multi-channel acquisition units.

2. The system according to claim 1, characterized in that Each of the multi-channel acquisition units comprises: A sensor subunit, configured to collect the ultrasonic echo signal according to the clock signal corresponding to the current multi-channel acquisition unit, and convert the collected ultrasonic echo signal into a multi-channel analog signal; The regulating subunit is used to amplify the received multi-channel analog signal and filter out the noise signal in the multi-channel analog signal to obtain a signal to be converted; The conversion subunit is used to convert the signal to be converted into the multi-channel digital signal.

3. The system according to claim 2, characterized in that The logic control module comprises: The feedback submodule is used to process the multi-channel digital signals obtained by the multiple multi-channel acquisition units, cache the obtained target sampling data, and send the target sampling data to the host computer until receiving the transmission instruction of the host computer.

4. The system according to claim 3, characterized in that The feedback submodule includes: A delay setting unit, used to adjust the return delay corresponding to each of the multiple multi-channel acquisition units according to the phase information of the multi-channel digital signal, so as to ensure that the return submodule synchronously receives the multi-channel digital signal sent by the multiple multi-channel acquisition units; A conversion unit, used for performing serial-to-parallel conversion on a plurality of the multi-channel digital signals to obtain a plurality of multi-channel parallel data; The alignment unit is used to perform bit sliding processing on the plurality of multi-channel parallel data respectively according to the predetermined calibration parallel data, so as to ensure that the plurality of multi-channel parallel data are bit-aligned.

5. The system according to claim 4, characterized in that The delay setting unit adjusts the return delay corresponding to each of the plurality of multi-channel acquisition units according to the phase information of the multi-channel digital signal, including: For each of the multi-channel acquisition units, determining a delay adjustment multiple corresponding to each of the plurality of multi-channel digital signals according to the phase information of the multi-channel digital signal; According to the delay adjustment multiples and the predetermined delay corresponding to each of the plurality of multi-channel digital signals, the return delay corresponding to each of the plurality of multi-channel digital signals is adjusted.

6. The system according to claim 4, characterized in that The feedback submodule also includes: A merging unit, used for merging the plurality of multi-channel parallel data after bit alignment to obtain the target sampling data; The buffer unit is used to temporarily store the target sampling data until receiving a transmission instruction from the host computer, and then sending the target sampling data to the host computer.

7. The system according to claim 3, characterized in that The logic control module also includes: The sampling control submodule is used to parse the target instruction sent by the host computer to obtain sampling control parameters, and initialize the configuration of the multi-channel acquisition module according to the sampling control parameters.

8. The system according to claim 7, characterized in that The sampling control parameters include the enabling parameters and clock frequency parameters of the synchronous clock submodule and the amplification gain parameters, filter frequency band parameters and sampling parameters of the multiple multi-channel acquisition units; The synchronous clock submodule generates a plurality of clock signals respectively used for the plurality of multi-channel acquisition units according to the sampling control parameters, including: Initialize and configure the synchronous clock submodule using the sampling control submodule according to the enable parameter and clock frequency parameter of the synchronous clock submodule; According to the amplification gain parameters, filter band parameters and sampling parameters of the multiple multi-channel acquisition units, the configured synchronous clock submodule is used to generate multiple clock signals respectively used for the multiple multi-channel acquisition units, so that the multiple multi-channel acquisition units synchronously acquire the ultrasonic echo signals within a sampling period.

9. The system according to claim 3, characterized in that It also includes a data transmission module, wherein the data transmission module is used to buffer the target instructions sent to the logic control module and the target sampling data sent to the host computer.

10. The system according to claim 2, characterized in that The multi-channel acquisition module also includes: Auxiliary circuit submodule, including: The impedance matching circuit is used to adjust the sensor subunits in the multiple multi-channel acquisition units to a pure resistive load to achieve impedance matching of the multiple multi-channel acquisition units.

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