CPU (Central Processing Unit) synchronization system and method based on double CPLD (Complex Programmable Logic Device) bidirectional control

Abstract

The invention provides a CPU (Central Processing Unit) synchronization system and method based on double CPLD (Complex Programmable Logic Device) bidirectional control, and relates to the technical field of chip verification. Comprising a master CPLD and a slave CPLD. The pins of each Die are classified according to function signals and then are connected with the CPLD with the closest physical distance; the master CPLD and the slave CPLD are connected through four bidirectional signal lines and one direction control signal line; the direction control signal line is used for controlling the data direction of the four bidirectional signal lines; the four bidirectional signal lines are used for carrying out data transmission between the double CPLDs according to the data direction determined by the direction control signal line, and the four bidirectional signal lines can be switched to be input or output at any moment so as to complete time sequence synchronization of the CPU; according to the method, the problems of resource limitation and signal transmission caused by the fact that pins are concentrated on a single CPLD are solved, and it is guaranteed that all the Dies can keep consistent and reliable in the starting, initializing and running processes.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA) and chip verification, and in particular to a CPU synchronization system and method based on dual CPLD bidirectional control. Background Art

[0002] In traditional verification platform design, a single CPLD is usually used to manage all CPU pins. This solution is suitable for CPU designs with a small number of pins and simpler functions.

[0003] Limitations of single CPLD solution; Insufficient resources: A single CPLD is limited in the number of logic units and pins, making it difficult to meet the comprehensive verification requirements of multi-die CPU pins, resulting in many functions not being covered.

[0004] Inflexible PCB routing and difficult stray signal routing: The single CPLD solution requires access to a large number of CPU pins in a limited space, which places extremely high demands on PCB routing. Since the CPLD is small in area and has dense routing, it is difficult to achieve flexible routing. Especially for multi-die CPUs, the pins of each die may be distributed in different areas of the chip. When a single CPLD centrally connects these pins, the difficulty of PCB routing increases significantly.

[0005] Difficulty in debugging and maintenance: The presence of stray signals increases the complexity of system debugging. After the PCB design is completed, signal adjustment is difficult and the system maintenance cost increases.

[0006] A highly complex CPU verification platform needs to ensure that each IO and function can be fully verified under limited resource conditions. If the CPU is made up of 4 Dies, the number of pins that need to be verified by CPLD is as high as 700. Its functional verification platform mainly verifies whether all the interface functions of the CPU are correct. In addition to special interfaces such as DDR, PCIe, and high-speed interconnection, each Die also has commonly used low-speed communication interfaces such as UART, SPI, JTAG, I2C, LPC, general GPIO, function configuration, function status and other special function GPIOs that need to be switched internally by CPLD, functional testing or monitoring. Due to the ballmap distribution of the CPU, the two CPLDs have to be distributed on both sides of the CPU. The PCB signal layer is limited, and it is very difficult to distribute the pins of the same function of the CPU (4 Dies) on one CPLD routing, so it is inevitable that there will be pin allocation problems between the two CPLDs and the CPU.

[0007] 4 Die CPU startup and initialization, the interconnection between internal Dies has a certain timing relationship, and the external enable is controlled by the Die initialization completion signal. Therefore, the necessary communication signals must be retained between the two CPLDs to synchronize and ensure similar timing control as mentioned above.

[0008] With the widespread application of multi-die CPUs in the field of high-performance computing, the number of CPU pins and the types of functions are showing a sharp increase. In multi-die packaged CPUs, the startup, interconnection and initialization of multiple dies usually have strict timing requirements. At the same time, due to the large number of pins (such as more than 8,000), the verification platform often requires multiple CPLDs to process these IO signals. However, the number of PCB signal layers and wiring resources are limited. How to reasonably allocate pins and ensure timing coordination and signal synchronization between multiple CPLDs has become an urgent problem to be solved.

[0009] Limitations of current dual-CPLD communication solutions; I2C communication has limited bandwidth and speed: I2C is a low-speed serial communication protocol suitable for low-speed data transmission, but it is insufficient in timing control and high-speed signal synchronization of multi-die CPUs. The I2C communication bandwidth is low and cannot meet the timing synchronization requirements of the CPU during startup, initialization and interconnection, making it difficult to achieve accurate signal coordination.

[0010] Directional limitation of SPI communication: SPI is a high-speed communication protocol that supports full-duplex communication, but it is mainly used for data transmission between master and slave devices and does not support multiple master devices sharing the communication bus. Communication between dual CPLDs requires flexible bidirectional data transmission and timing control, while the fixed directionality of traditional SPI limits the free communication between dual CPLDs and makes it difficult to adapt to the complex signal interaction between multiple CPU dies.

[0011] The signal line resource consumption of the parallel bus is large: the parallel bus can provide higher data transmission speed and wider communication bandwidth, but it requires more signal lines. In PCB design, resources are limited, and the signal lines between dual CPLDs are usually limited, making it difficult to implement a wider parallel bus. Especially when the number of pins is limited, the signal line requirements of the parallel bus exceed the actual available resources, resulting in increased design complexity.

[0012] Complexity of synchronization control: The startup, initialization and interconnection of multi-die CPUs have strict timing control requirements, while existing communication methods such as I2C and SPI have limited support for timing control. Existing communication solutions usually do not have dedicated direction control signals, which makes it difficult for signal synchronization and direction switching to meet the strict timing requirements of the CPU, and the timing coordination of dual CPLDs becomes a major difficulty.

[0013] Therefore, the existing technology currently has the following technical problems: 1. The traditional single CPLD architecture is difficult to cover a multi-die CPU with nearly 800 pins. A single CPLD has limited resources and cannot manage all pins and is difficult to meet complex IO function verification requirements; 2. Multi-die CPUs have very strict requirements on signal timing during startup, initialization, and interconnection. There are only 5 GPIOs between two CPLDs for communication, which makes it difficult to meet the timing control of multiple dies inside the CPU. 3. Multi-die CPUs and various system peripherals require multiple power signal support (such as core power, IO power, etc.), and these signals need to be uniformly controlled during startup and operation. Summary of the invention

[0014] In view of the above technical problems in the related art, the present invention proposes a CPU synchronization system and method based on dual CPLD bidirectional control.

[0015] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme: In a first aspect, the present invention provides a CPU synchronization system based on dual CPLD bidirectional control, including a power management signal; the CPU includes a plurality of Dies; the dual CPLD includes a master CPLD and a slave CPLD; the software workflow and state machine design of the master CPLD and the slave CPLD are the same; the pins of each Die are classified according to the functional signal and connected to the CPLD with the closest physical distance; the power management signal is generated by the CPU and the system peripherals; the power management signal is connected to the slave CPLD, and the slave CPLD controls the start and stop of the power management signal; The power management signal includes EN and PWROK; wherein EN is used to control the start and stop of the power management signal from the CPLD, and is sent from the CPLD to the system peripherals. When EN=1, it indicates starting the system peripherals, and when EN=0, it indicates shutting down the system peripherals; PWROK is used to feedback whether the peripheral is started or shut down. It is sent by the system peripheral to the slave CPLD. When PWROK=1, it means that the system peripheral is started. When PWROK=0, it means that the system peripheral is shut down.

[0016] The master CPLD and the slave CPLD are connected via four bidirectional signal lines and one direction control signal line; the four bidirectional signal lines correspond to the bidirectional signal M2S[3:0]; the direction control signal line corresponds to the direction control signal M2S_CTRL; wherein, M2S[3:0] corresponds to the pins N1, N2, N3, and N4 of the CPLD; and M2S_CTRL corresponds to the pin R1 of the CPLD.

[0017] The direction control signal line is used to control the data direction of the four bidirectional signal lines; the four bidirectional signal lines are used to perform data transmission between the two CPLDs according to the data direction determined by the direction control signal line, and the four bidirectional signal lines can be switched to input or output at any time to complete the timing synchronization of the CPU.

[0018] Specifically, the direction control signal line is used to control the data direction of the four bidirectional signal lines: When M2S_CTRL is at a high level, the master CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the master CPLD is the receiver.

[0019] Specifically, when the data direction is determined, the CPLD of the sender loads the data onto the four bidirectional signal lines, and the CPLD of the receiver reads the data. During data transmission, the sender keeps the signal line in output mode, and the receiver switches to input mode.

[0020] Specifically, the direction control signal M2S_CTRL is controlled by the main CPLD.

[0021] Specifically, the functional signals include UART, I2C, SPI, JTAG, SPI, GPIO and FUNC.

[0022] Specifically, the data transmission between the dual CPLDs includes key signals flash_done, Good and En: flash_done signal: It is used to indicate the completion signal of Die reading flash information in the Die initialization stage, and is output by Die to CPLD; when flash_done is equal to 0, it means that the Die Flash has not been read; when flash_done is equal to 1, it means that the Die Flash has been read; In the Die2Die stage of Die, flash_done is also used to indicate whether the Die2Die training is completed, and it must be combined with the good signal of Die. Only when flash_done is 1 and good is 1, it indicates that the Die2Die training of the corresponding Die is completed; when flash_done is 0, it indicates that the Die2Die training is not completed. good: used in conjunction with the flash_done signal to indicate whether the Die2Die training of Die is completed, and is output by Die to CPLD; when good is equal to 0, it indicates that the Die2Die training of Die is not completed; when flash_done is equal to 1 and good is equal to 1, it indicates that the Die2Die training of Die is completed; en: used to indicate the start and stop of Die2Die training, output by CPLD to Die; when en is equal to 0, it indicates that Die2Die training is turned off; when en is equal to 1, it indicates that Die2Die training is started.

[0023] Specifically, the CPU includes Die0, Die1, Die2 and Die3; Die0 and Die1 are connected to the slave CPLD, and Die2 and Die3 are connected to the master CPLD; the direction control signal M2S_CTRL controls the data transmission direction in the four bidirectional data lines; M2S[3:0] represents flash_done and good of the two dies of the master CPLD or the slave CPLD depending on whether M2S_CTRL is equal to 1 or 0.

[0024] Specifically, when M2S_CTR of the slave CPLD is equal to 0, the four bidirectional signal lines are used as outputs, that is, M2S[3:0] represents Die0_flash_done, Die0_good, Die1_flash_done, Die1_good of the slave CPLD in turn. The master CPLD can obtain the information of Die0 and Die1 connected to the slave CPLD through M2S[3:0]. When M2S_CTRL is equal to 1, the slave CPLD uses four bidirectional signal lines as input, that is, M2S[3:0] represents Die2_flash_done, Die2_good, Die3_flash_done, Die3_good of the master CPLD respectively. The slave CPLD can obtain the information of Die2 and Die3 connected to the master CPLD through M2S[3:0].

[0025] The present invention reasonably distributes the high pins of multi-die CPU on two CPLDs through the dual CPLD architecture, avoiding the resource limitation and signal transmission problems caused by the concentration of pins on a single CPLD; divides the signals according to the pin functions and physical areas, optimizes the PCB wiring, and improves the integrity of signal transmission. The dual CPLD structure reduces the pin density on the PCB, ensuring more space for PCB wiring, especially in high-speed signal wiring and power wiring, avoiding the problems of excessive stray signals and crosstalk.

[0026] The dual-CPLD distributed architecture not only better adapts to the CPU pin distribution physically, but also enables each CPLD to independently complete the functional verification of the pins in its area through partition management, ensuring full coverage of the pins, thereby optimizing PCB wiring, reducing routing interference, and improving the effective use of CPLD resources; In addition, the dual CPLDs are located on both sides of the CPU, utilizing PCB layers in different areas to reduce stray interference of cross-area signal lines and improve the flexibility of PCB design and signal quality.

[0027] Furthermore, the present invention manages multiple power signals in one CPLD, avoiding the timing control and signal coordination problems caused by the power signals being dispersed between two CPLDs. Through centralized control, the core power supply, IO power supply, etc. of each CPU Die can maintain consistency and reliability during startup, initialization and operation, avoiding the need for power coordination between dual CPLDs.

[0028] In a second aspect, the present invention provides a CPU synchronization method based on dual CPLD bidirectional control, based on the CPU synchronization system based on dual CPLD bidirectional control described in any one of the first aspects, comprising the following steps: S1. After the mainboard is powered on, both the master CPLD and the slave CPLD are in Idle state, M2S_CTRL is set to 1, the master CPLD resets Die3 and enters Die3_flash_read state, Die3 starts to read the flash, and after the reading is completed, the CPU sets Die3_flash_done to 1; S2. When the main CPLD detects that Die3_flash_done is equal to 1, the main CPLD resets Die2 and enters the Die2_flash_read state. M2S_CTRL is set to 1, and Die2 starts to read the flash. After the reading is completed, the CPU sets Die2_flash_done to 1. S3. When the master CPLD detects that Die2_flash_done is equal to 1, it enters the Die1_flash_read state and M2S_CTRL is set to 0. In steps S1 and S2, when M2S_CTRL is equal to 1, the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through data lines M2S[3] and M2S[1] respectively. When both are equal to 1, the slave CPLD resets Die1 and enters the Die1_flash_read state. S4. When the slave CPLD detects that Die1_flash_done is equal to 1, the slave CPLD resets Die0 to enter the Die0_flash_read state, and Die0 starts to read the flash. After the reading is completed, the CPU sets Die0_flash_done to 1. In S5, steps S3 and S4, when M2S_CTRL is equal to 0, the main CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through data lines M2S[3] and M2S[1] respectively, and when both are equal to 1, enters the Die2die_ready1 state; S6. When in the Die2die_ready1 state, set M2S_CTRL to 1, wait for a preset cycle, and synchronously obtain the values ​​of Die2_flash_done and Die3_flash_done from the CPLD through the data lines M2S[3] and M2S[1] respectively, and enter the Die2die_ready2 state; S7, when in Die2die_ready2 state, the CPU first sets the flash_done of the four Dies to 0. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started for the first time. S8. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, and Die3_good, Die2_good, Die1_good and Die0_good are all 1, Die2Die training ends and enters the Die2die_finish state.

[0029] Specifically, in step S7, when the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, enabling Die2Die training for the first time specifically includes: S71. When the master-slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started, the Die2die_ctl_en_wait state is entered, M2S_CTRL is set to 1, and a preset cycle time is waited. The slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively; S72. After a preset cycle time, the system enters the Die2die_ctl_en state, sets M2S_CTRL to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. At this time, the synchronization of the flash done signals of all dies between the master and slave CPLDs is completed. When the master and slave CPLDs both detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, the Die2Die training enable is turned off and the system enters the Die2Die_pre1 state.

[0030] Specifically, step S8 specifically includes: S81. When in the Die2Die_pre1 state, M2S_CTRL is set to 1, and the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, waits for a preset cycle time, and enters the Die2Die_pre2 state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively; S82. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 0, the Die2Die training enable is turned on for the second time, and the state of Die2die_start1 is entered. M2S_CTRL is set to 1. The slave CPLD obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively. After waiting for a preset cycle time, the state of Die2Die_start2 is entered. M2S_CTRL is set to 0. The master CPLD obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. S83, when both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 1, the Die2Die training enable is turned off for the second time and the state of Die2die_done1 is entered; S84, when in the Die2die_done1 state, M2S_CTRL is set to 1, and the values ​​of Die2_flash_done and Die3_flash_done are synchronously obtained from the CPLD through the data lines M2S[3] and M2S[1], and the values ​​of Die2_good and Die3_good are synchronously obtained through the data lines M2S[2] and M2S[0], respectively. After waiting for one cycle, it enters the Die2die_done2 ​​state; S85. When in the Die2die_done2 ​​state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1], and synchronously obtains the values ​​of Die0_good and Die0_good through the data lines M2S[2] and M2S[0]. When both the master and slave CPLDs detect that Die0_good, Die1_good, Die2_good and Die3_good are all 1 and Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, they enter the Die2die_finish state and the Die2die training is completed. Otherwise, they keep waiting, indicating that the training is not completed.

[0031] In the dual CPLD architecture, the present invention realizes efficient signal synchronization between CPLDs through 4 bidirectional signal lines and 1 direction control signal. The 4-line bidirectional communication allows two CPLDs to flexibly switch signal directions, ensuring that each CPLD can read or send the other party's signal when needed; the direction control signal is used for timing control to meet strict timing requirements during the startup and initialization of multi-die CPUs. This method ensures accurate timing control and signal synchronization between dual CPLDs under limited signal resources; Furthermore, during the CPU multi-die startup and initialization process, the state machine controls the switching of direction signals to accurately manage the signal timing synchronization between CPLDs. This timing synchronization control strategy ensures signal consistency between multiple dies and avoids signal delay and loss problems in dual CPLD communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 Schematic diagram of a CPU synchronization system based on dual CPLD bidirectional control provided according to an embodiment of the present invention; Figure 2 It is a schematic diagram of the connection between DIE, CPLD and Flash provided in an embodiment of the present invention; Figure 3 It is a schematic diagram of a hardware circuit and key signals based on a bidirectional control part of a master-slave CPLD provided in an embodiment of the present invention; Figure 4 It is a schematic diagram of a CPU synchronization method based on dual CPLD bidirectional control according to an embodiment of the present invention; Figure 5 The present invention provides a schematic diagram of a state machine based on dual CPLD bidirectional control. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0035] In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0036] In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0037] Embodiment 1

[0038] refer to Figure 1 This embodiment provides a CPU synchronization system based on dual CPLD bidirectional control, including a power management signal; the CPU includes multiple Dies; the dual CPLD includes a master CPLD and a slave CPLD; the pins of each Die are classified according to the functional signal and connected to the CPLD closest to it physically; the power management signal is generated by the CPU and the power module; the power management signal is connected to the slave CPLD; The power management signals include EN and PWROK; Wherein, EN is used to control the start and stop of the power management signal from the CPLD, and is sent from the CPLD to the power module. When EN=1, it indicates starting the power module, and when EN=0, it indicates shutting down the power module; PWROK is used to feedback whether the power module is normal after startup. It is sent by the power module to the slave CPLD. When PWROK=1, it means that the power module is working normally. When PWROK=0, it means that the power module is not working properly.

[0039] Based on the dual CPLD design requirement background, this embodiment centrally manages all power management signals of the CPU and power module (all core power supplies, IO power supplies) in the slave CPLD to ensure that the timing of the power signals is controllable.

[0040] The functional signals include UART, I2C, SPI, JTAG, SPI, GPIO and FUNC; The dual CPLD architecture design of this application allocates more than 700 pins that need to be verified for multi-die CPUs to two CPLDs for management. According to the physical distribution and functional requirements of the CPU pins, the pins of different die areas are reasonably allocated to the two CPLDs; through distributed management, the same functional signals of each die (such as UART, I2C, SPI, JTAG, etc.) are concentrated on the same CPLD for verification as much as possible.

[0041] In this embodiment, the CPU includes Die0, Die1, Die2, and Die3.

[0042] This embodiment provides a connection method between a CPU including 4 dies and dual CPLDs; For example, if Die0 and Die1 of the CPU are close to the slave CPLD, all UART (usually multiple) interfaces of Die0 and Die1 are connected to the slave CPLD, and similarly, all I2C interfaces are connected to the slave CPLD. On the contrary, all UART, I2C and other interfaces of Die2 and Die3 are connected to the master CPLD.

[0043] This design allows each CPLD to be physically close to the pin area it manages, reducing cross-area wiring and improving signal transmission integrity. Distributed IO management effectively improves the utilization of CPLD resources, avoids resource bottlenecks in the number of pins and function management of a single CPLD, and ensures that the verification requirements of each pin are met.

[0044] The system further comprises a Flash, in which BIOS information is stored, and the Die can read the BIOS information from the Flash.

[0045] refer to Figure 2,Flash is external and independent during die initialization. Because the configuration files are the same, the circuit can share one Flash through MUX (multiplexer) and read it in different time periods. CPLD is used to determine whether the Flash is completed and switch the channel for reading Flash; The multiplexer described in this embodiment is a 4-to-1 multiplexer; x0 of the multiplexer corresponds to Die0 flash channel, x1 corresponds to Die1 flash channel, x2 corresponds to Die2 flash channel, x3 corresponds to Die3 flash channel, x corresponds to the common flash channel, and the switch of the selector channel is controlled by SEL1 and SEL0.

[0046] The channel control relationship is: when SEL[1:0]=11, the switch channel between X3 and X is turned on, that is, the hardware path is the channel for Die3 to read Flash; when SEL[1:0]=10, the switch channel between X2 and X is turned on, that is, the hardware path is the channel for Die2 to read Flash; when SEL[1:0]=01, the switch channel between X1 and X is turned on, that is, the hardware path is the channel for Die1 to read Flash; when SEL[1:0]=00, the switch channel between X0 and X is turned on, that is, the hardware path is the channel for Die0 to read Flash.

[0047] In this embodiment, the Flash configurations of the four Dies are the same. The circuit shares one Flash through MUX, and there is a priority reading in the timing. After power-on, Die3 is entered by default to read the Flash status first, and the main CPLD sets SEL[1:0]=11. Then Die2 reads the Flash status, and the main CPLD sets SEL[1:0]=10. Then Die1 reads the Flash status, and the main CPLD sets SEL[1:0]=01. Finally, Die0 reads the Flash status, and the main CPLD sets SEL[1:0]=00. The four Dies read the Flash in sequence.

[0048] In another possible implementation, each Die may correspond to one Flash.

[0049] refer to Figure 3 , the master CPLD and the slave CPLD are connected via 4 bidirectional signal lines and 1 direction control signal line; the 4 bidirectional signal lines correspond to the bidirectional signal M2S[3:0]; the direction control signal line corresponds to the direction control signal M2S_CTRL; wherein, M2S[3:0] corresponds to the pins N1, N2, N3, N4 of the CPLD; M2S_CTRL corresponds to the pin R1 of the CPLD; The direction control signal line is used to control the direction of the four bidirectional signal lines; Specifically, when M2S_CTRL is at a high level, the master CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the master CPLD is the receiver; Specifically, the M2S_CTRL is a high level, which may be 1; the M2S_CTRL is a low level, which may be 0; The M2S_CTRL signal is controlled by the master CPLD, and the slave CPLD is output only when M2S_CTRL=0; When the R1 pin of the main CPLD is at a high level, M2S_CTRL is at a high level; that is, when the R1 pin of the main CPLD is at a low level, M2S_CTRL is at a low level; the level of the R1 pin is controlled by the main CPLD, thereby controlling the high and low levels of M2S_CTRL; The four bidirectional signal lines are used to determine the data direction according to the value of M2S_CTRL to perform data transmission between the two CPLDs, and the four bidirectional signal lines can be switched to input or output at any time; Specifically, when the direction control signal determines the data direction, the sender's CPLD loads the data onto four bidirectional signal lines, and the receiver's CPLD reads the data. During data transmission, the sender keeps the signal line in output mode, and the receiver switches to input mode.

[0050] Specifically, the communication operation process: 1) Direction switching: According to the timing requirements, the M2S_CTRL signal is controlled by the state machine of the master CPLD, and the slave CPLD is used as an output only when M2S_CTRL=0.

[0051] For example, when a die of the CPU completes startup and needs to notify the other CPLD, the main CPLD state machine switches the M2S_CTRL signal to the corresponding direction to ensure correct signal transmission.

[0052] 2) Data transmission: When the direction control signal determines the data direction, the sender's CPLD loads the data onto the four bidirectional signal lines, and the receiver's CPLD reads the data. During data transmission, the sender keeps the signal line in output mode, and the receiver switches to input mode.

[0053] In the existing solution, the master and slave CPLDs complete the startup and interconnection communication between Dies, which normally requires 8 direct signals; this embodiment designs a communication mechanism with 4 bidirectional signal lines (corresponding to signal M2S[3:0]) and 1 direction control signal line (corresponding to signal M2S_CTRL). Through these 5 signal lines, the two CPLDs can flexibly perform bidirectional data transmission as needed to meet the timing synchronization requirements of multiple Die CPUs during startup, initialization and interconnection.

[0054] Direction control signal (M2S_CTRL): This signal is used to control the direction of the four bidirectional signal lines. M2S_CTRL is controlled by the master CPLD. Specifically, when M2S_CTRL is high, the master CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is low, the slave CPLD is the sender and the master CPLD is the receiver.

[0055] In this embodiment, the key signals between Die and CPLD include flash_done, good and en; among which: flash_done signal: It is used to indicate the completion signal of Die reading flash information in the Die initialization stage, and is output by Die to CPLD; when flash_done is equal to 0, it means that the Die Flash has not been read; when flash_done is equal to 1, it means that the Die Flash has been read; In the Die2Die stage of Die, flash_done is also used to indicate whether the Die2Die training is completed, and it must be combined with the good signal of Die. Only when flash_done is 1 and good is 1, it indicates that the Die2Die training of the corresponding Die is completed; when flash_done is 0, it indicates that the Die2Die training is not completed. good: used in conjunction with the flash_done signal to indicate whether the Die2Die training of Die is completed, and is output by Die to CPLD; when good is equal to 0, it indicates that the Die2Die training of Die is not completed; when flash_done is equal to 1 and good is equal to 1, it indicates that the Die2Die training of Die is completed; The values ​​of flash_done and good are assigned by Die according to its own situation, and CPLD only reads them; en: used to indicate the start and stop of Die2Die training, output by CPLD to Die; when en is equal to 0, it indicates that Die2Die training is turned off; when en is equal to 1, it indicates that Die2Die training is started; In addition, other key signals can be expanded between Die and CPLD as required; For the sake of easy distinction, this embodiment uses the naming method of "Die name_key signal" to facilitate distinguishing which Die the key signal belongs to; for example: The flash_done signal of Die3 is Die3_flash_done; the flash_done signal of Die2 is Die2_flash_done; The good signal of Die3 is Die3_good; the good signal of Die2 is Die2_good; The en signal of Die3 is Die3_en; the en signal of Die2 is Die2_en; The naming of key signals between Die1, Die0 and CPLD is similar. If there are more Dies, the above naming rules can also be used.

[0056] Signal line configuration: 4 bidirectional signal lines are used for data transmission. Each signal line can be switched to input or output at any time, and dynamic data exchange between the two CPLDs is realized according to the instruction of the direction control signal line M2S_CTRL.

[0057] In this embodiment, Die0 and Die1 of the CPU are connected to the slave CPLD, and Die2 and Die3 are connected to the master CPLD. The software workflow and state machine design of the master CPLD and the slave CPLD are basically the same, and the direction of data transmission in the four bidirectional data lines is controlled by the direction control signal M2S_CTRL; Specifically, the bidirectional signal M2S[3:0] represents the flash_done and good of two Dies connected to the master CPLD or the slave CPLD when the direction control signal M2S_CTRL is equal to 1 or 0.

[0058] Specifically, M2S_CTRL is controlled by the state machine of the master CPLD. When M2S_CTR is equal to 0, the slave CPLD uses four bidirectional signal lines as outputs, that is, M2S[3:0] represents Die0_flash_done, Die0_good, Die1_flash_done, and Die1_good of the slave CPLD, that is, when M2S_CTRL is equal to 0, M2S[3] represents Die0_flash_done, M2S[2] represents Die0_good, M2S[1] represents Die1_flash_done, and M2S[0] represents Die1_good. The master CPLD can obtain the information of Die0 and Die1 connected to the slave CPLD through M2S[3:0]. When M2S_CTRL is equal to 1, the slave CPLD uses four bidirectional signal lines as inputs, that is, M2S[3:0] represents Die2_flash_done, Die2_good, Die3_flash_done, and Die3_good of the master CPLD, that is, when M2S_CTRL is equal to 1, M2S[3] represents Die2_flash_done, M2S[2] represents Die2_good, M2S[1] represents Die3_flash_done, and M2S[0] represents Die3_good. The slave CPLD can obtain the information of Die2 and Die3 connected to the master CPLD through M2S[3:0].

[0059] In this embodiment, in a dual CPLD architecture, efficient signal synchronization between CPLDs is achieved through four bidirectional signal lines and one direction control signal. The four-wire bidirectional communication allows the two CPLDs to flexibly switch signal directions, ensuring that each CPLD can read or send the other party's signal when needed; the direction control signal is used for timing control to meet strict timing requirements during the startup and initialization of multi-die CPUs.

[0060] Based on the dual CPLD design requirement background, this embodiment centrally manages all power management signals of the CPU and system peripherals in the slave CPLD to ensure that the timing of the power signal is controllable.

[0061] The slave CPLD is responsible for controlling the start and shut down of all core power, IO power and other related signals. All power control signals and the power OK indication signal PWROK are implemented in a single CPLD through the power signal control logic, avoiding the need to transmit power signals between dual CPLDs, effectively reducing power timing delays and inconsistencies, and ensuring reliable startup and operation of the CPU.

[0062] The power control logic is designed according to the system power timing requirements. For example, a CPU contains multiple power supplies, including core voltage (VDD), IO voltage (VDDIO), PCIe voltage (VDDH), memory voltage (VDDQ), etc. During power-on, these power supplies have a certain sequence, i.e., timing requirements. CPLD controls the enablement of these power supplies in sequence according to the timing relationship to achieve control.

[0063] The traditional I2C communication rate is low and it is difficult to meet the CPU's high-speed signal transmission requirements; while SPI has a higher speed, it lacks flexible direction control and cannot perform bidirectional timing synchronization switching between dual CPLDs. In addition, although the parallel bus solution has a high bandwidth, it requires large PCB wiring resources, increasing complexity and design costs.

[0064] This embodiment uses a dual CPLD architecture to reasonably distribute the high pins of multi-die CPUs on two CPLDs, avoiding resource limitations and signal transmission problems caused by the concentration of pins on a single CPLD; divides signals according to pin functions and physical areas, optimizes PCB wiring, and improves the integrity of signal transmission. The dual CPLD structure reduces the pin density on the PCB, ensuring more space for PCB wiring, especially in high-speed signal wiring and power wiring, avoiding problems caused by excessive stray signals and crosstalk.

[0065] The dual-CPLD distributed architecture not only better adapts to the CPU pin distribution physically, but also enables each CPLD to independently complete the functional verification of the pins in its area through partition management, ensuring full coverage of the pins, thereby optimizing PCB wiring, reducing routing interference, and improving the effective use of CPLD resources; In addition, the dual CPLDs are located on both sides of the CPU, utilizing PCB layers in different areas to reduce stray interference of cross-area signal lines and improve the flexibility of PCB design and signal quality.

[0066] Furthermore, this embodiment manages multiple power signals in one CPLD, avoiding the timing control and signal coordination problems caused by the power signals being dispersed between two CPLDs. Through centralized control, the core power supply, IO power supply, etc. of each CPU Die can maintain consistency and reliability during startup, initialization and operation, avoiding the need for power coordination between dual CPLDs.

[0067] Embodiment 2

[0068] refer to Figure 4 This embodiment provides a CPU synchronization method based on dual CPLD bidirectional control, based on the CPU synchronization system based on dual CPLD bidirectional control described in Embodiment 1, wherein the CPU includes Die0, Die1, Die2 and Die3; and includes the following steps: S1. After the mainboard is powered on, both the master CPLD and the slave CPLD are in Idle state, M2S_CTRL is set to 1, the master CPLD resets Die3 and enters Die3_flash_read state, Die3 starts to read the flash, and after the reading is completed, the CPU sets Die3_flash_done to 1; S2. When the main CPLD detects that Die3_flash_done is equal to 1, the main CPLD resets Die2 and enters the Die2_flash_read state. M2S_CTRL is set to 1, and Die2 starts to read the flash. After the reading is completed, the CPU sets Die2_flash_done to 1. S3. When the master CPLD detects that Die2_flash_done is equal to 1, it enters the Die1_flash_read state and M2S_CTRL is set to 0. In steps S1 and S2, when M2S_CTRL is equal to 1, the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through data lines M2S[3] and M2S[1] respectively. When both are equal to 1, the slave CPLD resets Die1 and enters the Die1_flash_read state. S4. When the slave CPLD detects that Die1_flash_done is equal to 1, the slave CPLD resets Die0 to enter the Die0_flash_read state, and Die0 starts to read the flash. After the reading is completed, the CPU sets Die0_flash_done to 1. In S5, steps S3 and S4, when M2S_CTRL is equal to 0, the main CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through data lines M2S[3] and M2S[1] respectively, and when both are equal to 1, enters the Die2die_ready1 state; S6. When in the Die2die_ready1 state, set M2S_CTRL to 1, wait for a preset cycle, and synchronously obtain the values ​​of Die2_flash_done and Die3_flash_done from the CPLD through the data lines M2S[3] and M2S[1] respectively, and enter the Die2die_ready2 state; at this time, the synchronization of the flash done signals of all dies between the master and slave CPLDs and the initialization of all dies are completed; In this embodiment, flash_done of Die is reused, and its meanings in different steps are different. In steps S1-S6, flash_done is used to indicate the flash reading status corresponding to Die; when flash_done of Die is 1, it indicates that the flash reading of the corresponding Die is completed, and when flash_done of Die is 0, it indicates that the flash reading of the corresponding Die is not completed; In steps S7-S8, flash_done is used to represent some parameters of the Die2Die training status corresponding to the Die; only when the flash_done of the Die is 1 and the good is 1, it indicates that the Die2Die training corresponding to the corresponding Die is completed. The Die2Die training is the behavior of the CPU, and the CPLD only monitors these two signals.

[0069] If Die2Die training is not successful, flash_done will not be 1, and the CPLD will remain in a waiting state. The CPU will try to train multiple times, and the CPLD only monitors these signals.

[0070] S7. After all Die initialization is completed, the CPU first sets the flash_done of the four Dies to 0. When the master-slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started for the first time. It can be understood that the master-slave CPLD is an abbreviation of a master CPLD and a slave CPLD; Specifically, when the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the first start of Die2Die training specifically includes: S71. When the master-slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started, the Die2die_ctl_en_wait state is entered, M2S_CTRL is set to 1, and a preset cycle time is waited. The slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively; S72. After a preset cycle time, the system enters the Die2die_ctl_en state, sets M2S_CTRL to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. At this time, the synchronization of the flash done signals of all dies between the master and slave CPLDs is completed. When the master and slave CPLDs both detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, the Die2Die training enable is turned off and the system enters the Die2Die_pre1 state.

[0071] The preset cycle time is determined according to specific needs; in this embodiment, the preset cycle time is 20ns; S8. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, and Die3_good, Die2_good, Die1_good and Die0_good are all 1, Die2Die training ends and enters the Die2die_finish state.

[0072] Step S8 specifically includes: After turning off the Die2Die training enable in steps S81 and S72, the system enters Die2Die_pre1, M2S_CTRL is set to 1, and the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1], respectively, and waits for a preset cycle time, and enters the Die2Die_pre2 state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1], respectively; S82. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 0, the Die2Die training enable is turned on for the second time, and the state of Die2die_start1 is entered. M2S_CTRL is set to 1. The slave CPLD obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively. After waiting for a preset cycle time, the state of Die2Die_start2 is entered. M2S_CTRL is set to 0. The master CPLD obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. S83, when both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 1, the Die2Die training enable is turned off for the second time and the state of Die2die_done1 is entered; Repeating turning on and off the Die2Die training enable twice is the CPU behavior, which is mainly used for 2 instruction synchronization to ensure stability; S84, when in the Die2die_done1 state, M2S_CTRL is set to 1, and the values ​​of Die2_flash_done and Die3_flash_done are synchronously obtained from the CPLD through the data lines M2S[3] and M2S[1], and the values ​​of Die2_good and Die3_good are synchronously obtained through the data lines M2S[2] and M2S[0], respectively. After waiting for one cycle, it enters the Die2die_done2 ​​state; S85. When in the Die2die_done2 ​​state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1], and synchronously obtains the values ​​of Die0_good and Die0_good through the data lines M2S[2] and M2S[0]. When both the master and slave CPLDs detect that Die0_good, Die1_good, Die2_good and Die3_good are all 1 and Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, they enter the Die2die_finish state and the Die2die training is completed. Otherwise, they keep waiting, indicating that the training is not completed.

[0073] The CPU synchronization of this embodiment can be regarded as two stages. The first stage: completing the initialization of the four dies, i.e., steps S1-S6; the second stage: completing the training between Die2Die, i.e., steps S7-S8; The two stages of Die initialization and Die2Die training are independent. After all four dies are initialized, the CPU will set their flash_done to 0 and start Die2Die training.

[0074] After the first stage of flash reading is completed, the second stage Die2Die training phase begins. The entry condition is that the flash_done of the four dies are all 0. After the Die2Die enable en is turned on, the CPLD will detect the flash_done signals of the four dies again. If they are all 1, it means that the CPU has received the Die2Die training command. The Die2Die enable en can be turned off to enter the Die2die_done state. At this time, the CPLD only needs to detect whether the good signal of the four dies is 1. If it is 1, it means that the training is completed and the whole process is over. If it is not 1, continue to wait.

[0075] After the motherboard is powered on, the main CPLD resets Die3 by default, enters the Die3 flash reading state, and M2S_CTRL is equal to 1, Die3 starts to read flash. The main CPLD waits for Die3_flash_done to be 1. If it is 1, Die2 is reset to enter the Die2 flash reading state and M2S_CTRL is equal to 1. Die2 starts to read flash, and the main CPLD waits for Die2_flash_done to be 1. The first two states of the slave CPLD are to determine whether Die3 and Die2 have completed flash reading. Because M2S_CTRL is equal to 1, M2S[3:0] is used as the input of the slave CPLD, so the slave CPLD only needs to determine the values ​​of M2S[3:0]. Back to the main CPLD state machine, if it is 1, the main CPLD similarly enters the state of determining whether Die1 and Die0 have completed flash reading and M2S_CTRL is equal to 0, and M2S[3:0] is used as the input judgment value of the main CPLD.

[0076] When the subsequent state machine needs to determine the flash_done and good of the four dies at the same time, it only needs to add a level of M2S_CTRL direction control state in the main CPLD to synchronize the values ​​of M2S[3:0] on both sides. The above is the coordination mechanism principle of the five signal lines.

[0077] refer to Figure 5 , this embodiment provides a bidirectional control part state machine of the main CPLD; Idle: indicates idle; flash_read: indicates that Die reads the flash status; flash_done: In the initialization phase of Die, it is used to indicate whether the Die has completed reading the flash. When preparing to start the Die2Die training phase, the flash_done of the four Dies is 0 at the same time to start the Die2Die training, and is 1 at the same time to close the Die2Die training. There are two identical operations for synchronization confirmation. In the Die2Die training process, in addition to good, this signal is also used to indicate whether the Die2Die training of a certain Die is successful. good: In the Die2Die training phase, this signal is used to indicate whether the Die2Die training of a certain Die is completed, and flash_done also needs to be set to 1; When flash_done is equal to 1, it means that the Die has completed reading the flash or one of the conditions of the Die2Die training has been completed; When flash_done is equal to 0, it means that the Die flash reading is not completed or one of the Die2Die training flags is not completed; The CPU can also be considered as Die telling the CPLD whether the falsh reading is completed through the flash_done signal; For the sake of easy distinction, this embodiment uses the naming method of "Die name_state machine type" to facilitate identification of which Die the state machine type belongs to; For example: Die3_flash_read: indicates the status of Die3 reading Flash; when Die3 finishes reading Flash, Die3_flash_done is set to 1; when Die3 does not finish reading Flash, Die3_flash_done is set to 0; Die2_flash_read: indicates the status of Die2 reading flash; when Die2 finishes reading flash, Die2_flash_done is set to 1; when Die2 does not finish reading flash, Die2_flash_done is set to 0; Die1_flash_read: indicates the status of Die1 reading flash; when Die1 finishes reading flash, Die1_flash_done is set to 1; when Die1 does not finish reading flash, Die1_flash_done is set to 0; Die0_flash_read: indicates the status of Die0 reading flash; when Die0 finishes reading flash, Die0_flash_done is set to 1; when Die0 does not finish reading flash, Die0_flash_done is set to 0; Die2die_ready1: Set M2S_CTRL = 1, wait for one cycle, and get the flash_done of Die3 and Die2 from CPLD; Die2die_ready2: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 0. If they are 0, the Die2Die enable condition is turned on; Die2die_ctl_en_wait: Set M2S_CTRL = 1, wait for one cycle, and get the flash_done of Die3 and Die2 from CPLD; Die2die_ctl_en: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 1. If they are 1, turn off the Die2Die enable condition; Die2die_pre1: Set M2S_CTRL = 1, which means waiting for one cycle to obtain the flash_done of Die3 and Die2 from the CPLD; repeat the Die2Die enabling process once. This is the behavior of the CPU and is used for two handshake synchronization.

[0078] Die2die_pre2: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 0. If they are 0, the Die2Die enabling condition is turned on; this is the same as the Die2die_ready2 state function, which is used for two-way handshake synchronization to ensure stability; Die2die_start1: Set M2S_CTRL = 1, wait for one cycle, and get the flash_done of Die3 and Die2 from CPLD; Die2die_start2: Set M2S_CTRL = 0, indicating that the master and slave CPLDs have synchronously obtained the flash done signals of Die3, Die2, Die1, and Die0. And start waiting and monitoring whether the flash done signals of Die3, Die2, Die1, and Die0 are 1. If they are 1, turn off the Die2Die enable condition; Because two CPLDs are communicating, the slave CPLD determines the value of M2S_CTRL in this state. For example, in the previous cycle, it outputs the signals of die1 and die0 to the master CPLD, and in the next cycle, it becomes the input to read the signals of die3 and die2 transmitted from the master CPLD. Because M2S_CTRL is controlled by the master CPLD, if the slave CPLD determines that M2S_CTRL has changed, it enters the next state.

[0079] Die2die_done1: Set M2S_CTRL = 0, which means waiting for one cycle, and the main CPLD obtains the flash_done and training good signals of Die1 and Die0; Die2die_done2: Set M2S_CTRL = 1. If the master and slave CPLDs have synchronously obtained the flash_done and training good signals of Die3, Die2, Die1, and Die0, and the results are all 1, the training is completed. Die2die_finish: indicates that Die2Die training is completed.

[0080] In this embodiment, in a dual CPLD architecture, efficient signal synchronization between CPLDs is achieved through 4 bidirectional signal lines and 1 direction control signal. 4-wire bidirectional communication allows two CPLDs to flexibly switch signal directions, ensuring that each CPLD can read or send the other party's signal when needed; the direction control signal is used for timing control to meet strict timing requirements during the startup and initialization of multi-die CPUs. This method ensures accurate timing control and signal synchronization between dual CPLDs under limited signal resources; Furthermore, during the CPU multi-die startup and initialization process, the state machine controls the switching of direction signals to accurately manage the signal timing synchronization between CPLDs. This timing synchronization control strategy ensures signal consistency between multiple dies and avoids signal delay and loss problems in dual CPLD communication.

[0081] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods provided above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components may be implemented as a microprocessor, such as a central processing unit, a digital signal processor, or software executed by a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A CPU synchronization system based on dual CPLD bidirectional control, characterized in that: Including power management signal; the CPU includes multiple Dies; the dual CPLD includes a master CPLD and a slave CPLD; the software workflow and state machine design of the master CPLD and the slave CPLD are the same; the pins of each Die are classified according to the functional signal and connected to the CPLD with the closest physical distance; the power management signal is generated by the CPU and system peripherals; the power management signal is connected to the slave CPLD, and the slave CPLD controls the start and stop of the power management signal; The master CPLD and the slave CPLD are connected via four bidirectional signal lines and one direction control signal line; the four bidirectional signal lines correspond to the bidirectional signal M2S[3:0]; the direction control signal line corresponds to the direction control signal M2S_CTRL; The direction control signal line is used to control the data direction of the four bidirectional signal lines; the four bidirectional signal lines are used to perform data transmission between the two CPLDs according to the data direction determined by the direction control signal line, and the four bidirectional signal lines can be switched to input or output at any time to complete the timing synchronization of the CPU.

2. The CPU synchronization system based on dual CPLD bidirectional control according to claim 1 is characterized in that: The direction control signal line is used to control the data direction of the four bidirectional signal lines: When M2S_CTRL is at a high level, the master CPLD is the sender and the slave CPLD is the receiver; when M2S_CTRL is at a low level, the slave CPLD is the sender and the master CPLD is the receiver.

3. The CPU synchronization system based on dual CPLD bidirectional control according to claim 2 is characterized in that: When the data direction is determined, the CPLD of the sender loads the data onto the four bidirectional signal lines, and the CPLD of the receiver reads the data. During data transmission, the sender keeps the signal line in output mode, and the receiver switches to input mode.

4. The CPU synchronization system based on dual CPLD bidirectional control according to claim 3 is characterized in that: The direction control signal M2S_CTRL is controlled by the main CPLD.

5. The CPU synchronization system based on dual CPLD bidirectional control according to claim 3 is characterized in that: The data transmission between the dual CPLDs includes key signals flash_done, Good and En: flash_done signal: used to indicate the completion signal of Die reading flash information during Die initialization phase, and output by Die to CPLD; When flash_done is equal to 0, it means that the Die Flash has not been read; when flash_done is equal to 1, it means that the Die Flash has been read; In the Die2Die stage of Die, flash_done is also used to indicate whether the Die2Die training is completed, and it must be combined with the good signal of Die. Only when flash_done is 1 and good is 1, it indicates that the Die2Die training of the corresponding Die is completed; when flash_done is 0, it indicates that the Die2Die training is not completed. good: used in conjunction with the flash_done signal to indicate whether the Die2Die training of Die is completed, and is output by Die to CPLD; when good is equal to 0, it indicates that the Die2Die training of Die is not completed; when flash_done is equal to 1 and good is equal to 1, it indicates that the Die2Die training of Die is completed; en: used to indicate the start and stop of Die2Die training, output by CPLD to Die; when en is equal to 0, it indicates that Die2Die training is turned off; when en is equal to 1, it indicates that Die2Die training is started.

6. The CPU synchronization system based on dual CPLD bidirectional control according to claim 5 is characterized in that: The CPU includes Die0, Die1, Die2 and Die3; Die0 and Die1 are connected to the slave CPLD, and Die2 and Die3 are connected to the master CPLD; the direction control signal M2S_CTRL controls the data transmission direction in the four bidirectional data lines; M2S[3:0] represents the flash_done and good of the two dies of the master CPLD or the slave CPLD according to whether M2S_CTRL is equal to 1 or 0.

7. The CPU synchronization system based on dual CPLD bidirectional control according to claim 6 is characterized in that: When M2S_CTR of the slave CPLD is equal to 0, the four bidirectional signal lines are used as outputs, that is, M2S[3:0] represents Die0_flash_done, Die0_good, Die1_flash_done, Die1_good of the slave CPLD in turn. The master CPLD can obtain the information of Die0 and Die1 connected to the slave CPLD through M2S[3:0]. When M2S_CTRL is equal to 1, the slave CPLD uses four bidirectional signal lines as input, that is, M2S[3:0] represents Die2_flash_done, Die2_good, Die3_flash_done, Die3_good of the master CPLD respectively. The slave CPLD can obtain the information of Die2 and Die3 connected to the master CPLD through M2S[3:0].

8. A CPU synchronization method based on dual CPLD bidirectional control, based on the CPU synchronization system based on dual CPLD bidirectional control according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. After the mainboard is powered on, both the master CPLD and the slave CPLD are in Idle state, M2S_CTRL is set to 1, the master CPLD resets Die3 and enters Die3_flash_read state, Die3 starts to read the flash, and after the reading is completed, the CPU sets Die3_flash_done to 1; S2. When the main CPLD detects that Die3_flash_done is equal to 1, the main CPLD resets Die2 and enters the Die2_flash_read state. M2S_CTRL is set to 1, and Die2 starts to read the flash. After the reading is completed, the CPU sets Die2_flash_done to 1. S3. When the master CPLD detects that Die2_flash_done is equal to 1, it enters the Die1_flash_read state and M2S_CTRL is set to 0. In steps S1 and S2, when M2S_CTRL is equal to 1, the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through data lines M2S[3] and M2S[1] respectively. When both are equal to 1, the slave CPLD resets Die1 and enters the Die1_flash_read state. S4. When the slave CPLD detects that Die1_flash_done is equal to 1, the slave CPLD resets Die0 to enter the Die0_flash_read state, and Die0 starts to read the flash. After the reading is completed, the CPU sets Die0_flash_done to 1. In S5, steps S3 and S4, when M2S_CTRL is equal to 0, the main CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through data lines M2S[3] and M2S[1] respectively, and when both are equal to 1, enters the Die2die_ready1 state; S6. When in the Die2die_ready1 state, set M2S_CTRL to 1, wait for a preset cycle, and synchronously obtain the values ​​of Die2_flash_done and Die3_flash_done from the CPLD through the data lines M2S[3] and M2S[1] respectively, and enter the Die2die_ready2 state; S7, when in Die2die_ready2 state, the CPU first sets the flash_done of the four Dies to 0. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started for the first time. S8. When the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, and Die3_good, Die2_good, Die1_good and Die0_good are all 1, Die2Die training ends and enters the Die2die_finish state.

9. The CPU synchronization method based on dual CPLD bidirectional control according to claim 8, characterized in that: In step S7, when the master and slave CPLD detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the first opening of Die2Die training enable specifically includes: S71. When the master-slave CPLD detects that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 0, the Die2Die training is started, the Die2die_ctl_en_wait state is entered, M2S_CTRL is set to 1, and a preset cycle time is waited. The slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively; S72. After a preset cycle time, the system enters the Die2die_ctl_en state, sets M2S_CTRL to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. At this time, the synchronization of the flash done signals of all dies between the master and slave CPLDs is completed. When the master and slave CPLDs both detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, the Die2Die training enable is turned off and the system enters the Die2Die_pre1 state.

10. The CPU synchronization method based on dual CPLD bidirectional control according to claim 8, characterized in that: Step S8 specifically includes: S81. When in the Die2Die_pre1 state, M2S_CTRL is set to 1, and the slave CPLD synchronously obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively, waits for a preset cycle time, and enters the Die2Die_pre2 state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively; S82. When both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 0, the Die2Die training enable is turned on for the second time, and the state of Die2die_start1 is entered. M2S_CTRL is set to 1. The slave CPLD obtains the values ​​of Die2_flash_done and Die3_flash_done through the data lines M2S[3] and M2S[1] respectively. After waiting for a preset cycle time, the state of Die2Die_start2 is entered. M2S_CTRL is set to 0. The master CPLD obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1] respectively. S83, when both the master and slave CPLDs detect that Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are 1, the Die2Die training enable is turned off for the second time and the state of Die2die_done1 is entered; S84, when in the Die2die_done1 state, M2S_CTRL is set to 1, and the values ​​of Die2_flash_done and Die3_flash_done are synchronously obtained from the CPLD through the data lines M2S[3] and M2S[1], and the values ​​of Die2_good and Die3_good are synchronously obtained through the data lines M2S[2] and M2S[0], respectively. After waiting for one cycle, it enters the Die2die_done2 ​​state; S85. When in the Die2die_done2 ​​state, M2S_CTRL is set to 0, and the master CPLD synchronously obtains the values ​​of Die0_flash_done and Die1_flash_done through the data lines M2S[3] and M2S[1], and synchronously obtains the values ​​of Die0_good and Die0_good through the data lines M2S[2] and M2S[0]. When both the master and slave CPLDs detect that Die0_good, Die1_good, Die2_good and Die3_good are all 1 and Die0_flash_done, Die1_flash_done, Die2_flash_done and Die3_flash_done are all 1, they enter the Die2die_finish state and the Die2die training is completed. Otherwise, they keep waiting, indicating that the training is not completed.

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