Low power consumption control circuit, chip, microcontroller and low power consumption control method

Abstract

The present invention discloses a low-power control circuit, a chip, a microcontroller and a low-power control method, wherein the low-power control circuit is applied to a chip, the chip includes a power-off module, and the low-power control circuit includes: a controllable switch module, the first end of the controllable switch module is suitable for connecting to a power supply, and the second end of the controllable switch module is suitable for connecting to the power supply end of the power-off module; a discharge module, the first end of the discharge module is connected to the power supply end of the power-off module, and the second end of the discharge module is grounded; a power control module is configured to respond to a sleep instruction, and when the controllable switch module is disconnected, the discharge module is controlled to discharge the residual charge of the power supply end of the power-off module. When the power-off module is powered off, the circuit discharges the residual charge of the power supply end of the power-off module through the discharge module, and quickly discharges the suspended power supply charge of the power-off module to the ground, thereby reducing the static power consumption of the chip.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a low-power control circuit, a chip, a microcontroller and a low-power control method. Background Art

[0002] In MCU (Microcontroller Unit) applications, low power consumption mode is usually considered, that is, the MCU enters sleep mode when it is not busy, and when the wake-up signal arrives, the MCU will wake up from sleep mode and enter normal working mode, thereby reducing average power consumption. Power gating technology is one of the common ways to reduce power consumption, that is, cut off the power supply of the module in sleep mode to reduce static power consumption, and turn on the power supply when the wake-up signal arrives to restore to normal mode. Therefore, quickly reducing static power consumption and faster wake-up speed have become key indicators of MCU chip low power consumption performance.

[0003] However, power gating technology generally directly disconnects the power supply of the modules. At this time, the power supply of these modules is in a floating state, and the parasitic load capacitance is large. There is still residual charge at the disconnected power supply. Therefore, the static power consumption of the MCU decreases slowly. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first object of the present invention is to provide a low-power control circuit, which discharges the residual charge at the power supply terminal of the power-off module through the discharge module when the power-off module is powered off, and quickly discharges the suspended power supply charge of the power-off module to the ground, thereby reducing the static power consumption of the chip.

[0005] The second objective of the present invention is to provide a chip.

[0006] The third objective of the present invention is to provide a microcontroller.

[0007] A fourth objective of the present invention is to provide a low power consumption control method.

[0008] To achieve the above-mentioned purpose, a low-power consumption control circuit is proposed according to an embodiment of the first aspect of the present invention, which is applied to a chip, wherein the chip includes a power-off module, and the low-power consumption control circuit includes: a controllable switch module, wherein the first end of the controllable switch module is suitable for connecting to a power supply, and the second end of the controllable switch module is suitable for connecting to a power supply end of the power-off module; a discharge module, wherein the first end of the discharge module is connected to the power supply end of the power-off module, and the second end of the discharge module is grounded; and a power control module, which is configured to respond to a sleep instruction, and when the controllable switch module is controlled to be disconnected, control the discharge module to discharge the residual charge at the power supply end of the power-off module.

[0009] According to the low-power control circuit of the embodiment of the present invention, it includes a controllable switch module, a discharge module and a power control module, wherein the first end of the controllable switch module is suitable for connecting to the power supply, the second end of the controllable switch module is suitable for connecting to the power end of the power-off module, the first end of the discharge module is connected to the power end of the power-off module, the second end of the discharge module is grounded, and the power control module is configured to respond to the sleep instruction, and when the controllable switch module is disconnected, the discharge module is controlled to discharge the residual charge of the power end of the power-off module. Therefore, when the power control module controls the controllable switch module to disconnect, the power end of the power-off module is suspended, and then the discharge module discharges the residual charge of the power end of the power-off module to the ground, so as to quickly discharge the suspended power charge of the power-off module to the ground, thereby reducing the static power consumption of the chip.

[0010] According to one embodiment of the present invention, the low power consumption control circuit further includes: a voltage detection module, wherein the detection end of the voltage detection module is connected to the power end of the power-off module, and is suitable for detecting the power-on voltage of the power-off module to output a voltage detection signal; the power control module is also configured to control the controllable switch module to close in response to a wake-up signal, and control the chip to enter a working state when it is determined according to the voltage detection signal that the power-on voltage reaches a preset reference voltage.

[0011] According to an embodiment of the present invention, the power control module is further configured to control the discharge module to stop the discharge operation when the time for the discharge module to discharge the residual charge at the power supply end reaches a preset time.

[0012] According to one embodiment of the present invention, the discharge module includes a discharge switch and a discharge resistor connected in series.

[0013] According to one embodiment of the present invention, a first end of the discharge switch is connected to a power supply end of the power-off module, a second end of the discharge switch is connected to one end of a discharge resistor, a control end of the discharge switch is connected to a first control output end of the power control module, and the other end of the discharge resistor is grounded.

[0014] According to an embodiment of the present invention, the discharge switch includes at least one of a thyristor, a triode, and a MOS tube.

[0015] According to one embodiment of the present invention, the voltage detection module includes: a first resistor, one end of the first resistor is connected to the power supply end of the power-off module; a second resistor, one end of the second resistor is connected to the other end of the first resistor and has a first node, and the other end of the second resistor is grounded; a first comparator, the positive input end of the first comparator is connected to the first node, the negative input end of the first comparator is suitable for connecting to the reference voltage providing end, and the output end of the first comparator is connected to the input end of the power control module.

[0016] According to one embodiment of the present invention, the controllable switch module includes a PMOS tube, the source of the PMOS tube is suitable for connecting to a power supply, the gate of the PMOS tube is connected to the second control output terminal of the power control module, and the drain of the PMOS tube is connected to the power supply terminal of the power-off module.

[0017] To achieve the above objective, a chip is provided according to a second aspect of the present invention, comprising a low power consumption control circuit according to any of the above embodiments.

[0018] According to the chip of the embodiment of the present invention, by adopting the above-mentioned low-power control circuit, when the power-off module is powered off, the residual charge at the power supply end of the power-off module is discharged through the discharge module, and the suspended power supply charge of the power-off module is quickly discharged to the ground, thereby reducing the static power consumption of the chip.

[0019] To achieve the above objective, a microcontroller is provided according to a third aspect of the present invention, comprising the aforementioned chip.

[0020] According to the microcontroller of the embodiment of the present invention, by adopting the above-mentioned chip, when the power-off module is powered off, the residual charge at the power supply end of the power-off module is discharged through the discharge module, and the suspended power supply charge of the power-off module is quickly discharged to the ground, thereby reducing the static power consumption of the chip.

[0021] To achieve the above-mentioned purpose, a low-power consumption control method is proposed according to an embodiment of the fourth aspect of the present invention, which is applied to a chip. The chip includes a power-off module, a controllable switch module and a discharge module. The controllable switch module is suitable for controlling the power supply of the power supply to the power-off module, and the discharge module is suitable for establishing a discharge path for the residual charge at the power supply end of the power-off module. The method includes: in response to a sleep instruction, controlling the controllable switch module to disconnect, and when the power supply is disconnected from the power supply to the power-off module, controlling the discharge module to discharge the residual charge at the power supply end of the power-off module.

[0022] According to the low power consumption control method of the embodiment of the present invention, in response to the sleep instruction, the controllable switch module is controlled to be disconnected, and when the power supply is disconnected to supply power to the power-off module, the discharge module is controlled to discharge the residual charge at the power supply end of the power-off module. When the controllable switch module is controlled to be disconnected, the power supply end of the power-off module is suspended, and then the discharge module discharges the residual charge at the power supply end of the power-off module to the ground, thereby realizing the rapid discharge of the suspended power supply charge of the power-off module to the ground, thereby reducing the static power consumption of the chip.

[0023] According to one embodiment of the present invention, the chip also includes a voltage detection module, which is suitable for detecting the power-on voltage of the power-off module to output a voltage detection signal. The method also includes: in response to a wake-up signal, controlling the controllable switch module to close, and controlling the chip to enter a working state when it is determined according to the voltage detection signal that the power-on voltage reaches a preset reference voltage.

[0024] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of the structure of a chip according to an embodiment of the present invention;

[0026] Figure 2 is a timing diagram of a low power consumption control circuit according to an embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of the structure of a clock source management module and an isolator according to an embodiment of the present invention;

[0028] Figure 4 is a schematic structural diagram of a chip according to another embodiment of the present invention;

[0029] Figure 5 is a circuit diagram of a discharge module according to an embodiment of the present invention;

[0030] Figure 6 is a circuit diagram of a voltage detection module according to an embodiment of the present invention;

[0031] Figure 7 is a circuit diagram of a controllable switch module according to an embodiment of the present invention;

[0032] Figure 8 is a schematic diagram of the structure of a microcontroller according to an embodiment of the present invention;

[0033] Fig. 9 is a flowchart of a low power consumption control method according to an embodiment of the present invention;

[0034] Fig.10 It is a flowchart of a low power consumption control method according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0036] The low power consumption control circuit, chip, microcontroller and low power consumption control method according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0037] Figure 1 FIG. 1 is a schematic diagram of the structure of a chip according to an embodiment of the present invention. Figure 1 As shown, the low power consumption control circuit 100 is applied to a chip 1000 , and the chip 1000 includes a power-off module 200 . The low power consumption control circuit 100 includes: a controllable switch module 10 , a discharge module 20 and a power control module 30 .

[0038] Among them, the first end of the controllable switch module 10 is suitable for connecting to the power supply VDD, and the second end of the controllable switch module 10 is suitable for connecting to the power supply end of the power-off module 200; the first end of the discharge module 20 is connected to the power supply end of the power-off module 200, and the second end of the discharge module 20 is grounded; the power control module 30 is configured to respond to the sleep instruction, and when the controllable switch module 10 is controlled to be disconnected, the discharge module 20 is controlled to discharge the residual charge at the power supply end of the power-off module 200.

[0039] Specifically, when the controllable switch module 10 is closed, the power supply terminal of the power-off module 200 is connected to the power supply VDD, and the power-off module 200 is powered on. Figure 2 As shown, after receiving the sleep instruction, the power control module 30 outputs the first control signal PWN to control the controllable switch module 10 to disconnect, so that the connection between the power supply end of the power-off module 200 and the power supply VDD is disconnected, and the power supply end of the power-off module 200 is suspended. At this time, there is residual charge at the power supply end of the power-off module 200. Therefore, the power supply end voltage of the power-off module 200 is not 0. The power control module 30 outputs the second control signal LEAKEN to control the discharge module 20 to discharge the residual charge at the power supply end of the power-off module 200. The discharge module 20 quickly discharges the residual charge to the ground, and the power supply end voltage of the power-off module 200 drops to 0, and the chip 1000 enters the sleep state.

[0040] It should be noted that the total power signal of the power supply VDD needs to be kept on all the time. The sleep instruction may be sent by the CPU (Central Processing Unit) to the power control module 30 .

[0041] In an optional embodiment, if Figure 3 As shown, the power control module 30 is also configured to control the system clock management module 300 of the chip 1000 to stop outputting the system clock after receiving the sleep instruction. The system clock includes clock signal 1 and clock signal 2, and turn on the isolator 400 in the chip 1000. After the chip 1000 enters the sleep state, the chip 1000 stops working, so the system clock can be stopped, thereby further reducing the standby power consumption of the chip 1000. The chip 1000 is also provided with a voltage normally open module 500, which always remains in the power-on state. Therefore, it is necessary to turn on the isolator 400 to isolate the power-off module 200 from the voltage normally open module 500 in the chip 1000, so as to avoid interference to the voltage normally open module 500 when the power-off module 200 is powered off. In the above embodiment, when the power-off module is powered off, the power control module controls the discharge module to discharge the residual charge at the power supply end of the power-off module, and quickly discharges the suspended power supply charge of the power-off module to the ground, thereby reducing the static power consumption of the chip.

[0042] In some embodiments, Figure 4 As shown, the low power control circuit 100 also includes: a voltage detection module 40, the detection end of the voltage detection module 40 is connected to the power end of the power-off module 200, and is suitable for detecting the power-on voltage VDDP of the power-off module 200 to output a voltage detection signal PWR_VALID; the power control module 30 is also configured to control the controllable switch module 10 to close in response to the wake-up signal, and when it is determined according to the voltage detection signal PWR_VALID that the power-on voltage VDDP reaches a preset reference voltage, the control chip 1000 enters a working state.

[0043] Specifically, in the related art, after receiving the wake-up signal sent by the CPU, the power control module 30 controls the controllable switch module 10 to close to restore the power supply to the power-off module 200. The hardware circuit in the MCU is configured with a fixed recovery time to wait for the power supply voltage to stabilize and then continue to run the program. Although the circuit cost is low, the response speed is slow. Therefore, the low-power control circuit 100 of this embodiment also includes a voltage detection module 40, such as Figure 2As shown, when the chip 1000 is in the sleep mode, the power control module 30 responds to the wake-up signal and outputs the first control signal PWN to control the controllable switch module 10 to close, the power end of the power-off module 200 is connected to the power supply VDD, the power-off module 200 is powered on, and the voltage detection module 40 detects the power-on voltage VDDP of the power-off module 200 (that is, the power end voltage of the power-off module 200) and outputs the voltage detection signal PWR_VALID. The power control module 30 determines whether the power-on voltage VDDP reaches the preset reference voltage according to the voltage detection signal PWR_VALID. When the power-on voltage VDDP reaches the preset reference voltage, it indicates that the power-on voltage VDDP has recovered to be stable. Therefore, the power control module 30 controls the chip 1000 to enter the working state.

[0044] In an optional embodiment, if Figure 3 As shown, the power control module 30 is also configured to close the isolator 400 and turn on the system clock management module 300 when it is determined according to the voltage detection signal PWR_VALID that the power-on voltage VDDP reaches the preset reference voltage. When the power-on voltage VDDP reaches the preset reference voltage, the chip 1000 needs to enter the working state, so the power control module 30 needs to turn on the system clock to ensure that the chip 1000 can operate normally. At this time, the power-off module 200 has been powered on normally, and there will be no interference between the power-off module 200 and the voltage normally-on module 500, so the isolator 400 is turned off.

[0045] In the above embodiment, the power-on voltage of the power-off module is detected by the voltage detection module. When the power-on voltage of the power-off module reaches the preset reference voltage, the chip can be immediately controlled to enter the working state, thereby improving the response speed of the chip.

[0046] In some embodiments, the power control module 30 is further configured to control the discharge module 20 to stop the discharge operation when the discharge module 20 discharges the residual charge at the power supply end for a preset time.

[0047] That is to say, when the time for the discharge module 20 to discharge the residual charge at the power supply end reaches the preset time, the discharge module 20 has completely discharged the residual charge to the ground, and the discharge module 20 does not need to perform the discharge work. Therefore, the power control module 30 controls the discharge module 20 to stop the discharge work.

[0048] In some embodiments, Figure 5 As shown, the discharge module 20 includes a discharge switch S and a discharge resistor R connected in series.

[0049] It can be understood that by controlling the switching state of the discharge switch S, the working state of the discharge module 20 can be controlled. When the discharge switch S is closed, the discharge module 20 performs the discharge work, and when the discharge switch S is disconnected, the discharge module 20 stops the discharge work.

[0050] In some embodiments, Figure 5 As shown, the first end of the discharge switch S is connected to the power supply end of the power-off module 200, the second end of the discharge switch S is connected to one end of the discharge resistor R, the control end of the discharge switch S is connected to the first control output end of the power control module 30, and the other end of the discharge resistor R is grounded.

[0051] Specifically, when the power control module 30 controls the discharge switch S to be closed, the discharge resistor R is connected to the power supply end of the power-off module 200 to form a path, and the residual charge at the power supply end of the power-off module 200 is discharged to the ground through the discharge resistor R; when the power control module 30 controls the discharge switch S to be disconnected, the discharge resistor R and the power supply end of the power-off module 200 are disconnected, and the discharge module 20 stops the discharge work.

[0052] Furthermore, in some embodiments, the discharge switch S includes at least one of a thyristor, a triode, and a MOS tube.

[0053] It should be noted that the discharge switch S is not limited to the above three switches, and may also be other switches as long as it can be switched according to the second control signal LEAKEN of the power control module 30, and no specific limitation is made here.

[0054] In some embodiments, Figure 6 As shown, the voltage detection module 40 includes: a first resistor R1, a second resistor R2 and a first comparator 41, wherein one end of the first resistor R1 is connected to the power supply end of the power-off module 200; one end of the second resistor R2 is connected to the other end of the first resistor R1 and has a first node J1, and the other end of the second resistor R2 is grounded; the positive input end of the first comparator 41 is connected to the first node J1, the negative input end of the first comparator 41 is suitable for connecting to the reference voltage VBG providing end, and the output end of the first comparator 41 is connected to the input end of the power control module 30.

[0055] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider circuit to divide the power-on voltage VDDP of the power-off module 200, and input the divided power-on voltage to the positive input terminal of the first comparator 41. The negative input terminal of the first comparator 41 is suitable for connecting to the reference voltage VBG providing terminal. The reference voltage VBG is set by a preset reference voltage. For example, if the divided power-on voltage is 1 / 2 of the power-on voltage VDDP, the reference voltage VBG can also be 1 / 2 of the preset reference voltage. When the divided power-on voltage is greater than or equal to the reference voltage VBG, the first comparator 41 outputs a high level. When the divided power-on voltage is less than the reference voltage VBG, the first comparator 41 outputs a low level. When the electrical signal output by the first comparator 41 is a voltage detection signal PWR_VALID, such as Figure 2 As shown, when the voltage detection signal PWR_VALID is at a high level, the power-on voltage after voltage division is greater than or equal to the reference voltage VBG, so the power-on voltage VDDP reaches the preset reference voltage, and the power control module 30 controls the chip 1000 to enter the working state; when the voltage detection signal PWR_VALID is at a low level, the power-on voltage after voltage division is less than the reference voltage VBG, so the power-on voltage VDDP does not reach the preset reference voltage, and the chip 1000 remains in a sleep state.

[0056] In some embodiments, Figure 7 As shown, the controllable switch module 10 includes a PMOS (Positive Channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor field effect transistor) tube Q1, the source of the PMOS tube Q1 is suitable for connecting to the power supply VDD, the gate of the PMOS tube Q1 is connected to the second control output terminal of the power control module 30, and the drain of the PMOS tube Q1 is connected to the power supply terminal of the power-off module 200.

[0057] Specifically, Figure 2 As shown, when the first control signal PWN output by the power control module 30 is at a low level, the PMOS tube Q1 is turned on, the controllable switch module 10 is closed, and the power supply end of the power-off module 200 is connected to the power supply VDD; when the first control signal PWN output by the power control module 30 is at a high level, the PMOS tube Q1 is turned off, the controllable switch module 10 is turned on, and the power supply end of the power-off module 200 is disconnected from the power supply VDD.

[0058] It should be noted that the switch tube in the controllable switch module 10 can also be an NMOS (Negative Channel Metal Oxide Semiconductor) tube. When the switch tube is an NMOS tube, when the first control signal PWN is at a high level, the controllable switch module 10 is closed, and when the first control signal PWN is at a low level, the controllable switch module 10 is disconnected.

[0059] In summary, the low-power control circuit according to the embodiment of the present invention includes a controllable switch module, a discharge module and a power control module, wherein the first end of the controllable switch module is suitable for connecting to a power supply, the second end of the controllable switch module is suitable for connecting to a power end of a power-down module, the first end of the discharge module is connected to the power end of the power-down module, the second end of the discharge module is grounded, and the power control module is configured to respond to a sleep instruction, and when the controllable switch module is disconnected, the discharge module is controlled to discharge the residual charge of the power end of the power-down module. Therefore, when the power control module controls the controllable switch module to disconnect, the power end of the power-down module is suspended, and then the discharge module discharges the residual charge of the power end of the power-down module to the ground, so that the suspended power charge of the power-down module is quickly discharged to the ground, thereby reducing the static power consumption of the chip; and the power-on voltage of the power-down module is detected by the voltage detection module, and when the power-on voltage of the power-down module reaches a preset reference voltage, the chip can be immediately controlled to enter a working state, thereby improving the response speed of the chip.

[0060] Corresponding to the above embodiment, the embodiment of the present invention further provides a chip. Figure 1 As shown, the chip 1000 includes the low power consumption control circuit 100 of any of the aforementioned embodiments.

[0061] According to the chip of the embodiment of the present invention, by adopting the above-mentioned low-power control circuit, when the power-off module is powered off, the residual charge at the power supply end of the power-off module is discharged through the discharge module, and the suspended power supply charge of the power-off module is quickly discharged to the ground, thereby reducing the static power consumption of the chip.

[0062] Corresponding to the above embodiment, the embodiment of the present invention further provides a microcontroller. Figure 8 As shown, the microcontroller 2000 includes the aforementioned chip 1000 .

[0063] According to the microcontroller of the embodiment of the present invention, by adopting the above-mentioned chip, when the power-off module is powered off, the residual charge at the power supply end of the power-off module is discharged through the discharge module, and the suspended power supply charge of the power-off module is quickly discharged to the ground, thereby reducing the static power consumption of the chip.

[0064] Corresponding to the above embodiment, the embodiment of the present invention further provides a low power consumption control method. Figure 1 As shown, the chip 1000 includes a power-off module 200, a controllable switch module 10 and a discharge module 20. The controllable switch module 10 is suitable for controlling the power supply VDD to the power-off module 200. The discharge module 20 is suitable for establishing a discharge path for residual charge at the power supply end of the power-off module 200. Fig. 9 As shown, the low power consumption control method includes:

[0065] S101, in response to a sleep instruction, controlling a controllable switch module to be disconnected, and controlling a discharge module to discharge residual charge at a power supply terminal of the power-down module when a power supply is disconnected from supplying power to the power-down module.

[0066] Specifically, when the controllable switch module 10 is closed, the power supply terminal of the power-off module 200 is connected to the power supply VDD, and the power-off module 200 is powered on. Figure 2 As shown, after receiving the sleep instruction, the power control module 30 outputs the first control signal PWN to control the controllable switch module 10 to disconnect, so that the connection between the power supply end of the power-off module 200 and the power supply VDD is disconnected, and the power supply end of the power-off module 200 is suspended. At this time, there is residual charge at the power supply end of the power-off module 200. Therefore, the power supply end voltage of the power-off module 200 is not 0. The power control module 30 outputs the second control signal LEAKEN to control the discharge module 20 to discharge the residual charge at the power supply end of the power-off module 200. The discharge module 20 quickly discharges the residual charge to the ground, and the power supply end voltage of the power-off module 200 drops to 0, and the chip 1000 enters the sleep state.

[0067] It should be noted that the total power signal of the power supply VDD needs to be kept on all the time. The sleep instruction can be sent by the CPU to the power control module 30 .

[0068] In an optional embodiment, after receiving the sleep instruction, the method further includes: controlling the system clock management module of the chip to stop outputting the system clock, and turning on the isolator in the chip, wherein the system clock includes clock signal 1 and clock signal 2. After the chip enters the sleep state, the chip stops working, so the system clock can be stopped, thereby further reducing the standby power consumption of the chip. A voltage normally-on module is also provided in the chip, and the voltage normally-on module always remains in the power-on state. Therefore, it is necessary to turn on the isolator to isolate the power-off module from the voltage normally-on module in the chip to avoid interference with the voltage normally-on module when the power-off module is powered off.

[0069] In the above embodiment, when the power-off module is powered off, the power control module controls the discharge module to discharge the residual charge at the power supply end of the power-off module, and quickly discharges the suspended power supply charge of the power-off module to the ground, thereby reducing the static power consumption of the chip.

[0070] In some embodiments, the chip 1000 also includes a voltage detection module 40, which is suitable for detecting the power-on voltage VDDP of the power-off module 200 to output a voltage detection signal PWR_VALID. The method also includes: in response to a wake-up signal, controlling the controllable switch module 10 to close, and when it is determined according to the voltage detection signal PWR_VALID that the power-on voltage VDDP reaches a preset reference voltage, controlling the chip 1000 to enter a working state.

[0071] Specifically, in the related art, after receiving the wake-up signal sent by the CPU, the power control module 30 controls the controllable switch module 10 to close to restore the power supply to the power-off module 200. The hardware circuit in the MCU is configured with a fixed recovery time to wait for the power supply voltage to stabilize and then continue to run the program. Although the circuit cost is low, the response speed is slow. Therefore, the low-power control circuit 100 of this embodiment also includes a voltage detection module 40, such as Figure 2 As shown, when the chip 1000 is in the sleep mode, the power control module 30 responds to the wake-up signal and outputs the first control signal PWN to control the controllable switch module 10 to close, the power end of the power-off module 200 is connected to the power supply VDD, the power-off module 200 is powered on, and the voltage detection module 40 detects the power-on voltage VDDP of the power-off module 200 (that is, the power end voltage of the power-off module 200) and outputs the voltage detection signal PWR_VALID. The power control module 30 determines whether the power-on voltage VDDP reaches the preset reference voltage according to the voltage detection signal PWR_VALID. When the power-on voltage VDDP reaches the preset reference voltage, it indicates that the power-on voltage VDDP has recovered to be stable. Therefore, the power control module 30 controls the chip 1000 to enter the working state.

[0072] In an optional embodiment, when it is determined according to the voltage detection signal PWR_VALID that the power-on voltage VDDP reaches the preset reference voltage, the method further includes: turning off the isolator and turning on the system clock management module. When the power-on voltage reaches the preset reference voltage, the chip needs to enter the working state, so the power control module needs to turn on the system clock to ensure that the chip can operate normally. At this time, the power-off module has been powered on normally, and there will be no interference between the power-off module and the voltage normally-on module, so the isolator is turned off.

[0073] In the above embodiment, the power-on voltage of the power-off module is detected by the voltage detection module. When the power-on voltage of the power-off module reaches the preset reference voltage, the chip can be immediately controlled to enter the working state, thereby improving the response speed of the chip.

[0074] In some embodiments, the method further includes: when the time for the discharge module 20 to discharge the residual charge at the power supply end reaches a preset time, controlling the discharge module 20 to stop the discharge operation.

[0075] That is to say, when the time for the discharge module 20 to discharge the residual charge at the power supply end reaches the preset time, the discharge module 20 has completely discharged the residual charge to the ground, and the discharge module 20 does not need to perform the discharge work. Therefore, the power control module 30 controls the discharge module 20 to stop the discharge work.

[0076] In some embodiments, Figure 5 As shown, the discharge module 20 includes a discharge switch S and a discharge resistor R connected in series.

[0077] It can be understood that by controlling the switching state of the discharge switch S, the working state of the discharge module 20 can be controlled. When the discharge switch S is closed, the discharge module 20 performs the discharge work, and when the discharge switch S is disconnected, the discharge module 20 stops the discharge work.

[0078] In some embodiments, Figure 5 As shown, the first end of the discharge switch S is connected to the power supply end of the power-off module 200, the second end of the discharge switch S is connected to one end of the discharge resistor R, the control end of the discharge switch S is connected to the first control output end of the power control module 30, and the other end of the discharge resistor R is grounded.

[0079] Specifically, when the power control module 30 controls the discharge switch S to be closed, the discharge resistor R is connected to the power supply end of the power-off module 200 to form a path, and the residual charge at the power supply end of the power-off module 200 is discharged to the ground through the discharge resistor R; when the power control module 30 controls the discharge switch S to be disconnected, the discharge resistor R and the power supply end of the power-off module 200 are disconnected, and the discharge module 20 stops the discharge work.

[0080] Furthermore, in some embodiments, the discharge switch S includes at least one of a thyristor, a triode, and a MOS tube.

[0081] It should be noted that the discharge switch S is not limited to the above three switches, and may also be other switches as long as it can be switched according to the second control signal LEAKEN of the power control module 30, and no specific limitation is made here.

[0082] In some embodiments, Figure 6As shown, the voltage detection module 40 includes: a first resistor R1, a second resistor R2 and a first comparator 41, wherein one end of the first resistor R1 is connected to the power supply end of the power-off module 200; one end of the second resistor R2 is connected to the other end of the first resistor R1 and has a first node J1, and the other end of the second resistor R2 is grounded; the positive input end of the first comparator 41 is connected to the first node J1, the negative input end of the first comparator 41 is suitable for connecting to the reference voltage VBG providing end, and the output end of the first comparator 41 is connected to the input end of the power control module 30.

[0083] Specifically, the first resistor R1 and the second resistor R2 form a voltage divider circuit to divide the power-on voltage VDDP of the power-off module 200, and input the divided power-on voltage to the positive input terminal of the first comparator 41. The negative input terminal of the first comparator 41 is suitable for connecting to the reference voltage VBG providing terminal. The reference voltage VBG is set by the preset reference voltage VBG. For example, if the divided power-on voltage is 1 / 2 of the power-on voltage VDDP, the reference voltage VBG can also be 1 / 2 of the preset reference voltage. When the divided power-on voltage is greater than or equal to the reference voltage VBG, the first comparator 41 outputs a high level. When the divided power-on voltage is less than the reference voltage VBG, the first comparator 41 outputs a low level. When the electrical signal output by the first comparator 41 is a voltage detection signal PWR_VALID, such as Figure 2 As shown, when the voltage detection signal PWR_VALID is at a high level, the power-on voltage after voltage division is greater than or equal to the reference voltage VBG, so the power-on voltage VDDP reaches the preset reference voltage, and the power control module 30 controls the chip 1000 to enter the working state; when the voltage detection signal PWR_VALID is at a low level, the power-on voltage after voltage division is less than the reference voltage VBG, so the power-on voltage VDDP does not reach the preset reference voltage, and the chip 1000 remains in a sleep state.

[0084] In some embodiments, Figure 7 As shown, the controllable switch module 10 includes a PMOS (Positive Channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor field effect transistor) tube Q1, the source of the PMOS tube Q1 is suitable for connecting to the power supply VDD, the gate of the PMOS tube Q1 is connected to the second control output terminal of the power control module 30, and the drain of the PMOS tube Q1 is connected to the power supply terminal of the power-off module 200.

[0085] Specifically, Figure 2As shown, when the first control signal PWN output by the power control module 30 is at a low level, the PMOS tube Q1 is turned on, the controllable switch module 10 is closed, and the power supply end of the power-off module 200 is connected to the power supply VDD; when the first control signal PWN output by the power control module 30 is at a high level, the PMOS tube Q1 is turned off, the controllable switch module 10 is turned on, and the power supply end of the power-off module 200 is disconnected from the power supply VDD.

[0086] It should be noted that the switch tube in the controllable switch module 10 can also be an NMOS (Negative Channel Metal Oxide Semiconductor) tube. When the switch tube is an NMOS tube, when the first control signal PWN is at a high level, the controllable switch module 10 is closed, and when the first control signal PWN is at a low level, the controllable switch module 10 is disconnected.

[0087] The technical solution of the present application is further described in detail below in conjunction with specific implementation methods:

[0088] like Fig.10 As shown, the low power consumption control method includes the following steps:

[0089] S201, when the chip is in working state, receiving a sleep instruction sent by the CPU.

[0090] S202, the control system clock is stopped and the isolator in the chip is turned on.

[0091] S203, controlling the controllable switch module to disconnect.

[0092] S204, controlling the discharge module to discharge the residual charge at the power supply end of the power-off module, so that the chip completes the discharge and enters a dormant state.

[0093] S205: Receive a wake-up signal sent by the CPU.

[0094] S206, controlling the controllable switch module to close.

[0095] S207, judging whether the power-on voltage reaches the preset reference voltage according to the voltage detection signal of the voltage detection module, if the power-on voltage reaches the preset reference voltage, executing step S208, if the power-on voltage VDDP does not reach the preset reference voltage, returning to step S207.

[0096] S208, turn off the isolator and turn on the system clock.

[0097] S209, the control chip enters the working state.

[0098] In the above embodiment, when the power-off module is powered off, the residual charge at the power supply end of the power-off module is quickly discharged to the ground through the discharge module, thereby reducing the static power consumption of the chip; and the power-on voltage of the power-off module is detected by the voltage detection module. When the power-on voltage of the power-off module reaches a preset reference voltage, the chip can be immediately controlled to enter a working state, thereby improving the response speed of the chip.

[0099] In summary, according to the low power consumption control method of the embodiment of the present invention, in response to the sleep instruction, the controllable switch module is controlled to be disconnected, and when the power supply is disconnected to supply power to the power-off module, the discharge module is controlled to discharge the residual charge at the power supply end of the power-off module. When the controllable switch module is controlled to be disconnected, the power supply end of the power-off module is suspended, and then the discharge module discharges the residual charge at the power supply end of the power-off module to the ground, thereby realizing the rapid discharge of the suspended power supply charge of the power-off module to the ground, thereby reducing the static power consumption of the chip; the power-on voltage of the power-off module is detected by the voltage detection module, and when the power-on voltage of the power-off module reaches the preset reference voltage, the chip can be immediately controlled to enter the working state, thereby improving the response speed of the chip.

[0100] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0101] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0103] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0104] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0105] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0106] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A low power consumption control circuit, characterized in that: Applied to a chip, the chip includes a power-down module, and the low-power consumption control circuit includes: A controllable switch module, wherein a first end of the controllable switch module is suitable for connecting to a power supply, and a second end of the controllable switch module is suitable for connecting to a power supply end of the power-off module; A discharge module, wherein a first end of the discharge module is connected to a power supply end of the power-off module, and a second end of the discharge module is grounded; The power control module is configured to control the discharge module to discharge the residual charge at the power supply terminal of the power-off module in response to the sleep instruction while controlling the controllable switch module to be disconnected.

2. The low power consumption control circuit according to claim 1, characterized in that: Also includes: A voltage detection module, wherein a detection end of the voltage detection module is connected to a power supply end of the power-off module, and is adapted to detect a power-on voltage of the power-off module to output a voltage detection signal; The power control module is further configured to, in response to a wake-up signal, control the controllable switch module to close, and control the chip to enter a working state when it is determined according to the voltage detection signal that the power-on voltage reaches a preset reference voltage.

3. The low power consumption control circuit according to claim 1 or 2, characterized in that: The power control module is further configured to control the discharge module to stop the discharge operation when the time for the discharge module to discharge the residual charge at the power supply end reaches a preset time.

4. The low power consumption control circuit according to claim 3, characterized in that: The discharge module includes a discharge switch and a discharge resistor connected in series.

5. The low power consumption control circuit according to claim 4, characterized in that: The first end of the discharge switch is connected to the power supply end of the power-off module, the second end of the discharge switch is connected to one end of the discharge resistor, the control end of the discharge switch is connected to the first control output end of the power control module, and the other end of the discharge resistor is grounded.

6. The low power consumption control circuit according to claim 4, characterized in that: The discharge switch includes at least one of a thyristor, a triode, and a MOS tube.

7. The low power consumption control circuit according to claim 2, characterized in that: The voltage detection module comprises: A first resistor, one end of which is connected to a power supply end of the power-off module; a second resistor, one end of the second resistor being connected to the other end of the first resistor and having a first node, and the other end of the second resistor being grounded; A first comparator, wherein the positive input terminal of the first comparator is connected to the first node, the negative input terminal of the first comparator is suitable for connecting to a reference voltage supply terminal, and the output terminal of the first comparator is connected to the input terminal of the power control module.

8. The low power consumption control circuit according to claim 1, characterized in that: The controllable switch module includes a PMOS tube, the source of the PMOS tube is suitable for connecting to the power supply, the gate of the PMOS tube is connected to the second control output end of the power control module, and the drain of the PMOS tube is connected to the power end of the power-off module.

9. A chip, characterized in that: The invention comprises a low power consumption control circuit according to any one of claims 1 to 8.

10. A microcontroller, characterized in that: Comprising the chip according to claim 9.

11. A low power consumption control method, characterized in that: Applied to a chip, the chip includes a power-off module, a controllable switch module and a discharge module, the controllable switch module is suitable for controlling the power supply of the power supply to the power-off module, the discharge module is suitable for establishing a discharge path for residual charge at the power supply end of the power-off module, and the method includes: In response to a sleep instruction, the controllable switch module is controlled to be disconnected, and when the power supply is disconnected from supplying power to the power-off module, the discharge module is controlled to discharge residual charge at the power supply terminal of the power-off module.

12. The method according to claim 11, characterized in that The chip further includes a voltage detection module, and the voltage detection module is adapted to detect the power-on voltage of the power-off module to output a voltage detection signal. The method further includes: In response to the wake-up signal, the controllable switch module is controlled to be closed, and when it is determined according to the voltage detection signal that the power-on voltage reaches a preset reference voltage, the chip is controlled to enter a working state.

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