Storage device, storage system, and method for operating a storage system

Abstract

A storage device, a storage system and a method for operating the storage system are provided. The storage system may include a host device and a storage device. The storage device may be configured to perform an eye opening monitor (EOM) operation on a signal received from the host device to generate an EOM result value when powered on, to store the EOM result value in a buffer memory, and to output the EOM result value in the buffer memory to the host device in response to receiving an asynchronous event request (AER) command from the host device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a storage device and a storage system including the storage device. Background Art

[0002] Recently, interest in high-speed transmission systems capable of high-speed data transmission is increasing. While a signal passes through a transmission channel such as a cable, a printed circuit board, or an optical fiber, the waveform of the data is affected by bandwidth limitations.

[0003] Eye open monitors (EOMs) are used to identify quality characteristics of signals transmitted and received on a channel. For example, the eye diagram of a signal received at a signal receiving end in a storage device can be measured. At the same time, as data capacity increases and data transmission speeds increase, the time required to measure the eye diagram of a signal may become a major factor limiting data transmission speeds. Summary of the invention

[0004] Example embodiments of the present disclosure provide a storage device having enhanced signal quality and a storage system including the storage device.

[0005] According to an aspect of an example embodiment, a storage system may include: a host device; and a storage device, the storage device being configured to: upon being powered on, perform an eye opening monitor (EOM) operation on a signal received from the host device to generate an EOM result value, be configured to store the EOM result value in a buffer memory, and be configured to output the EOM result value in the buffer memory to the host device in response to receiving an asynchronous event request (AER) command from the host device.

[0006] According to an aspect of an example embodiment, a method of operating a storage system may include: performing, by a storage device, an eye opening monitor (EOM) operation on a received signal based on being powered on to generate an EOM result value; receiving an asynchronous event request (AER) command from a host device; and sending the EOM result value to the host device.

[0007] According to an aspect of an example embodiment, a storage device may include: an equalizer configured to adjust a gain of a received signal to generate an equalized serial bit; an eye opening monitor (EOM) unit configured to: input the equalized serial bit into a main path to obtain a first output based on a reference condition, the reference condition including a reference clock and a reference voltage; input the equalized serial bit into an EOM path while changing an offset clock and an offset voltage to obtain a second output; and generate an error count signal based on a count of an error between the first output and the second output, and generate a sampling count signal based on a count of a comparison between the first output and the second output; an eye diagram generation (EGU) unit configured to generate an eye diagram based on the error count signal and the sampling count signal, in which the received signal is divided into unit intervals and values ​​of the divided segments are superimposed on each other, and the eye diagram generation unit is configured to generate an EOM result value including at least one of the error count signal or the eye diagram; and an analog front end (AFE) end, AFE) controller, the analog front end controller is configured to control the equalizer based on the EOM result value. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a diagram illustrating a storage system according to example embodiments.

[0010] Figure 2 is a diagram illustrating a host interface according to an example embodiment.

[0011] Figure 3 is a diagram for explaining the operation of a clock data recovery (CDR) block according to example embodiments.

[0012] Figure 4 is a diagram for explaining the operation of an eye opening monitor (EOM).

[0013] Figure 5 is a diagram illustrating a memory controller and a memory device according to example embodiments.

[0014] Figure 6 It is shown Figure 5 A block diagram of a memory device.

[0015] Figure 7is a diagram illustrating a storage system according to example embodiments.

[0016] Figure 8 and Fig. 9 is a flowchart for explaining a process of performing an EOM operation of a storage device according to an example embodiment.

[0017] Fig.10 is a diagram illustrating a storage system according to example embodiments.

[0018] Fig.11 It shows that according to Fig.10 A diagram of an example of a storage system.

[0019] Fig.12 It shows that according to Fig.10 A diagram of an example of a storage system.

[0020] Fig.13 is a diagram illustrating a data transmission and reception system according to an exemplary embodiment.

[0021] Fig.14 is a diagram illustrating a user system to which a storage system according to an example embodiment is applied. DETAILED DESCRIPTION

[0022] In the following detailed description, only certain exemplary embodiments of the present disclosure are shown and described by way of illustration. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0023] Therefore, the drawings and description are to be considered as illustrative in nature and not restrictive. Throughout the specification, the same reference numerals represent the same elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, certain operations may be divided, and specific operations may not be performed.

[0024] In addition, unless an explicit expression such as "one" or "single" is used, an expression written in the singular may be interpreted in the singular or plural. Terms including ordinal numbers such as first, second, etc. will only be used to describe various components and should not be interpreted as limiting these components. These terms may be used to distinguish one component from other components.

[0025] Figure 1 is a diagram illustrating a storage system according to example embodiments.

[0026] In an embodiment, the storage system 10 may be included in a user device such as a personal computer, a laptop computer, a server, a media player, a digital camera, etc., or in a vehicle-mounted device such as a navigation device, a black box, a vehicle-mounted electronic device, etc. Alternatively, the storage system 10 may be included in a mobile system such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet personal computer (tablet PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device.

[0027] like Figure 1 As shown, the storage system 10 includes a host device 100 and a storage device 200 .

[0028] The host device 100 may control the overall operation of the memory system 10 .

[0029] The host device 100 can communicate with the storage device 200 through various interfaces. For example, the host device 100 can communicate with the storage device 200 through various interfaces such as universal serial bus (USB), multimedia card (MMC), PCI Express (PCI-E), AT attachment (ATA), serial AT attachment (SATA), parallel AT attachment (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), enhanced small disk interface (ESDI), integrated drive electronics (IDE), non-volatile memory express (NVMe), etc. In an embodiment, when the host device 100 uses NVMe, the storage device 200 can use the asynchronous event request (AER) defined by the NVMe specification. The storage device 200 can make a request to the host device 100 by using the asynchronous event request (AER). However, even when the predetermined interface method is not NVMe, the storage device 200 can make a request using a method corresponding to the asynchronous event request (AER). Hereinafter, as an example, it is assumed that the storage device 200 uses the asynchronous event request (AER) specified in the NVMe specification.

[0030] The host device 100 may include a host controller 110 , a host memory 120 , and an interface circuit 130 .

[0031] The host controller 110 may control operations (eg, calculation, logic, control, input / output, etc.) of the host device 100. For example, the host controller 110 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, or an application processor (AP).

[0032] In an embodiment, the host device 100 may provide a request signal REQ and a logical block address LBA to the storage device 200. For example, the request signal REQ may include an eye opening monitor (EOM) acquisition signal for obtaining an EOM result value of the storage device 200 and / or a control signal for controlling the storage device 200 based on the EOM result value. In an embodiment, the EOM acquisition signal may be an asynchronous event reporting (AER) signal. In addition, the host device 100 may exchange data DATA with a plurality of storage devices 200.

[0033] The host memory 120 may store commands and data executed and processed by the host controller 110. For example, the operating system executed by the host controller 110 may include a file system for file management and a device driver for controlling peripheral devices including the storage device 200 at an operating system layer.

[0034] In an embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. In an embodiment, the host controller 110 and the host memory 120 may be integrated on the same semiconductor chip. For example, the host controller 110 may be one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory provided in the application processor, or may be a non-volatile memory or storage module provided outside the application processor.

[0035] The host device 100 may communicate with the memory device 200 through the interface circuit 130. Specifically, the interface circuit 130 may receive the EOM result value of the memory device 200 as a response RES to the request signal REQ (or the EOM acquisition signal included in the request signal REQ) from the memory device 200. In addition, the interface circuit 130 may receive a control signal generated by the host controller 110, and may transmit the control signal to the memory device 200.

[0036] The storage device 200 may be accessed by the host device 100. The storage device 200 may store data DATA received from the host device 100, or process data DATA in response to a request signal REQ from the host device 100. For example, the storage device 200 may be implemented as a solid state drive (SSD), a smart SSD, an embedded multimedia card (eMMC), an embedded universal flash storage (UFS) memory device, a UFS memory card, a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), an extreme digital (xD), a memory stick, or the like.

[0037] The memory device 200 may include a host interface 210 , a memory controller 250 , a buffer memory 230 , a memory interface 270 , and a nonvolatile memory device 290 .

[0038] The host interface 210 may send and receive data packets to and from the host device 100. The data packets sent from the host device 100 to the host interface 210 may include commands, data to be written in the non-volatile memory device 290, and the like. The data packets sent from the host interface 210 to the host device 100 may include a response RES to the command and / or data DATA read from the non-volatile memory device 290. In response to the EOM acquisition signal received from the host device 100, the host interface 210 may send an EOM result and / or an eye diagram to the host device 100 as a response RES. The eye diagram may be a diagram in which an input signal is divided into unit intervals and the divided segments are superimposed on each other and displayed. For example, the eye diagram may be a graph of a signal in which the x-axis is time and the y-axis is a measured voltage. In an embodiment, the host interface 210 may send the EOM result and / or the eye diagram to the host device 100 in an AER method.

[0039] In an embodiment, the interface circuit 130 and the host interface 210 may support multiple lanes, and each lane may be implemented as a differential pair. For example, the interface circuit 130 and the host interface 210 may include at least one receiving channel and at least one transmitting channel. The number of transmitting channels and receiving channels included in the interface circuit 130 and the host interface 210 may be predetermined. For example, the storage device 200 may send data to the host device 100 through the transmitting channel, while receiving data from the host device 100 through the receiving channel. In addition, control data (such as commands from the host device 100 to the storage device 200) and user data to be stored in the non-volatile storage device 290 of the storage device 200 or to be read from the non-volatile storage device 290 by the host device 100 may be sent through (one or more) the same channel.

[0040] In an embodiment, the host interface 210 may include an EOM unit 211 and an eye pattern generation (EGU) unit 213 .

[0041] The EOM unit 211 may measure signal distortion due to a channel through which data DATA is transmitted.

[0042] In more detail, the EOM unit 211 may perform an EOM operation on a signal provided from the host device 100. The EOM operation may be an operation of measuring the quality of a signal received from the host device 100 under a specific offset condition. For example, a signal transmitted from the host device 100 may be attenuated under the influence of a channel, and the host interface 210 may receive the attenuated signal. For example, in a signal transmitted from the host device 100, a high frequency component may have a greater degree of attenuation than a low frequency component due to the influence of a channel. The EOM unit 211 may generate an EOM result value indicating an attenuation level of the signal.

[0043] In an embodiment, when the memory device 200 is powered on, the EOM unit 211 may perform an EOM operation. That is, the EOM unit 211 may perform an EOM operation without receiving a separate command to perform the EOM operation.

[0044] In an embodiment, when the attenuation level of the signal is a predetermined threshold value or more based on the EOM result value, the EOM unit 211 may transmit the EOM result value to the host device 100 .

[0045] The EGU unit 213 may generate an eye diagram based on the EOM result value generated by the EOM unit 211. Figure 2 An example structure of the host interface 210 is described.

[0046] The memory controller 250 may control the overall operation of the memory device 200. In an embodiment, the memory controller 250 may include a central processing unit (CPU), a controller, an application-specific integrated circuit (ASIC), and the like.

[0047] For example, the memory controller 250 may provide a signal (eg, Figure 6 For example, the memory controller 250 may provide a signal to the nonvolatile memory device 290 so as to write data to the nonvolatile memory device 290 or read data from the nonvolatile memory device 290. In addition, the memory controller 250 and the nonvolatile memory device 290 may exchange data DATA.

[0048] In an embodiment, the memory controller 250 may use the buffer memory 230 and / or the nonvolatile memory device 290 as an operation memory of the memory controller 250 .

[0049] The buffer memory 230 may store commands and data executed and processed by the memory controller 250. The buffer memory 230 may temporarily store data stored or to be stored in the nonvolatile memory device 290. In an embodiment, the buffer memory 230 may temporarily store an EOM result value measured by the host interface 210.

[0050] The buffer memory 230 may be implemented as a volatile memory such as a dynamic random access memory (DRAM), a static RAM (SRAM), etc. However, it is not limited thereto, and the buffer memory 230 may be implemented as a resistive non-volatile memory such as a magnetic RAM (MRAM), a phase change RAM (PRAM), a resistive RAM (ReRAM), etc., and various types of non-volatile memories such as a flash memory, a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a ferroelectric random access memory (FRAM), etc.

[0051] In an embodiment, the buffer memory 230 may store code data required for initial booting of the memory device 200. The buffer memory 230 may buffer a request signal REQ, data DATA, a command, etc. received from the host device 100. The signals buffered in the buffer memory 230 may be transmitted to the nonvolatile memory device 290 through the memory interface 270 and used in the nonvolatile memory device 290. For example, the data DATA buffered in the buffer memory 230 may be programmed in the nonvolatile memory device 290.

[0052] The storage controller 250 and the non-volatile storage device 290 may be connected to each other through a storage interface 270. The storage interface 270 may be implemented to comply with a standard protocol, such as trigger or open NAND flash interface (ONFI). In an embodiment, the storage interface 270 may be used to send command and control signals to the non-volatile storage device 290 together with data to be written in the non-volatile storage device 290, or may be used to receive data read from the non-volatile storage device 290. The storage interface 270 may be implemented to comply with a standard protocol, such as trigger or ONFI.

[0053] The nonvolatile memory device 290 may include a plurality of memory cells. Each of the plurality of memory cells may include a V-NAND flash memory in a 2D structure or a 3D structure, but may include another type of nonvolatile memory such as PRAM and / or RRAM. Magnetic RAM (MRAM), spin transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive memory (e.g., resistive RAM), and various other types of memory may be applied as memory cells included in the nonvolatile memory device 290.

[0054] Figure 2 is a diagram illustrating a host interface according to an example embodiment. Figure 3 is a diagram for explaining the operation of a clock data recovery (CDR) block according to example embodiments. Figure 4 is a diagram for explaining the EOM operation.

[0055] like Figure 2 As shown, the host interface 210 may include an equalizer 2800 including an analog front end (AFE), a CDR block 2600, a decoder 2500, a descrambler 2400, a symbol remover 2300, a channel merger 2200, a symbol converter 2100, an AFE controller 2700 and a special function register (SFR) 2900.

[0056] The equalizer 2800 may receive a differential input signal pair DIN_T and DIN_C as data DATA from the host device 100, and may perform equalization to output a serial bit SB. The equalizer 2800 may adjust the gain of the input signal and output a serial bit SB of the equalized input signal. The equalizer 2800 may compensate for signal distortion by considering the characteristics of the transmission channel, and may determine a compensation level of signal distortion according to an equalization coefficient.

[0057] In an embodiment, the equalizer 2800 may include a continuous time linear equalizer (CTLE) and a decision feedback equalizer (DFE). The CTLE may uniformly equalize all frequency components of the data signal by amplifying the amplitude of the high frequency component of the data signal in consideration of the influence of the channel. For example, the CTLE may include a sampling and holding circuit, sample the data signal by using the sampling and holding circuit, and perform an equalization operation by using the sampling result. The DFE may perform an equalization operation based on decision feedback on the sampled data.

[0058] The CDR block 2600 may receive the serial bits SB equalized by the equalizer 2800 and may restore data using the serial bits SB. Specifically, the CDR block 2600 may perform clock data recovery (CDR) and data deserialization to output an N-bit signal (N is a natural number).

[0059] In an embodiment, the CDR block 2600 may include: an EOM unit 2630 configured to perform an EOM operation to measure the signal quality of a communication channel with respect to the host device 100; and an EGU unit 2610 configured to generate an eye diagram. The CDR block 2600 may generate an EOM result value EOM_RES. The EOM result value EOM_RES may include at least one of an error count signal EC and an eye diagram. In an embodiment, the EOM result value EOM_RES may also include a sampling count signal SC.

[0060] The EOM unit 2630 may perform an EOM operation on the serial bits SB received from the equalizer 2800 .

[0061] In an embodiment, the EOM operation of the EOM unit 2630 may be performed by using the SFR 2900 , but the present disclosure is not limited thereto and the EOM operation may be performed based on data stored in the buffer memory 230 .

[0062] The SFR 2900 may store data to be used in the EOM operation of the EOM unit 2630. For example, the SFR 2900 may store a value related to an offset set during the EOM operation.

[0063] Reference together Figure 3 , the EOM unit 2630 can be based on the comparison Figure 3 The main path signal MS generated by the main path indicated by the solid line and the main path signal MS based on Figure 3 The EOM operation is performed based on the EOM path signal ES generated by the EOM path 310 indicated by the dotted line in FIG.

[0064] A clock recovery circuit (CRC) 3003, a slicer 3005, and a deserializer 3007 may be positioned on the primary path.

[0065] The clock recovery circuit 3003 can recover the clock based on the serial bit SB and generate a recovered clock RCK.

[0066] The limiter 3005 can extract the data of the serial bit SB based on the recovered clock RCK and the reference voltage YR. That is, the limiter 3005 can use the recovered clock RCK as a reference clock. The limiter 3005 can transmit the extracted data to the deserializer 3007. Figure 4 Describe the reference voltage YR.

[0067] The deserializer 3007 may generate a main path signal MS by deserializing the data received from the limiter 3005. The deserializer 3007 may transmit the main path signal MS to the comparator 3017.

[0068] The multiplier 3011 , the limiter 3013 , the deserializer 3015 , and the comparator 3017 may be positioned on the EOM path 310 .

[0069] The multiplier 3011 may receive the recovered clock RCK from the clock recovery circuit 3003 and generate an EOM clock dXRCK reflecting a specific offset clock value dX in the recovered clock RCK. Figure 2 The SFR 2900 in receives a specific offset clock value dX.

[0070] The limiter 3013 may receive the EOM clock dXRCK from the multiplier 3011, and may extract the data of the serial bit SB based on the received EOM clock dXRCK and the specific offset value dY. The limiter 3013 may transmit the extracted data to the deserializer 3015. In an embodiment, the limiter 3013 may receive the specific offset value dY from the SFR 2900.

[0071] The deserializer 3015 may generate an EOM path signal ES by deserializing the data received from the slicer 3013 . The deserializer 3015 may transmit the EOM path signal ES to the comparator 3017 .

[0072] Reference together Figure 4 , the main path signal MS may correspond to Figure 4 The reference conditions XR and YR extracted data, and the EOM path signal ES may correspond to the data based on Figure 4 The offset values ​​dX and dY of the extracted data.

[0073] like Figure 4 As shown, the eye diagram is used to represent the signal based on the time offset value on the X-axis and the voltage offset value on the Y-axis. Specifically, Figure 4 (a) shows an eye diagram of an input signal before being equalized by the equalizer 2800, and Figure 4 (b) is a diagram showing an input signal after being equalized by the equalizer 2800. As described above, the eye diagram refers to a diagram obtained by dividing an input signal into unit intervals and superimposing voltage values ​​of the divided segments.

[0074] exist Figure 4, it is shown that the offset value dX is a time offset value, and the offset value dY is a voltage offset value, but the present disclosure is not limited thereto, and the offset clock value dX may be, for example, a phase offset value.

[0075] The time offset value or phase offset value to be used in performing the EOM operation can be provided from the host device 100 to the storage device 200 through the timing offset field and the timing step field. When various time offset values ​​within a predetermined range and various voltage offset values ​​within a predetermined range are provided to the equalizer 2800, changes in the input signal can be measured.

[0076] In the signal Figure 4 In the case of the eye diagram shown in (a), it may be difficult to determine the baseline used as a standard for distinguishing between 0 and 1, and the size of the signal also varies. Therefore, it may be difficult to determine the value of the data received from the equalizer 2800. In this case, the equalizer 2800 can compensate for the signal distortion caused by the transmission channel by performing an equalization operation on the input signal to facilitate determination of the data value.

[0077] In the signal Figure 4 In the case of the eye diagram shown in (b), the upper division and the lower division are clear based on the reference conditions XR and YR, and therefore, it may be easy to distinguish data between 0 and 1. That is, the equalizer 2800 can sample the input signal and adjust the gain of the input signal so that the data value can be easily determined. At this time, the equalizer 2800 can control the gain applied to the input signal based on the control of the AFE controller 2700.

[0078] The input signal equalized by the equalizer 2800 may represent each of the offset value dX and the offset value dY, not in the form of Figure 4 , is not represented by a single value in the embodiment shown in , but is represented by two fields, namely, a reference value (eg, a reference phase or a reference voltage) and an offset value relative to the reference value (eg, an offset phase value or an offset voltage value).

[0079] The comparator 3017 can compare the main path signal MS and the EOM path signal ES. In an embodiment, the offset value dX input to the multiplier 3011 on the EOM path 310 and the offset value dY input to the limiter 3013 can vary within a predetermined range. The comparator 3017 can compare each of the EOM path signals ES that vary with the offset values ​​dX and dY with the main path signal MS.

[0080] When there is a difference between the main path signal MS and the EOM path signal ES (in other words, the main path signal MS does not match the EOM path signal ES), the comparator 3017 may determine that there is an error and determine an error count based on the offset values ​​dX and dY. The comparator 3017 may generate an error count signal EC based on the error count determined based on the offset values ​​dX and dY.

[0081] In addition, whenever sampling (eg, comparison of the EOM path signal ES and the main path signal MS) is performed, the comparator 3017 may output a sampling count signal SC.

[0082] The comparator 3017 may transmit the generated error count signal EC and the sampling count signal SC to the EGU unit 2610 .

[0083] The EGU unit 2610 may generate an eye diagram based on the error count signal EC and the sampling count signal SC. For example, the X-axis represents an eye diagram of an offset value X and the Y-axis represents a voltage value Y. The EGU unit 2610 may generate an EOM result value EOM_RES based on the error count signal EC and the sampling count signal SC received from the comparator 3017. The EOM result value EOM_RES may include the error count signal EC, the sampling count signal SC, and the eye diagram.

[0084] In an embodiment, the offset value dX, the offset value dY, the error count value according to the error count signal EC, and the sampling count information according to the sampling count signal SC, etc. may be stored in the SFR 2900, but the present disclosure is not limited thereto, and such information may be stored in a buffer memory (e.g., Figure 1 230).

[0085] The AFE controller 2700 may receive an EOM result value EOM_RES from the EGU unit 2610. The EOM result value EOM_RES may include an error count signal EC, a sampling count signal SC, and an eye pattern.

[0086] The AFE controller 2700 may generate an AFE control signal CTRL_AFE based on the received EOM result value EOM_RES. The AFE control signal CTRL_AFE may be a signal for changing a physical (PHY) setting of the equalizer 2800. For example, the PHY setting may include a gain of at least one of the CTLE and the DFE. When the CTLE and the DFE increase the amplitude of the input voltage required for the input signal, the error may be reduced, and the error count in the error count signal EC may be reduced.

[0087] However, the present disclosure is not limited thereto, and the AFE controller 2700 may generate the AFE control signal CTRL_AFE for controlling various elements of the host interface 210 so that the error count in the error count signal EC may be a predetermined threshold or less.

[0088] Return to reference Figure 2 , the decoder 2500 may decode the N-bit signal from the CDR block 2600 into an M-bit signal (M is a natural number less than N) and a distinguishing signal DS. The decoder 2500 may output the M-bit signal and the distinguishing signal DS to the descrambler 2400. In an embodiment, the N-bit signal may be a 10-bit signal, and the M-bit signal may be an 8-bit signal, but the present disclosure is not limited thereto.

[0089] The N-bit signal received from the CDR block 2600 may be a data signal D or a control signal K. When the N-bit signal is a data symbol, the decoder 2500 may output the data signal D as a distinguishing signal DS. When the N-bit signal is a control symbol, the decoder 2500 may output the control signal K as a distinguishing signal DS.

[0090] The descrambler 2400 may perform descrambling on the input M-bit signal. The descrambler 2400 may output the descrambled signal to the symbol remover 2300.

[0091] The symbol remover 2300 may remove a skip symbol such as a flag from an input M-bit signal.

[0092] The channel merger 2200 may merge the signals input to each channel and may provide the merged signal to the symbol converter 2100 .

[0093] The symbol converter 2100 may convert the symbol. The symbol converter 2100 may output the converted symbol to the memory controller 250.

[0094] Figure 5 is a diagram illustrating a memory controller and a memory device according to example embodiments.

[0095] The memory device 5300 may include first to eighth pins P11 to P18 , a memory interface circuit 5310 , a control logic 5350 , and a memory cell array 5370 .

[0096] The memory interface circuit 5310 may receive a chip enable signal nCE from the memory controller 5100 through the first pin P11. The memory interface circuit 5310 may transmit and receive signals with the memory controller 5100 through the second pin P12 to the eighth pin P18 according to the chip enable signal nCE.

[0097] The memory interface circuit 5310 may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 5100 through the second pin P12 to the fourth pin P14. The memory interface circuit 5310 may receive a data signal DQ from the memory controller 5100 through the seventh pin P17, or may send the data signal DQ to the memory controller 5100. The command CMD, the address ADDR, and the data DATA may be transmitted through the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals.

[0098] The memory interface circuit 5310 can obtain a command CMD from a data signal DQ received in an enable period (e.g., a high level state) of a command latch enable signal CLE based on a switching timing of a write enable signal nWE. The memory interface circuit 5310 can obtain an address ADDR from a data signal DQ received in an enable period (e.g., a high level state) of an address latch enable signal ALE based on a switching timing of a write enable signal nWE.

[0099] The memory interface circuit 5310 may receive a read enable signal nRE from the memory controller 5100 through a fifth pin P15. The memory interface circuit 5310 may receive a data strobe signal DQS from the memory controller 5100 through a sixth pin P16, or may transmit the data strobe signal DQS to the memory controller 5100 through the sixth pin P16.

[0100] In the operation of the memory device 5300 outputting the data DATA, the memory interface circuit 5310 may receive the switched read enable signal nRE through the fifth pin P15 before outputting the data DATA. The memory interface circuit 5310 may generate a data strobe signal DQS switched based on the switching of the read enable signal nRE. The memory interface circuit 5310 may send a data signal DQ including the data DATA based on the switching timing of the data strobe signal DQS. Therefore, the data DATA may be sent to the memory controller 5100 by aligning with the switching timing of the data strobe signal DQS.

[0101] In an operation in which the memory device 5300 inputs data DATA, when receiving a data signal DQ including the data DATA from the memory controller 5100, the memory interface circuit 5310 may receive a switched data strobe signal DQS together with the data DATA from the memory controller 5100. The memory interface circuit 5310 may obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0102] The memory interface circuit 5310 may send a ready / busy output signal nR / B to the memory controller 5100 through the eighth pin P18. The memory interface circuit 5310 may send the state information of the memory device 5300 to the memory controller 5100 through the ready / busy output signal nR / B. When the memory device 5300 is in a busy state (e.g., when an internal operation of the memory device 5300 is being performed), the memory interface circuit 5310 may send the ready / busy output signal nR / B indicating the busy state to the memory controller 5100. When the memory device 5300 is in a ready state (e.g., the internal operation of the memory device 5300 is not being performed or has been completed), the memory interface circuit 5310 may send the ready / busy output signal nR / B indicating the ready state to the memory controller 5100.

[0103] The memory interface circuit 5310 may include an EOM unit 5311. The EOM unit 5311 may perform an EOM operation on data DATA received from the memory controller 5100 through the seventh pin P17. The EOM operation may be an operation of measuring the quality of a signal received from the memory controller 5100 under a specific offset condition.

[0104] In an embodiment, when the memory device 5300 is powered on, the EOM unit 5311 may perform an EOM operation. In addition, when the error count included in the EOM result value obtained by the EOM operation is a predetermined threshold or more, the EOM unit 5311 may transmit the EOM result value to the memory controller 5100 in an AER method. In an embodiment, the memory interface circuit 5310 may change the PHY setting based on the EOM result value.

[0105] The control logic 5350 may generally control various operations of the memory device 5300. The control logic 5350 may receive a command / address CMD / ADDR obtained from the memory interface circuit 5310. The control logic 5350 may generate a control signal for controlling other components of the memory device 5300 according to the received command / address CMD / ADDR. For example, the control logic 5350 may generate various control signals for programming data DATA in the memory cell array 5370 or reading data DATA from the memory cell array 5370.

[0106] The memory cell array 5370 may store data DATA obtained from the memory interface circuit 5310 under the control of the control logic 5350. The memory cell array 5370 may output the stored data DATA to the memory interface circuit 5310 under the control of the control logic 5350.

[0107] The memory cell array 5370 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, description is made assuming that the memory cells are NAND flash memory cells, but the present disclosure is not limited thereto, and the memory cells may be any other type of memory cells, such as, but not limited to, resistive random access memory (RRAM) cells, ferroelectric random access memory (FRAM) cells, phase change random access memory (PRAM) cells, thyristor random access memory (TRAM) cells, and magnetic random access memory (MRAM) cells.

[0108] The memory controller 5100 may include first to eighth pins P21 to P28 and a controller interface circuit 5110. The first to eighth pins P21 to P28 may correspond to first to eighth pins P11 to P18 of the memory device 5300. The memory controller 5100 and the memory device 5300 may transmit and receive a command CMD, an address ADDR, and data DATA through the controller interface circuit 5110 and the memory interface 5310.

[0109] The controller interface circuit 5110 may transmit the chip enable signal nCE to the memory device 5300 through the first pin P21. The controller interface circuit 5110 may transmit and receive a signal selected by the chip enable signal nCE to and from the memory device 5300 through the second to eighth pins P22 to P28.

[0110] The controller interface circuit 5110 may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 5300 through the second pin P22 to the fourth pin P24. The controller interface circuit 5110 may transmit the data signal DQ to the memory device 5300 through the seventh pin P27, or may receive the data signal DQ from the memory device 5300.

[0111] The controller interface circuit 5110 may transmit a data signal DQ including a command CMD or an address ADDR together with the switched write enable signal nWE to the memory device 5300. The controller interface circuit 5110 may transmit the data signal DQ including the command CMD to the memory device 5300 based on the command latch enable signal CLE having an enable state being transmitted, and may transmit the data signal DQ including the address ADDR to the memory device 5300 based on the address latch enable signal ALE having an enable state being transmitted.

[0112] The controller interface circuit 5110 may transmit the read enable signal nRE to the memory device 5300 through the fifth pin P25. The controller interface circuit 5110 may receive the data strobe signal DQS from the memory device 5300 through the sixth pin P26, or may transmit the data strobe signal DQS to the memory device 5300.

[0113] In the operation of the memory device 5300 outputting the data DATA, the controller interface circuit 5110 may generate a switched read enable signal nRE, and may send the read enable signal nRE to the memory device 5300. For example, the controller interface circuit 5110 may generate a read enable signal nRE that changes from a fixed state (e.g., a high level or a low level) to a switched state before the data DATA is output. Therefore, a data strobe signal DQS switched based on the read enable signal nRE may be generated in the memory device 5300. The controller interface circuit 5110 may receive a data signal DQ including the data DATA together with the switched data strobe signal DQS from the memory device 5300. The controller interface circuit 5110 may obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0114] In the operation of inputting data DATA to the memory device 5300, the controller interface circuit 5110 may generate a switched data strobe signal DQS. For example, the controller interface circuit 5110 may generate a data strobe signal DQS that changes from a fixed state (e.g., a high level or a low level) to a switched state before transmitting the data DATA. The controller interface circuit 5110 may transmit a data signal DQ including data DATA to the memory device 5300 based on the switching timing of the data strobe signal DQS.

[0115] The controller interface circuit 5110 may receive the ready / busy output signal nR / B from the memory device 5300 through the eighth pin P28. The controller interface circuit 5110 may determine the state information of the memory device 5300 based on the ready / busy output signal nR / B.

[0116] Figure 6 It is shown Figure 5 A block diagram of a memory device.

[0117] refer to Figure 6 , the memory device 600 may include a control logic 610, a memory cell array 620, a page buffer unit 650, a voltage generator 630, and a row decoder 640. The memory device 600 may correspond to Figure 5 Memory device 5300.

[0118] The control logic 610 may generally control various operations of the memory device 600. The control logic 610 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit 5310. For example, the control logic 610 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0119] The memory cell array 620 may include a plurality of memory blocks BLK1 to BLKn (n is a positive integer), and each of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 620 may be connected to the page buffer unit 650 through a plurality of bit lines BL, and may be connected to the row decoder 640 through word lines WL, string selection lines SSL, and ground selection lines GSL.

[0120] In an embodiment, the memory cell array 620 may include a three-dimensional (3D) memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines vertically stacked on a substrate, respectively. In an embodiment, the memory cell array 620 may include a two-dimensional (2D) memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along a row direction and a column direction.

[0121] The page buffer unit 650 may include a plurality of page buffers PB1 to PBn (n is an integer of 3 or more), and the plurality of page buffers PB1 to PBn may be connected to the memory cells through a plurality of bit lines BL, respectively. The page buffer unit 650 may select at least one of the plurality of bit lines BL in response to the column address Y-ADDR. Depending on the operation mode, the page buffer unit 650 may operate as a write driver or a sense amplifier. For example, during a programming operation, the page buffer unit 650 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer unit 650 may detect the data stored in the corresponding memory cell by detecting the current or voltage of the selected bit line.

[0122] The voltage generator 630 may generate various types of voltages for performing program operations, read operations, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 630 may generate a word line voltage VWL such as a program voltage, a read voltage, a program verification voltage, an erase voltage, etc.

[0123] The row decoder 640 may select one of the plurality of word lines WL and one of the plurality of string selection lines SSL in response to the row address X-ADDR. For example, during a programming operation, the row decoder 640 may apply a program voltage and a program verification voltage to the selected word line, and during a read operation, may apply a read voltage to the selected word line.

[0124] Figure 7 is a diagram illustrating a storage system according to example embodiments.

[0125] In step S701 , the storage device 200 may be powered on.

[0126] For example, when the memory device 200 is connected to the host device 100 , or when a power supply voltage cut off from the host device 100 is supplied to the memory device 200 , the memory device 200 may be powered on.

[0127] In step S703 , the storage device 200 may perform an EOM operation.

[0128] When the memory device 200 is powered on, the memory device 200 may perform an EOM operation on a signal received from the host device 100. The memory device 200 may temporarily store an EOM result value obtained by performing the EOM operation in the buffer memory 230. In an embodiment, when an error count value in the EOM result value has a value of a predetermined threshold or more, the memory device 200 may store the EOM result value in the buffer memory 230.

[0129] In step S705 , the host device 100 may transmit an asynchronous event request (AER) command AER_CMD to the storage device 200 .

[0130] The asynchronous event request command AER_CMD may be a command for receiving an asynchronous event request (AER). In an embodiment, the asynchronous event request command AER_CMD may have a request for a device (or a device request). For example, the AER command may include a request for the device to perform an EOM operation.

[0131] In an embodiment, the host device 100 may issue a predetermined number of asynchronous event request commands AER_CMD with respect to the storage device 200. The host device 100 may perform another operation in a state where a response with respect to the asynchronous event request command AER_CMD has not been received.

[0132] In step S707 , the storage device 200 may send a command completion signal to the host device 100 .

[0133] In more detail, at step S705, the storage device 200 may receive an AER command. The storage device 200 may read a device request corresponding to the AER command and generate a signal corresponding to the device request. In an embodiment, since the storage device 200 has obtained an EOM result value EOM_RES by performing an EOM operation at step S703, the storage device 200 may determine that the device request received from the host device 100 has been completed. Therefore, the storage device 200 may generate a command completion signal indicating that the command corresponding to the received device request has been completed. The storage device 200 may send the generated command completion signal to the host device 100.

[0134] Thereafter, the storage device 200 may transmit the EOM result value EOM_RES to the host device 100 in step S709 .

[0135] In more detail, the storage device 200 may send an asynchronous event request (AER) as an EOM result value EOM_RES to the host device 100. The asynchronous event request (AER) may correspond one-to-one to the previously received asynchronous event request command AER_CMD. That is, the asynchronous event request (AER) of the storage device 200 may be a response corresponding to the asynchronous event request command AER_CMD.

[0136] In an embodiment, when the error count in the error count signal EC exceeds a predetermined threshold, the memory device 200 may transmit an EOM result value EOM_RES to the host device 100 .

[0137] Although in Figure 7 Although not shown in the figure, the storage device 200 may generate an AFE control signal based on the EOM result value EOM_RES. Therefore, the storage device 200 may control the equalizer 2800 so that the error count has a value of a predetermined threshold or less. The present disclosure is not limited thereto, and various commands may be generated based on the EOM result value EOM_RES received by the host device 100 to control the host interface 210 in the storage device 200.

[0138] Figure 8 and Fig. 9 is a flowchart for illustrating a process of performing an EOM operation of a storage device according to an example embodiment. In particular, Figure 8 and Fig. 9 It is used to illustrate Figure 7 Flowchart of step S703 for performing the EOM operation.

[0139] First, in step S901 , the storage device 200 may set (or predetermine) an initial offset value.

[0140] In an embodiment, the initial offset value may be stored in SFR 2900. The initial offset value may include an offset value dX (eg, an offset clock value or an offset phase value) provided to multiplier 3011 and an offset value dY (eg, an offset voltage value) provided to limiter 3013.

[0141] In step S903 , the storage device 200 may perform the EOM operation by using a predetermined offset value that varies within a predetermined range with respect to a set initial offset value.

[0142] The memory device 200 may generate the EOM path signal ES by using a predetermined offset value. Thereafter, the memory device 200 may compare the EOM path signal ES with the main path signal MS to generate a sampling count signal SC and an error count signal EC.

[0143] In step S905 , the storage device 200 may determine whether the EOM operation is performed on all offset values ​​within a predetermined range.

[0144] In more detail, the storage device 200 may determine whether the EOM operation is performed on all offset values ​​dX and dY within a predetermined range.

[0145] In step S906, when the EOM operation is not performed on all offset values, the storage device 200 may change the offset value to another offset value within a predetermined range. Subsequently, the storage device 200 may proceed to step S903 to perform the EOM operation by using the changed offset value, and repeat step S905 to determine whether the EOM operation is performed on all offset values.

[0146] In step S907 , when the EOM operation is performed on all offset values, the memory device 200 may generate an EOM result value EOM_RES.

[0147] In more detail, the EOM result value EOM_RES may include an error count signal EC, a sampling count signal SC, and an eye diagram. The eye diagram may be obtained by dividing the input signal into unit intervals and displaying the divided segments by superimposing the value (e.g., voltage value) of the input signal. That is, the eye diagram may indicate the amplitude of the signal according to the offset value dX and the offset value dY.

[0148] In step S909 , the memory device 200 may determine whether the error count of the error count signal EC is a predetermined threshold or more.

[0149] In step S911 , when the error count of the error count signal EC is a predetermined threshold or more, the memory device 200 may transmit an EOM result value.

[0150] In more detail, when the error count of the error count EC is a predetermined threshold or more, the memory device 200 may transmit the EOM result value EOM_RES as an asynchronous event request (AER) to the host device 100. This may correspond to Figure 7 Step S709 for sending the EOM result value EOM_RES.

[0151] Thereafter, in step S913 , the memory device 200 may generate an AFE control signal CTRL_AFE.

[0152] In more detail, the memory device 200 may generate an AFE control signal CTRL_AFE based on the EOM result value EOM_RES. The AFE control signal CTRL_AFE may be a signal for changing a PHY setting of the equalizer 2800. In an embodiment, the PHY setting may include a gain of at least one of CTLE and DFE.

[0153] Fig. 9 The step S913 of generating the AFE control signal CTRL_AFE is described in more detail.

[0154] First, in step S9131, the storage device 200 may change the PHY setting based on the EOM result.

[0155] In an embodiment, the PHY settings to be changed according to the EOM result may be predetermined. In an embodiment, the gain increase of the CTLE and / or DFE may be controlled so that the error count may be reduced.

[0156] In step S9133, the storage device 200 may perform an EOM operation based on the changed PHY setting.

[0157] In an embodiment, the memory device 200 may perform an EOM operation based on an increased gain of the CTLE and / or the DFE.

[0158] In step S9135 , the storage device 200 may determine whether the error count is a predetermined threshold or less.

[0159] In more detail, the memory device 200 may compare the main path signal MS and the EOM path signal ES performed based on the changed PHY setting to generate the sampling count signal SC and the error count signal EC. The memory device 200 may determine whether the error count in the error count signal EC is less than or equal to a predetermined threshold.

[0160] When the error count exceeds a predetermined threshold, the storage device 200 may perform step S9131 and subsequent steps again.

[0161] In step S9137 , when the error count is less than or equal to the predetermined threshold, the memory device 200 may generate an AFE control signal CTRL_AFE based on the changed PHY setting.

[0162] In more detail, when the error count is a predetermined threshold or less, the memory device 200 may generate an AFE control signal CTRL_AFE to control the equalizer 2800 to have the PHY setting set in step S9131. Although the above embodiment describes changing the PHY setting of the equalizer 2800, the present disclosure is not limited thereto, and the memory device 200 may generate an AFE control signal CTRL_AFE to control various elements of the host interface 210 so that the error count in the error count signal EC may be a predetermined threshold or less.

[0163] Meanwhile, in an embodiment, the step S913 in which the memory device 200 generates the AFE control signal CTRL_AFE may be omitted. In this case, the memory device 200 may change the PHY setting of the memory device 200 based on a command for controlling the host interface 210 in the memory device 200 generated by the host device 100 in response to receiving the EOM result value EOM_RES by the host device 100.

[0164] Fig.10 is a diagram illustrating a storage system according to example embodiments.

[0165] refer to Figures 1 to 9 The described storage system 10 may be a system compliant with the Universal Flash Storage (UFS) standard promulgated by the Joint Electron Device Engineering Council (JEDEC).

[0166] refer to Fig.10 The UFS system 20 may include a UFS host device 1000 , a UFS memory device 1050 , and a UFS interface 400 .

[0167] The UFS host device 1000 and the UFS memory device 1050 may be interconnected through a UFS interface 400. In an embodiment, the UFS host device 1000 may be implemented as a part of an application processor.

[0168] The UFS host device 1000 may include a UFS host controller 1001 , an application 1003 , a UFS driver 1005 , a host memory 1007 , and a UIC (UFS Interconnect) layer 1009 .

[0169] The UFS memory device 1050 may include a UFS device controller 1051 , a nonvolatile memory device 1053 , a storage interface 1055 , a device memory 1057 , a UIC layer 1059 , and a regulator 1061 .

[0170] The nonvolatile memory device 1053 may be configured as a plurality of memory cells 1062. The memory cell 1062 may include a V-NAND flash memory in a 2D structure or a 3D structure, but the present disclosure is not limited thereto and the memory cell 1062 may include another type of nonvolatile memory such as PRAM and / or RRAM.

[0171] The UFS device controller 1051 and the nonvolatile memory device 1053 may be connected to each other through a storage interface 1055. The storage interface 1055 may be implemented to comply with a standard protocol such as trigger or ONFI.

[0172] The application 1003 may be a program that communicates with the UFS memory device 1050 to use the functions of the UFS memory device 1050. The application 1003 may send an input-output request (IOR) to the UFS driver 1005 for input / output with respect to the UFS memory device 1050. The input-output request (IOR) may include a read request, a write request, an erase request, etc. of data, but the present disclosure is not limited thereto.

[0173] The UFS driver 1005 can manage the UFS host controller 1001 through the UFS host controller interface (HCI). The UFS driver 1005 can convert the input and output request generated by the application 1003 into a UFS command defined in the UFS standard, and can transmit the converted UFS command to the UFS host controller 1001. One input and output request can be converted into a plurality of UFS commands. The UFS command can be a command defined by the Small Computer System Interface (SCSI) standard, but can also be a command proprietary to the UFS standard.

[0174] The UFS host controller 1001 may transmit the UFS command converted by the UFS driver 1005 to the UIC layer 1059 of the UFS memory device 1050 through the UIC layer 1009 and the UFS interface 400. In this case, the UFS host register 111 of the UFS host controller 1001 may be used as a command queue (CQ).

[0175] The UIC layer 1009 of the UFS host device 1000 may include MIPI M-PHY and MIPI UniPro, and the UIC layer 1059 of the UFS memory device 1050 may also include MIPI M-PHY and MIPI UniPro.

[0176] The UFS interface 400 may include a line configured to transmit a reference clock REF_CLK, a line configured to transmit a hardware reset signal RESET_n regarding the UFS memory device 1050, a pair of lines configured to transmit a differential input signal pair DIN_T and DIN_C, and a pair of lines configured to transmit a differential output signal pair DOUT_T and DOUT_C.

[0177] The frequency value of the reference clock REF_CLK provided from the UFS host device 1000 to the UFS memory device 1050 may be one of four values ​​of 19.2Mhz, 26Mhz, 38.4Mhz, and 52MHz, but is not necessarily limited thereto. Even during operation, that is, even while data transmission and reception are performed between the UFS host device 1000 and the UFS memory device 1050, the UFS host device 1000 may change the frequency value of the reference clock REF_CLK.

[0178] The UFS memory device 1050 may generate clocks of various frequencies according to the reference clock REF_CLK provided from the UFS host device 1000 by using a phase-locked loop (PLL) or the like. In addition, the UFS host device 1000 may set a data rate value between the UFS host device 1000 and the UFS memory device 1050 by the frequency value of the reference clock REF_CLK. That is, the data rate value may be determined according to the frequency value of the reference clock REF_CLK.

[0179] The UFS interface 400 may support multiple channels, and each channel may be implemented as a differential pair. For example, the UFS interface 400 may include one or more receiving channels and one or more transmitting channels. Figure 1 In the embodiment, the paired lines configured to transmit the differential input signal pair DIN_T and DIN_C may constitute a receiving channel, and the paired lines configured to transmit the differential output signal pair DOUT_T and DOUT_C ​​may constitute a transmitting channel. Figure 1 One transmission channel and one reception channel are shown, but the number of transmission channels and reception channels may be modified according to the embodiment.

[0180] The receiving channel and the transmitting channel may transmit data in a serial communication method, and by using a structure that separates the receiving channel and the transmitting channel, communication in a full-duplex method between the UFS host device 1000 and the UFS memory device 1050 is possible. That is, the UFS memory device 1050 may transmit data to the UFS host device 1000 through the transmitting channel while receiving data from the UFS host device 1000 through the receiving channel. In addition, control data (such as a command from the UFS host device 1000 to the UFS memory device 1050) and user data to be stored in the non-volatile memory device 1053 of the UFS memory device 1050 or to be read from the non-volatile memory device 1053 by the UFS host device 1000 may be transmitted through the same channel. Therefore, in addition to one (more) pair of receiving channels and one (more) pair of transmitting channels, a separate channel for data transmission may not exist between the UFS host device 1000 and the UFS memory device 1050.

[0181] Fig.11 It shows that according to Fig.10 A diagram of an example of a storage system.

[0182] In more detail, Fig.11 It is a schematic diagram showing the Fig.10 Figure 1 shows an example of a storage system. Fig.11 , the storage system may include a UFS host device 1000 and a UFS memory device 1050. The UFS host device 1000 may include a UIC layer 1009, and the UIC layer 1009 may include an EOM unit 1011. The UFS memory device 1050 may include a UIC layer 1059.

[0183] The UIC layer 1009 of the UFS host device 1000 may perform an EOM operation. For example, the UIC layer 1009 of the UFS host device 1000 may perform an EOM operation on the differential output signal pair DOUT_T and DOUT_C ​​received from the UFS memory device 1050. In an embodiment, when the UFS host device 1000 is powered on, the EOM unit 1011 in the UIC layer 1009 may perform an EOM operation. Thereafter, when the error count in the error count signal EC is a predetermined threshold or greater, the UIC layer 1009 may store an EOM result value in a host memory (e.g., Fig.10 Thereafter, the UFS host device 1000 may send the EOM result value to the UFS memory device 1050. The UFS host device 1000 may change the PHY setting of the UFS host device 1000 based on the EOM result value.

[0184] Fig.12is a diagram illustrating a storage system according to example embodiments.

[0185] In more detail, Fig.12 It is a schematic diagram showing the Fig.10 Figure 1 shows an example of a storage system. Fig.12 , the storage system may include a UFS host device 1000 and a UFS memory device 1050. The UFS host device 1000 may include a UIC layer 1009, and the UIC layer 1009 may include an EOM unit 1011. The UFS memory device 1050 may include a UIC layer 1059, and the UIC layer 1059 may include an EOM unit 1063.

[0186] The UIC layer 1009 of the UFS host device 1000 may perform an EOM operation. For example, the UIC layer 1009 of the UFS host device 1000 may perform an EOM operation on the differential output signal pair DOUT_T and DOUT_C ​​received from the UFS memory device 1050. In an embodiment, when the UFS host device 1000 is powered on, the EOM unit 1101 in the UIC layer 1009 may perform an EOM operation. Thereafter, when the error count in the error count signal EC is a predetermined threshold or greater, the UIC layer 1009 may store an EOM result value in the host memory 1007 (refer to Fig.10 ). Thereafter, the UFS host device 1000 may transmit the EOM result value to the UFS memory device 1050. The UFS host device 1000 may change a PHY setting of the UFS host device 1000 based on the EOM result value.

[0187] At the same time, the UIC layer 1059 of the UFS memory device 1050 may also perform an EOM operation. For example, the UIC layer 1059 of the UFS memory device 1050 may perform an EOM operation on the differential input signal pair DIN_T and DIN_C received from the UFS host device 1000. In an embodiment, when the UFS memory device 1050 is powered on, the EOM unit 1063 in the UIC layer 1059 may perform an EOM operation. Thereafter, when the error count in the error count signal EC is a predetermined threshold or greater, the UIC layer 1059 may store an EOM result value in the device memory 1057 (refer to Fig.10 ). Thereafter, the UFS memory device 1050 may transmit the EOM result value to the UFS host device 1000. The UFS host device 1000 may change a PHY setting of the UFS host device 1000 based on the EOM result value.

[0188] Fig.13 is a diagram illustrating a data transmission and reception system according to an exemplary embodiment.

[0189] refer to Fig.13 , the data transmission and reception system 35 may include a first data transmission and reception device 1300 and a second data transmission and reception device 1350. The first data transmission and reception device 1300 may include a first interface 1301. The first interface 1301 may include an EOM unit 1303. The second data transmission and reception device 1350 may include a second interface 1359. The second interface 1359 may include an EOM unit 1363.

[0190] In an embodiment, when the first data transmission and reception device 1300 is powered on, the EOM unit 1303 may perform an EOM operation. In addition, when the second data transmission and reception device 1350 is powered on, the EOM unit 1363 may perform an EOM operation. That is, the EOM operation may be performed on the data symbols transmitted between the first data transmission and reception device 1300 and the second data transmission and reception device 1350.

[0191] When the error count in the error count signal EC is a predetermined threshold or more, the EOM unit 1303 may temporarily store the EOM result value in a memory in the first data transmitting and receiving device 1300. Thereafter, the first data transmitting and receiving device 1300 may transmit the EOM result value to the second data transmitting and receiving device 1350.

[0192] When the error count in the error count signal EC is a predetermined threshold or more, the EOM unit 1363 may temporarily store the EOM result value in a memory in the second data transmitting and receiving device 1350. Thereafter, the second data transmitting and receiving device 1350 may transmit the EOM result value to the first data transmitting and receiving device 1300.

[0193] In some embodiments, the first data transmitting and receiving device 1300 may be a camera module, and the second data transmitting and receiving device 1350 may be an application processor. In addition, in some embodiments, the first data transmitting and receiving device 1300 may be a display driver integrated circuit (IC), and the second data transmitting and receiving device 1350 may be a display panel. In addition, the first data transmitting and receiving device 1300 and the second data transmitting and receiving device 1350 may be implemented by being modified to various electronic devices not described herein.

[0194] Fig.14 is a diagram illustrating a user system to which a storage system according to an example embodiment is applied.

[0195] refer to Fig.14 The user system 30 includes an application processor 301 , a storage module 302 , a network module 303 , a storage module 304 , and a user interface 305 .

[0196] The application processor 301 may drive components included in the user system 30 and an operating system (OS). For example, the application processor 301 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 30. The application processor 301 may be provided as a system on chip (SoC).

[0197] The storage module 302 can work as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 30. The storage module 302 can include a volatile random access memory such as DRAM, synchronous DRAM (SDRAM), double data rate (double data rate, DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, low-power DDR (low-power DDR, LPDDR) SDRAM, LPDDR3 SDRAM, LPDDR3 SDRAM, etc., or a non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM.

[0198] The network module 303 may perform communication with an external device. For example, the network module 303 may support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, WI-DI. In an embodiment, the network module 303 may be included in the application processor 301.

[0199] The storage module 304 may store data. For example, the storage module 304 may store data received from the application processor 301. Alternatively, the storage module 304 may send data stored in the storage module 304 to the application processor 301. As an example, the storage module 304 may be implemented as a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, a three-dimensional NAND flash memory, etc.

[0200] As an example, the storage module 304 may correspond to the reference Figures 1 to 9 The storage device described (for example, Figure 1 of 200).

[0201] The storage module 304 may perform an EOM operation when powered on. For example, the storage module 304 may perform an EOM operation on a signal received from the storage module 302, a signal received from an external device through the network module 303, a signal input from the user interface 305, and the like. The storage module 304 may send an EOM result value obtained through the EOM operation to the application processor 301 using the AER method. Meanwhile, the EOM result value may include an eye diagram. As described above, the eye diagram may be a graph showing a signal according to a time offset value on the X-axis and a voltage offset value on the Y-axis. Since the eye diagram needs to represent the amplitude of the signal according to all clock values ​​and all voltage values ​​within a predetermined range, a large number of EOM operations may be required to generate the eye diagram. However, the storage module 304 according to an example embodiment may not perform an EOM operation (e.g., GetLog Page) in response to a request from a host device, but may perform an EOM operation when powered on. In addition, the storage module 304 may temporarily store an EOM result value obtained through the EOM operation. Therefore, in response to receiving a signal requesting an EOM result value, the stored EOM result value may be output. Therefore, when measuring the EOM characteristics of the signal received by the storage module 304, the EOM result value can be obtained more quickly. In addition, the storage module 304 can independently change the PHY setting based on the obtained EOM result value so that the error count becomes a predetermined threshold or less.

[0202] In the prior art, the storage module only sends the error count signal EC and the error sampling signal ES to the host according to the EOM operation, and the eye diagram can be generated by the host based on the error count signal EC and the error sampling signal ES received from the storage module. However, the storage module 304 according to the example embodiment also includes an EGU unit, and an eye diagram can be generated for a signal received from the outside. Therefore, the storage module 304 can output an EOM result value including not only the error count signal EC and the error sampling signal ES but also the eye diagram. In an embodiment, the storage module 304 can send the EOM result value to the host only when the error count exceeds a predetermined threshold. Therefore, the host does not need to directly generate an eye diagram, and since the EOM result value can be received only when the error count exceeds a predetermined threshold, the burden on the host can be reduced.

[0203] The user interface 305 may include an interface for inputting data or commands in the application processor 301 and / or outputting data to an external device. As an example, the user interface 305 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, a piezoelectric element, etc. The user interface 305 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, a motor, etc.

[0204] According to example embodiments, at least one of the parts, elements, modules or units described herein can be implemented as various numbers of hardware, software and / or firmware structures for running the corresponding functions described above. For example, at least one of these parts, elements or units can use a direct circuit structure that can run the corresponding function through the control of one or more microprocessors or other control devices, such as a memory, a processor, a logic circuit, a lookup table, etc. Moreover, at least one of these parts, elements or units can be specifically implemented by a part of a module, a program or a code that contains one or more executable instructions for performing a specific logical function and is run by one or more microprocessors or other control devices. Moreover, at least one of these parts, elements or units can also include a processor such as a central processing unit (CPU), a microprocessor, etc. that performs the corresponding function or is implemented by the processor. Two or more of these parts, elements or units can be combined into a single part, element or unit that performs all operations or functions of two or more parts, elements or units combined. Moreover, at least part of the function of at least one of these parts, elements or units can be performed by another of these parts, elements or units. Further, although the bus is not shown in the block diagram, the communication between the components, elements or units can be performed via the bus. The functional aspects of the above example embodiments can be implemented in algorithms running on one or more processors. In addition, the components, elements or units represented by blocks or processing operations can adopt any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0205] While the disclosure has been described in conjunction with example embodiments, it should be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A storage system, comprising: Host device; as well as A storage device, the storage device being configured to: upon being powered on, perform an EOM operation on a signal received from the host device to generate an EOM result value, store the EOM result value in a buffer memory, and output the EOM result value in the buffer memory to the host device in response to receiving an asynchronous event request command from the host device, the EOM being an eye opening monitor.

2. The storage system according to claim 1, wherein: The storage device comprises: an equalizer configured to adjust a gain of the received signal to generate equalized serial bits; a clock data recovery block configured to recover a received signal using the equalized serial bits; and An analog front end controller is configured to generate an analog front end control signal for controlling the equalizer based on the EOM result value.

3. The storage system according to claim 2, wherein: The equalizer includes a continuous time linear equalizer and a decision feedback equalizer, and The analog front-end control signal is a signal used to control at least one of the gain of the continuous-time linear equalizer or the gain of the decision feedback equalizer.

4. The storage system according to claim 2, wherein: The EOM operations include: inputting the equalized serial bits into a main path to obtain a first output based on a reference condition, the reference condition comprising a reference clock and a reference voltage; inputting the equalized serial bits into the EOM path while changing the offset clock and the offset voltage to obtain a second output; and The first output and the second output are compared.

5. The storage system according to claim 4, wherein: The clock data recovery block also includes: an EOM block configured to generate an error count signal based on a count of errors between the first output and the second output, and to generate a sample count signal based on a count of comparisons between the first output and the second output; and an eye diagram generating unit configured to generate an eye diagram showing a signal according to a clock and a voltage based on the error count signal and the sampling count signal, and The EOM result value includes at least one of the error count signal or the eye diagram.

6. The storage system according to claim 5, wherein: The analog front end control signal causes the count of the errors to have a predetermined threshold or less.

7. The storage system according to claim 5, wherein: The storage device is further configured to send the EOM result value to the host based on the count of the errors being equal to or greater than a predetermined threshold.

8. The storage system according to claim 4, wherein: The main path includes: a clock recovery circuit configured to generate the reference clock based on the equalized serial bits, a first slicer configured to extract data of the equalized serial bits based on the reference condition, and A first deserializer is configured to generate the first output by deserializing the data of the equalized serial bits extracted based on the reference condition.

9. The storage system according to claim 4, wherein: The EOM path includes: a multiplier configured to receive the reference clock from a clock recovery circuit and generate an EOM clock by reflecting the offset clock; a second slicer configured to extract data of the equalized serial bits based on the EOM clock and the offset voltage; a second deserializer configured to generate the second output by deserializing the extracted data of the equalized serial bits; and A comparator is configured to compare the first output and the second output.

10. A method of operating a storage system, the method comprising: The storage device performs an EOM operation on the received signal based on being powered on to generate an EOM result value, wherein the EOM is an eye opening monitor; receiving an asynchronous event request command from a host device; as well as The EOM result value is sent to the host device.

11. The method according to claim 10, wherein: The storage device further comprises a buffer memory, wherein the executing comprises storing the EOM result value in the buffer memory, and The sending includes sending the EOM result value stored in the buffer memory to the host device.

12. The method according to claim 10, wherein: The execution includes: inputting the received signal into a main path to obtain a first output based on a reference condition, the reference condition comprising a reference clock and a reference voltage; Setting an offset value, wherein the offset value includes an offset clock and an offset voltage; inputting the received signal into the EOM path to obtain a second output by using a predetermined offset value, the predetermined offset value varying within a predetermined range relative to the set offset value; determining whether the EOM operation is performed with respect to all offset values ​​within the predetermined range; and The EOM result value is generated based on determining that the EOM operation is performed with respect to all offset values ​​within the predetermined range.

13. The method according to claim 12, wherein: The storage device includes: an equalizer configured to adjust the gain of a received signal to generate equalized serial bits; and a clock data recovery block configured to recover the received signal using the equalized serial bits, and The method further includes generating an analog front-end control signal for controlling the equalizer based on the EOM result value.

14. The method according to claim 13, wherein: The equalizer includes a continuous time linear equalizer and a decision feedback equalizer, and Wherein, generating the analog front-end control signal comprises: changing a PHY setting based on the EOM result value, the PHY setting comprising a gain of at least one of the continuous time linear equalizer or the decision feedback equalizer; performing the EOM operation based on the changed PHY setting to determine whether a count of errors between the first output and the second output while changing the offset clock and the offset voltage is a predetermined threshold or less; and Based on determining that the count of the errors is the predetermined threshold or less, generating the analog front end control signal based on the changed PHY setting.

15. The method according to claim 12, wherein: The method further comprises: The EOM result value is transmitted to the host based on a count of errors between the first output and the second output being a predetermined threshold or more while the offset clock and the offset voltage are changed.

16. A storage device, comprising: an equalizer configured to adjust a gain of the received signal to generate equalized serial bits; An EOM unit, the EOM is an eye opening monitor, and the EOM unit is configured to: inputting the equalized serial bits into a main path to obtain a first output based on a reference condition, the reference condition comprising a reference clock and a reference voltage; inputting the equalized serial bits into the EOM path while changing an offset clock and an offset voltage to obtain a second output; as well as generating an error count signal based on a count of errors between the first output and the second output, and generating a sample count signal based on a count of comparisons between the first output and the second output; an eye diagram generating unit configured to generate an eye diagram based on the error count signal and the sampling count signal, in which the received signal is divided into unit intervals and the values ​​of the divided segments are superimposed on each other, and to generate an EOM result value including at least one of the error count signal or the eye diagram; as well as An analog front end controller is configured to control the equalizer based on the EOM result value.

17. The storage device according to claim 16, wherein: The storage device further comprises a buffer memory, wherein the EOM result value is stored in the buffer memory, and The storage device is configured to output the EOM result value in the buffer memory in response to receiving an asynchronous event request command.

18. The storage device according to claim 16, wherein: The equalizer includes a continuous time linear equalizer and a decision feedback equalizer, and Wherein, the analog front-end controller is also configured to generate an analog front-end control signal based on the EOM result value, and the analog front-end control signal is a signal for controlling at least one of the gain of the continuous-time linear equalizer or the gain of the decision feedback equalizer.

19. The storage device according to claim 18, wherein: The analog front end control signal causes the count of the errors to have a predetermined threshold or less.

20. The storage device according to claim 16, wherein: The main path includes: a clock recovery circuit configured to generate the reference clock based on the equalized serial bits; a first slicer configured to extract data of the equalized serial bits based on the reference condition; and a first deserializer configured to generate the first output by deserializing the data of the equalized serial bits extracted based on the reference condition; and Wherein, the EOM path includes: a multiplier, which is configured to receive the reference clock from the clock recovery circuit and generate an EOM clock by reflecting the offset clock; a second limiter, which is configured to extract the data of the equalized serial bits based on the EOM clock and the offset voltage; a second deserializer, which is configured to generate the second output by deserializing the extracted data of the equalized serial bits; and a comparator, which is configured to compare the first output and the second output.

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