Pause parameter determination device and pause parameter determination method

Abstract

The invention relates to a pause parameter determination apparatus and a pause parameter determination method. The pause parameter determination device may include: a power monitoring circuit configured to monitor power consumption information of a storage device; a memory device configured to store an artificial intelligence model; and a control circuit configured to load the artificial intelligence model, input the performance information of the storage device and the power consumption information received from the power monitoring circuit to the artificial intelligence model, and transmit a pause parameter output by the artificial intelligence model to the storage device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0131358, filed on October 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a pause parameter determination apparatus and a pause parameter determination method. Background Art

[0004] The storage device is a device that stores data according to a request from an external device such as a computer, a mobile terminal (eg, a smartphone, or a tablet), or the like.

[0005] The storage device may include a memory for storing data and a controller for controlling the memory. The memory may be a volatile memory or a non-volatile memory. The controller may receive a command from an external device (i.e., a host) and perform or control a data read, write, or erase operation on the memory of the storage device according to the received command.

[0006] To ensure low latency of the read operation, the memory device may suspend the program operation or erase operation being executed and perform the read operation with high priority instead.

[0007] When the number of times a memory device suspends a program operation or an erase operation increases, the possibility of satisfying the user's performance requirements for the memory device increases. However, since the suspend operation causes the time of the program operation or the erase operation to be extended, the power consumption of the memory device may increase. Summary of the invention

[0008] Various embodiments of the present disclosure are intended to provide a pause parameter determination device and a pause parameter determination method that can meet the performance requirements of a user on a storage device and optimize the power consumption of the storage device.

[0009] In an embodiment of the present disclosure, a pause parameter determination device may include: a power monitoring circuit configured to monitor power consumption information of a storage device; a memory device configured to store an artificial intelligence model; and a control circuit configured to load the artificial intelligence model, input the performance information of the storage device and the power consumption information received from the power monitoring circuit into the artificial intelligence model, and transmit the pause parameter output by the artificial intelligence model to the storage device. The pause parameter can be used to control the pause operation of a programming operation or an erase operation being performed by the storage device.

[0010] In another embodiment of the present disclosure, a method for determining a pause parameter may include: measuring performance information of a storage device; monitoring power consumption information of the storage device; inputting the performance information and power consumption information into an artificial intelligence model; and transmitting the pause parameter output by the artificial intelligence model to the storage device. The pause parameter may be used to control a pause operation for a programming operation or an erase operation being performed by the storage device.

[0011] In another embodiment of the present disclosure, a system may include: a storage device; and a pause parameter determination device configured to monitor power consumption information of the storage device, input performance information of the storage device and power consumption information of the storage device into an artificial intelligence model, and transmit the pause parameters output by the artificial intelligence model to the storage device. The storage device may store the pause parameters in a pause parameter table, and control a pause operation for a program operation or an erase operation being executed based on the pause parameters stored in the pause parameter table.

[0012] According to the embodiments of the present disclosure, the performance requirements of users on storage devices can be met while optimizing the power consumption of the storage devices.

[0013] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present disclosure and the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic configuration diagram of a storage device according to an embodiment of the present disclosure.

[0015] Figure 2 It is schematically shown Figure 1 Block diagram of the memory.

[0016] Figure 3 It is a schematic diagram showing the structure of a system according to an embodiment of the present disclosure.

[0017] Figure 4 is a diagram illustrating input and output of an artificial intelligence model according to an embodiment of the present disclosure.

[0018] Figure 5 is a diagram illustrating an example of information input to an artificial intelligence model according to an embodiment of the present disclosure.

[0019] Figure 6 is a diagram illustrating an example of pause parameters according to an embodiment of the present disclosure.

[0020] Figure 7 is a flow chart illustrating a pause parameter determination method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the specification, references to "an embodiment," "another embodiment," etc. do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. The term "embodiment" used herein does not necessarily refer to all embodiments.

[0022] Various embodiments of the present disclosure will be described in more detail below in conjunction with the accompanying drawings. However, the present invention can be implemented in different forms and variations and should not be construed as being limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the present disclosure will be complete and comprehensive and fully convey the present invention to those skilled in the art to which the present invention belongs. Throughout the disclosure, the same reference numerals refer to the same components in the various drawings and embodiments of the present invention.

[0023] The methods, processes and / or operations described herein may be performed by codes or instructions executed by a computer, processor, controller or other signal processing device. The computer, processor, controller or other signal processing device may be a device described herein, or an element other than the elements described herein. Since the algorithm underlying the method (or the operation of a computer, processor, controller or other signal processing device) is described in detail, the code or instructions for implementing the operation of the method embodiment may convert the computer, processor, controller or other signal processing device into a dedicated processor for performing the method herein.

[0024] When implemented at least partially in software, controllers, processors, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device.

[0025] Figure 1 is a schematic configuration diagram of a storage device 100 according to an embodiment of the present disclosure.

[0026] Reference Figure 1 , the storage device 100 may include a memory 110 that stores data and a controller 120 that controls the memory 110 .

[0027] The memory 110 includes a plurality of memory blocks, and operates in response to the control of the controller 120. The operation of the memory 110 may include, for example, a read operation, a program operation (also referred to as a write operation), and an erase operation.

[0028] The memory 110 may include a memory cell array including a plurality of memory cells (also simply referred to as “cells”) storing data.

[0029] For example, the memory 110 may be implemented as various types of memories, such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Fourth Generation Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer torque random access memory (STT-RAM).

[0030] The memory 110 may be implemented as a three-dimensional array structure. For example, the embodiments of the present disclosure may be applied to a charge trap flash memory (CTF) in which a charge storage layer is configured by a dielectric layer and a flash memory in which a charge storage layer is configured by a conductive floating gate.

[0031] The memory 110 may receive a command and an address from the controller 120 and may access a region selected by the address in the memory cell array. The memory 110 may perform an operation indicated by the command on the region selected by the address.

[0032] The memory 110 may perform a programming operation, a reading operation, or an erasing operation. For example, when performing a programming operation, the memory 110 may program data to an area selected by an address. When performing a reading operation, the memory 110 may read data from an area selected by an address. In an erasing operation, the memory 110 may erase data stored in an area selected by an address.

[0033] The controller 120 may control writing (programming), reading, erasing, and background operations of the memory 110. For example, the background operation may include at least one of a garbage collection (GC) operation, a wear leveling (WL) operation, a read reclaim (RR) operation, a bad block management (BBM) operation, and the like.

[0034] The controller 120 may control the operation of the memory 110 according to a request of a device (eg, a host) located outside the storage device 100. However, the controller 120 may also control the operation of the memory 110 regardless of the request of the host.

[0035] As non-limiting examples, the host may be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, a smart wearable device, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID (radio frequency identification) device, and a mobile device (e.g., a vehicle, a robot, or a drone) capable of traveling under human control or driving automatically. Alternatively, the host may be a virtual reality (VR) device providing a 2D or 3D virtual reality image or an augmented reality (AR) device providing an augmented reality image. The host may be any of various electronic devices that require a storage device 100 capable of storing data.

[0036] The host may include at least one operating system (OS). The OS may generally manage and control functions and operations of the host, and may control interoperability between the host and the storage device 100. The OS may be classified into a general OS and a mobile OS according to the mobility of the host.

[0037] The controller 120 and the host may be separate devices, or the controller 120 and the host may be integrated into one device. For convenience, the controller 120 and the host are described as separate devices below.

[0038] exist Figure 1 In the illustrated embodiment, the controller 120 may include a memory interface 122 and a control circuit 123. The controller 120 may further include a host interface 121.

[0039] The host interface 121 provides an interface for communicating with the host. For example, the host interface 121 provides an interface using at least one of the following various communication standards or interfaces: USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-e or PCIe (PCI Express) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, and a proprietary protocol.

[0040] When receiving a command from the host, the control circuit 123 may receive the command through the host interface 121 and perform an operation of processing the received command.

[0041] The memory interface 122 may be coupled with the memory 110 to provide an interface for communicating with the memory 110. The memory interface 122 may be configured to provide an interface between the memory 110 and the controller 120 in response to control of the control circuit 123.

[0042] The control circuit 123 performs general control operations of the controller 120 to control the operation of the memory 110. To this end, the control circuit 123 may include at least one of a processor 124 and a working memory 125. The control circuit 123 may optionally include an error detection and correction circuit (ECC circuit) 126.

[0043] The processor 124 may control general operations of the controller 120 and may perform logical operations. The processor 124 may communicate with the host through the host interface 121 and may communicate with the memory 110 through the memory interface 122.

[0044] The processor 124 may run the logic operations required to perform the flash translation layer (FTL) functions. The processor 124 may convert the logical block address (LBA) provided by the host into a physical block address (PBA) through the flash translation layer. The flash translation layer may receive the logical block address and convert the logical block address into a physical block address by using a mapping table.

[0045] There are multiple address mapping methods in the flash translation layer according to different mapping units. Representative address mapping methods include page mapping method, block mapping method and hybrid mapping method.

[0046] The processor 124 may randomize the data received from the host. For example, the processor 124 may randomize the data received from the host by using a set randomization seed. The randomized data may be provided to the memory 110 and may be programmed into the memory cell array of the memory 110.

[0047] In a read operation, the processor 124 may derandomize the data received from the memory 110. For example, the processor 124 may derandomize the data received from the memory 110 by using a derandomization seed. The derandomized data may be output to the host.

[0048] The processor 124 may run firmware to control the operation of the controller 120. That is, in order to control the general operation of the controller 120 and perform logical operations, the processor 124 may run (drive) the firmware loaded into the working memory 125 at startup. The operation of the storage device 100 according to an embodiment of the present disclosure is described below as implementing the processor 124 running the firmware that defines the corresponding operation.

[0049] The firmware is a program running in the storage device 100 for driving the storage device 100, which may include various functional layers. For example, the firmware may include binary data in which codes for running each functional layer are defined.

[0050] For example, the firmware may include at least one selected from the following: a flash translation layer, which performs a conversion function between a logical address requested by the host to the storage device 100 and a physical address of the memory 110; a host interface layer (HIL), which is used to analyze a command requested by the host to the storage device 100 and transmit the command to the flash translation layer; and a flash interface layer (FIL), which transmits a command indicated from the flash translation layer to the memory 110.

[0051] Such firmware may be loaded into the working memory 125 from, for example, the memory 110 or a separate nonvolatile memory (e.g., ROM or NOR flash) located outside the memory 110. The processor 124 may first load all or part of the firmware into the working memory 125 when performing a startup operation after power-on.

[0052] The processor 124 may execute the logic operations defined in the firmware loaded into the working memory 125 to control the general operation of the controller 120. The processor 124 may store the result of executing the logic operations defined in the firmware in the working memory 125. The processor 124 may control the controller 120 according to the result of executing the logic operations defined in the firmware so that the controller 120 generates a command or a signal. When a portion of the firmware defining the logic operations to be executed is stored in the memory 110 but is not loaded into the working memory 125, the processor 124 may generate an event (e.g., an interrupt) for loading the corresponding portion of the firmware from the memory 110 into the working memory 125.

[0053] The processor 124 may load metadata required for driving firmware from the memory 110. The metadata is data for managing the memory 110, and may include management information on user data stored in the memory 110, for example.

[0054] The firmware may be updated when the storage device 100 is manufactured or when the storage device 100 is operating. The controller 120 may download new firmware from outside the storage device 100 and update the existing firmware with the new firmware.

[0055] In order to drive the controller 120, the working memory 125 may store necessary firmware, program code, commands, and data. The working memory 125 may be a volatile memory, for example, including at least one of SRAM (static RAM), DRAM (dynamic RAM), and SDRAM (synchronous DRAM). In addition to the working memory 125, the controller 120 may also additionally use a separate volatile memory (e.g., SRAM, DRAM) located outside the controller 120.

[0056] The error detection and correction circuit 126 can detect error bits of target data by using an error correction code and correct the detected error bits. The target data can be, for example, data stored in the working memory 125 or data read from the memory 110.

[0057] The error detection and correction circuit 126 can decode the data by using an error correction code. The error detection and correction circuit 126 can be implemented by various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0058] For example, when each read data is composed of multiple sectors, the error detection and correction circuit 126 can detect the error bit in each read data in units of set sectors. A sector can represent a data unit smaller than a page, which is a read unit of a flash memory. The sectors constituting each read data can be matched with each other using addresses.

[0059] The error detection and correction circuit 126 may calculate a bit error rate (BER) in units of sectors and determine whether the error is correctable. For example, when the bit error rate is greater than a reference value, the error detection and correction circuit 126 may determine that the corresponding sector is uncorrectable or failed. On the other hand, when the bit error rate is less than the reference value, the error detection and correction circuit 126 may determine that the corresponding sector is correctable or passed.

[0060] The error detection and correction circuit 126 may sequentially perform error detection and correction operations on all read data. In the case where a sector included in the read data is correctable, the error detection and correction circuit 126 may omit the error detection and correction operation for the corresponding sector of the next read data. If the error detection and correction operation for all read data is ended in this manner, the error detection and correction circuit 126 may detect the last uncorrectable sector in the read data. One or more sectors may be determined to be uncorrectable. The error detection and correction circuit 126 may transmit information (e.g., address information) about the sector determined to be uncorrectable to the processor 124.

[0061] The bus 127 may be configured to provide a channel between the components 121, 122, 124, 125, 126 of the controller 120. The bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., a data bus for transmitting various data, etc.

[0062] Some of the components 121, 122, 124, 125, 126 of the controller 120 may be omitted, or some of the components 121, 122, 124, 125, 126 of the controller 120 may be integrated into one component. In addition to the components 121, 122, 124, 125, 126 of the controller 120, one or more other components may be added.

[0063] The following will refer to Figure 2 The memory 110 is described in further detail.

[0064] Figure 2 It is schematically shown Figure 1 A block diagram of the memory 110 is shown.

[0065] Reference Figure 2 , the memory 110 according to an embodiment of the present disclosure may include a memory cell array 210 , an address decoder 220 , a read and write circuit 230 , a control logic 240 , and a voltage generation circuit 250 .

[0066] The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz, where z is a natural number of 2 or more.

[0067] In the plurality of memory blocks BLK1 to BLKz, a plurality of word lines WL and a plurality of bit lines BL may be provided, and a plurality of memory cells may be arranged.

[0068] The plurality of memory blocks BLK1 to BLKz may be coupled to the address decoder 220 through a plurality of word lines WL. The plurality of memory blocks BLK1 to BLKz may be coupled to the read and write circuit 230 through a plurality of bit lines BL.

[0069] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells may be nonvolatile memory cells and may be configured of nonvolatile memory cells having a vertical channel structure.

[0070] The memory cell array 210 may be configured by a memory cell array of a two-dimensional structure, or may be configured by a memory cell array of a three-dimensional structure.

[0071] Each of the plurality of memory cells included in the memory cell array 210 may store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-layer cell (SLC) storing 1 bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-layer cell (MLC) storing 2 bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-layer cell (TLC) storing 3 bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-layer cell (QLC) storing 4 bits of data. In other examples, the memory cell array 210 may include a plurality of memory cells, each of which stores 5 or more bits of data.

[0072] The number of bits of data stored in each of the plurality of memory cells can be dynamically determined. For example, a single-layer cell storing 1 bit of data can be changed to a triple-layer cell storing 3 bits of data.

[0073] exist Figure 2 In the illustrated embodiment, the address decoder 220 , the read and write circuit 230 , the control logic 240 , and the voltage generation circuit 250 may operate as peripheral circuits for driving the memory cell array 210 .

[0074] The address decoder 220 may be coupled to the memory cell array 210 through a plurality of word lines WL.

[0075] The address decoder 220 may be configured to operate in response to the control of the control logic 240 .

[0076] The address decoder 220 may receive an address through an input / output buffer in the memory 110. The address decoder 220 may be configured to decode a block address in the received address. The address decoder 220 may select at least one memory block according to the decoded block address.

[0077] The address decoder 220 may receive a read voltage Vread and a pass voltage Vpass from the voltage generating circuit 250 .

[0078] During a read operation, the address decoder 220 may apply a read voltage Vread to a selected word line WL in a selected memory block, and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0079] During a program verification operation, the address decoder 220 may apply a verification voltage generated in the voltage generation circuit 250 to a selected word line WL in a selected memory block, and may apply a pass voltage Vpass to the remaining unselected word lines WL.

[0080] The address decoder 220 may be configured to decode the column address in the received address. The address decoder 220 may transmit the decoded column address to the read and write circuit 230.

[0081] A read operation and a program operation of the memory 110 may be performed in units of pages. An address received when requesting a read operation or a program operation may include at least one of a block address, a row address, and a column address.

[0082] The address decoder 220 may select a memory block and a word line according to the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read and write circuit 230.

[0083] The address decoder 220 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0084] The read and write circuit 230 may include a plurality of page buffers PB. The read and write circuit 230 may operate as a read circuit in a read operation of the memory cell array 210 and may operate as a write circuit in a write operation of the memory cell array 210.

[0085] The above-mentioned read and write circuit 230 may also be referred to as a page buffer circuit or a data register circuit including a plurality of page buffers PB. The read and write circuit 230 may include a data buffer responsible for a data processing function, and may further include a cache buffer responsible for a cache function.

[0086] The plurality of page buffers PB may be connected to the memory cell array 210 through the plurality of bit lines BL. In a read operation and a program verification operation, the plurality of page buffers PB may continuously provide a sensing current to the bit lines BL connected to the memory cells to sense the threshold voltage (Vth) of the memory cells. In addition, the plurality of page buffers PB may latch sensing data by sensing a change in the amount of current generated according to a programming state of the corresponding memory cells through a sensing node.

[0087] The read and write circuit 230 may operate in response to a page buffer control signal output from the control logic 240 .

[0088] In a read operation, the read and write circuit 230 temporarily stores the read data by sensing the data of the memory cell and then outputs the data DATA to the input / output buffer of the memory 110. In an embodiment, the read and write circuit 230 may further include a column selection circuit in addition to the page buffer PB or the page register.

[0089] The control logic 240 may be coupled with the address decoder 220, the read and write circuit 230, and the voltage generating circuit 250. The control logic 240 may receive a command CMD and a control signal CTRL through an input / output buffer of the memory 110.

[0090] The control logic 240 may be configured to control a general operation of the memory 110 in response to the control signal CTRL. The control logic 240 may output a control signal for adjusting a precharge potential level of a sensing node of a plurality of page buffers PB.

[0091] The control logic 240 may control the read and write circuit 230 to perform a read operation of the memory cell array 210. The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass used in a read operation in response to a voltage generation circuit control signal output from the control logic 240.

[0092] Each memory block of the above-described memory 110 may be configured by a plurality of pages corresponding to a plurality of word lines WL and a plurality of strings corresponding to a plurality of bit lines BL.

[0093] In the memory block BLK, a plurality of word lines WL and a plurality of bit lines BL may be arranged to cross each other. For example, each of the plurality of word lines WL may be arranged along a row direction, and each of the plurality of bit lines BL may be arranged along a column direction. In another example, each of the plurality of word lines WL may be arranged along a column direction, and each of the plurality of bit lines BL may be arranged along a row direction.

[0094] The memory cell may be connected to one of a plurality of word lines WL and one of a plurality of bit lines BL. A transistor may be provided in each memory cell.

[0095] For example, the transistor provided in each memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected to the corresponding bit line BL directly or through another transistor. The source (or drain) of the transistor may be connected to a source line (which may be grounded) directly or through another transistor. The gate of the transistor may include a floating gate surrounded by a dielectric and a control gate to which a gate voltage is applied from a word line WL.

[0096] In each memory block, a first selection line (also called a source selection line or a drain selection line) may be additionally set outside a first outermost word line of the two outermost word lines that is closer to the read and write circuit 230, and a second selection line (also called a drain selection line or a source selection line) may be additionally set outside a second outermost word line of the two outermost word lines.

[0097] At least one dummy word line may be additionally provided between the first outermost word line and the first selection line. At least one dummy word line may be additionally provided between the second outermost word line and the second selection line.

[0098] The read operation and program operation (write operation) of the above-mentioned memory block may be performed in units of pages, and the erase operation may be performed in units of memory blocks.

[0099] Figure 3 It is a schematic diagram showing the structure of a system 300 according to an embodiment of the present disclosure.

[0100] Reference Figure 3 , the system 300 may include a storage device 310 and a pause parameter determination device 320 .

[0101] The storage device 310 is a device that can store data. For example, the storage device 310 can be the above-mentioned Figure 1 The storage device 100 described above. The storage device 310 may receive a read request or a write request from the pause parameter determination device 320 or a separate computing device, and may process the read request or the write request.

[0102] The pause parameter determining device 320 is a device for determining a pause parameter, which is a parameter for controlling a pause operation for a program operation or an erase operation being performed by the storage device 310. The storage device 310 can determine whether to perform a pause operation for a program operation or an erase operation, a time point for performing the pause operation, and the number of times the pause operation is performed based on the pause parameter.

[0103] For example, the pause parameter determination device 320 may be the above reference Figure 1 In this case, the pause parameter determining device 320 may transmit a read request or a write request to the storage device 310 and may determine the pause parameter at the same time.

[0104] For another example, the pause parameter determination device 320 may be a separate device from the host and the storage device 310 .

[0105] The pause parameter determination device 320 may include a power monitoring circuit 321 , a memory device 322 , and a control circuit 323 .

[0106] The power monitoring circuit 321 may monitor power consumption information of the storage device 310 .

[0107] For example, the power monitoring circuit 321 may determine the power consumption information of the storage device 310 by sensing the power consumed by the storage device 310 within a predetermined period of time.

[0108] For another example, the power monitoring circuit 321 may request the storage device 310 for the power consumption information of the storage device 310 , and may determine the power consumption information of the storage device 310 based on the response of the storage device 310 to the request.

[0109] The memory device 322 may store the artificial intelligence model MDL. For example, the memory device 322 may be a volatile memory (e.g., SRAM or DRAM) or a non-volatile memory (e.g., NAND flash memory or NOR flash memory). The artificial intelligence model MDL may be a program that has been trained on a set of data to recognize certain patterns or make certain decisions without further human intervention.

[0110] The artificial intelligence model MDL is a model for determining the pause parameters of the storage device 310 .

[0111] The artificial intelligence model MDL may be a model that is pre-learned based on preset learning data. Learning the artificial intelligence model MDL means adjusting internal parameters of the artificial intelligence model MDL (e.g., weights of nodes included in the artificial intelligence model MDL) based on pause parameters output according to the learning data input to the artificial intelligence model MDL when the storage device 310 is operating, so as to meet the user's performance requirements for the storage device 310 and optimize the power consumption of the storage device 310.

[0112] The learning process of the artificial intelligence model MDL can be expressed as training, and the result of training can be expressed as learning, but training or learning can be used to represent the learning process or result.

[0113] The learning of the artificial intelligence model MDL can be performed directly in the pause parameter determination device 320 or in a separate computing device. The pause parameter determination device 320 can load the artificial intelligence model MDL learned in the separate computing device into the memory device 322 .

[0114] The control circuit 323 may load the artificial intelligence model MDL from the memory device 322 , and may determine the pause parameters of the storage device 310 using the artificial intelligence model MDL.

[0115] The control circuit 323 may include a processor or a processing core that performs an operation of outputting a pause parameter using the loaded artificial intelligence model MDL. To this end, the control circuit 323 may drive software including instructions that define an operation of outputting a pause parameter using the artificial intelligence model MDL.

[0116] The control circuit 323 may use the artificial intelligence model MDL to perform an operation of determining the pause parameters of the storage device 310 within a preset time period (e.g., 5 to 10 minutes). The control circuit 323 may repeat the operation of determining the pause parameters of the storage device 310 a preset number of times (e.g., 1000 times).

[0117] The control circuit 323 may transmit the pause parameter to the storage device 310. For example, the control circuit 323 may transmit the pause parameter to the storage device 310 through a preset interface (eg, UART).

[0118] The storage device 310 may store the received pause parameters in a pause parameter table 311 in the storage device 310. For example, the pause parameter table 311 may be allocated to the above reference Figure 1 The memory space of the working memory 125 or the memory 110 is described.

[0119] The memory device 310 may control a pause operation for a program operation or an erase operation being performed based on the pause parameters stored in the pause parameter table 311 .

[0120] Figure 4 is a diagram showing the input and output of the artificial intelligence model MDL based on an embodiment of the present disclosure.

[0121] Reference Figure 4 , the artificial intelligence model MDL can receive performance information of the storage device 310 and power consumption information of the storage device 310.

[0122] The performance information of the storage device 310 may indicate the performance of the storage device 310 in processing at least one of a read operation and a write operation.

[0123] For example, the pause parameter determination device 320 may send a request for a read operation or a write operation to the storage device 310 according to the workload type set by the user, and the storage device 310 may respond to the pause parameter determination device 320 with the processing result of the request. The pause parameter determination device 320 may directly measure the performance information of the storage device 310 based on the response of the storage device 310.

[0124] For another example, the pause parameter determination device 320 may send a request for at least one of a read operation and a write operation to the storage device 310 , and receive performance information of the storage device 310 from the storage device 310 after the storage device 310 processes the request.

[0125] The power consumption information of the storage device 310 may be received through the power monitoring circuit 321 .

[0126] The artificial intelligence model MDL may output a pause parameter for the storage device 310 based on the received performance information and power consumption information. The artificial intelligence model MDL may output an optimal pause parameter within the range that the power consumption of the storage device 310 is optimized and the performance information of the storage device 310 meets the performance requirements.

[0127] The artificial intelligence model MDL can be implemented in many ways.

[0128] The artificial intelligence model MDL can be a current or future machine learning model, such as a model using algorithm-based machine learning or a model using artificial neural network-based learning.

[0129] Models using algorithm-based machine learning can be classic machine learning models such as tree-based models, k-nearest neighbors, k-means clustering, principal component analysis (PCA), support vector machines (SVM), etc.

[0130] The tree-based model may be, for example, a decision tree model, a regression model, or a random tree model.

[0131] The artificial intelligence model MDL can be an integrated model that solves the problem by learning and combining multiple models instead of using only one learning model.

[0132] The ensemble model can prevent overfitting problems and improve generalization performance by combining multiple independently learned models. When the performance of a single model cannot be guaranteed, the ensemble model can help improve performance.

[0133] The ensemble model can be roughly divided into voting method and boosting method.

[0134] A voting method is a method that obtains a final result by voting on the results produced by multiple models. For example, a voting method can be a bagging method, which combines algorithms of the same type but uses different learning data. A voting method can also combine algorithms of different types.

[0135] Boosting is a method of generating a more accurate and powerful machine learning model by combining weak machine learning models. Boosting is a method in which each weak machine learning model works sequentially and the later running weak machine learning model additionally explores the parts that the previous weak machine learning model did not discover. For example, boosting can be random forest, gradient boosting, eXtra Gradient Boost (XGBoost), etc.

[0136] Artificial neural network is a machine learning algorithm that imitates the working principle of human brain and is based on multiple interconnected artificial neurons to analyze and learn complex data. Artificial neural network can be i) Multilayer Perceptron (MLP), which is the most basic artificial neural network structure, consisting of input layer, hidden layer and output layer; ii) Convolutional Neural Network (CNN), which performs convolution operation to extract image features and reduces dimensionality through pooling operation; iii) Recurrent Neural Network (RNN), which is an artificial neural network structure for processing ordered data; etc. There are many modifications that can be made to artificial neural network according to the complexity and diversity of data.

[0137] Models based on artificial neural network training can also be ensemble models, which solve problems by learning and combining multiple models instead of learning and using only one model.

[0138] The algorithm-based machine learning model and the artificial neural network-based learning model can be used to complement each other. For example, the algorithm-based machine learning model can use the results of the artificial neural network-based learning model, and the artificial neural network-based learning model can use the results of the algorithm-based machine learning model. An integrated model between the algorithm-based machine learning model and the artificial neural network-based learning model can be used.

[0139] For example, the artificial intelligence model MDL may be a reinforcement learning model, which is a model that learns through reinforcement learning to determine or continuously update internal parameters.

[0140] Reinforcement learning is based on the idea that when given an environment where the agent can decide what action to take at each moment, the agent can choose the best action through experience without data.

[0141] For example, reinforcement learning can be performed via a Markov decision process (MDP), which is a process that first defines how the agent will act in the environment, defines rewards or penalties based on the agent's actions, and derives an optimal policy through repeated experience until future rewards are maximized.

[0142] For example, the reinforcement learning model can be a genetic algorithm model, a particle swarm optimization model, or an ant colony optimization model. The genetic algorithm model is a model that can be applied to a variety of problems and is effective for problems with a large solution space. The particle swarm optimization model is a model that is effective for continuous problems and can effectively find the global optimal solution. The ant colony optimization model is a model that is effective for combinatorial optimization problems or path problems.

[0143] Figure 5is a diagram illustrating an example of information input to an artificial intelligence model MDL according to an embodiment of the present disclosure.

[0144] exist Figure 5 In the embodiment, the performance information of the storage device 310 may include at least one of data throughput information and delay information.

[0145] The data throughput information may indicate the data throughput, i.e., the size of data read from or written to the storage device 310 within a predetermined time period. For example, the pause parameter determination device 320 may receive a response of the size of data read or written within a predetermined time period from the storage device 310, and may determine the data throughput based on the response. For example, the data throughput may range between 0 and a preset maximum throughput value.

[0146] The latency information may indicate a percentage of read commands processed within a corresponding reference processing time among read commands transmitted to the storage device 310 within a predetermined period of time. The reference processing time of the read commands may be different from each other and may be determined based on the size of data requested by the read command.

[0147] For example, when 99 read commands among 100 read commands transmitted to the storage device 310 are processed within the reference processing time, the delay information may indicate 99% (=99 / 100). For example, the delay information may range between 0 and a preset percentage value (eg, 99.9999%).

[0148] The power consumption information of the storage device 310 may include at least one of peak power consumption information and average power consumption information.

[0149] The peak power consumption information may indicate a value of the maximum power consumed by the storage device 310 within a predetermined period of time. For example, the peak power consumption information may range between 0 and a preset maximum power consumption value.

[0150] The average power consumption information may indicate an average value of the power consumed by the storage device 310 within a predetermined period of time. For example, the range of the average power consumption information may also be between 0 and a preset maximum power consumption value.

[0151] Figure 6 is a diagram illustrating an example of pause parameters according to an embodiment of the present disclosure.

[0152] Reference Figure 6 The suspend parameter may include at least one of a maximum program suspend count, a maximum erase suspend count, a suspend delay value after program resume, and a suspend delay value after erase resume.

[0153] The maximum program suspend count and the suspend delay value after program resume may be used to control the suspension of a program operation, and the maximum erase suspend count and the suspend delay value after erase resume may be used to control the suspension of an erase operation.

[0154] The maximum program suspension count may indicate a maximum count by which a program operation may be suspended at one time. After a program operation is suspended by the maximum program suspension count, the corresponding program operation is no longer suspended by a read operation until the corresponding program operation is completed.

[0155] For example, the maximum program suspend count may range between 1 and 15.

[0156] The maximum erase suspend count may indicate a maximum count by which an erase operation may be suspended. After the erase operation is suspended by the maximum erase suspend count, the corresponding erase operation is no longer suspended by a read operation until the corresponding erase operation is completed.

[0157] For example, the maximum erase suspend count may range between 1 and 10.

[0158] The program resume suspend delay value may indicate the duration of the non-suspend state after a program operation is resumed. After the program operation is resumed, the corresponding program operation may be suspended by a read operation after the program resume suspend delay value has elapsed.

[0159] For example, the pause delay value after programming resume can be between 50us and 400us.

[0160] The post-erase resume pause delay value may indicate the duration of the non-pause state after an erase operation is resumed. After the erase operation is resumed, the corresponding erase operation may be suspended by a read operation after the post-erase resume pause delay value has passed.

[0161] For example, the pause delay value after erase resume can be between 1200us and 2000us.

[0162] Figure 7 is a flow chart illustrating a pause parameter determination method according to an embodiment of the present disclosure.

[0163] Reference Figure 7 The pause parameter determination method may include S710 , namely measuring performance information of the storage device 310 .

[0164] For example, the performance information may include at least one of data throughput information and latency information. The data throughput information may indicate the size of data read from or written to the storage device 310 within a predetermined time period. The latency information may indicate the percentage of read commands processed within a reference processing time among read commands transmitted to the storage device 310.

[0165] The method for determining the pause parameters may include S720 , namely monitoring power consumption information of the storage device 310 .

[0166] For example, the power consumption information may include at least one of peak power consumption information of the storage device 310 and average power consumption information of the storage device 310 within a predetermined period of time.

[0167] The pause parameter determination method may include S730, that is, inputting the performance information and the power consumption information into the artificial intelligence model MDL.

[0168] The method for determining the pause parameter may include S740, that is, transmitting the pause parameter output by the artificial intelligence model MDL to the storage device 310. The pause parameter may be used to control a pause operation for a program operation or an erase operation being executed by the storage device 310.

[0169] For example, the suspension parameter may include at least one of a maximum program suspension count, a maximum erase suspension count, a suspension delay value after program resumption, and a suspension delay value after erase resumption. The maximum program suspension count may indicate a maximum count at which a program operation can be suspended. The maximum erase suspension count may indicate a maximum count at which an erase operation can be suspended. The suspension delay value after program resumption may indicate a time during which a non-suspended state lasts after a program operation is resumed. The suspension delay value after erase resumption may indicate a time during which a non-suspended state lasts after an erase operation is resumed.

[0170] Although the embodiments of the present disclosure are described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in the above description and the accompanying drawings should be considered only in a descriptive sense and should not limit the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted in conjunction with the attached claims and cover all equivalent forms within the scope of the attached claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A pause parameter determination device, comprising: A power monitoring circuit, monitoring power consumption information of the storage device; A memory device for storing artificial intelligence models; as well as a control circuit that loads the artificial intelligence model, inputs the performance information of the storage device and the power consumption information received from the power monitoring circuit into the artificial intelligence model, and transmits the pause parameter output by the artificial intelligence model to the storage device, The pause parameter is used to control a pause operation of a programming operation or an erasing operation being executed by the storage device.

2. The pause parameter determination device according to claim 1, wherein: The performance information includes at least one of data throughput information and delay information, The data throughput information indicates the size of data read from or written to the storage device within a predetermined period of time, and The latency information indicates a percentage of read commands processed within a reference processing time among read commands transmitted to the memory device.

3. The pause parameter determination device according to claim 1, wherein: The power consumption information includes at least one of peak power consumption information of the storage device and average power consumption information of the storage device within a predetermined time period.

4. The pause parameter determination device according to claim 1, wherein: The artificial intelligence model is a reinforcement learning model.

5. The pause parameter determination device according to claim 4, wherein: The reinforcement learning model is a genetic algorithm model, a particle swarm optimization model or an ant colony optimization model.

6. The pause parameter determination device according to claim 1, wherein: The suspend parameter includes at least one of a maximum program suspend count, a maximum erase suspend count, a suspend delay value after program resume, and a suspend delay value after erase resume, The maximum program suspension count indicates a maximum count at which a program operation can be suspended. The maximum erase suspend count indicates the maximum count at which an erase operation can be suspended. The post-programming resume pause delay value indicates the duration of a non-suspended state after a programming operation is resumed, and The post-erase resume pause delay value indicates the duration of a non-suspend state after an erase operation is resumed.

7. A method for determining a pause parameter, comprising: measuring performance information of the storage device; Monitoring power consumption information of the storage device; inputting the performance information and the power consumption information into an artificial intelligence model; transmitting the pause parameters output by the artificial intelligence model to the storage device, The pause parameter is used to control a pause operation of a programming operation or an erasing operation being executed by the storage device.

8. The method for determining pause parameters according to claim 7, wherein: The performance information includes at least one of data throughput information and delay information, The data throughput information indicates the size of data read from or written to the storage device within a predetermined period of time, and The latency information indicates a percentage of read commands processed within a reference processing time among read commands transmitted to the memory device.

9. The method for determining pause parameters according to claim 7, wherein: The power consumption information includes at least one of peak power consumption information of the storage device and average power consumption information of the storage device within a predetermined time period.

10. The method for determining pause parameters according to claim 7, wherein: The suspend parameter includes at least one of a maximum program suspend count, a maximum erase suspend count, a suspend delay value after program resume, and a suspend delay value after erase resume, The maximum program suspension count indicates a maximum count at which a program operation can be suspended. The maximum erase suspend count indicates the maximum count at which an erase operation can be suspended. The post-programming resume pause delay value indicates the duration of a non-suspended state after a programming operation is resumed, and The post-erase resume pause delay value indicates the duration of a non-suspend state after an erase operation is resumed.

11. A system comprising: Storage device; as well as a pause parameter determination device, monitoring the power consumption information of the storage device, inputting the performance information of the storage device and the power consumption information of the storage device into an artificial intelligence model, and transmitting the pause parameter output by the artificial intelligence model to the storage device, The storage device stores the pause parameters in a pause parameter table, and controls a pause operation for a program operation or an erase operation being executed based on the pause parameters stored in the pause parameter table.

12. The system according to claim 11, wherein: The performance information includes at least one of data throughput information and delay information, The throughput information indicates the size of data read from or written to the storage device within a predetermined period of time, and The data delay information indicates a percentage of read commands processed within a reference processing time among read commands transmitted to the memory device.

13. The system according to claim 11, wherein: The power consumption information includes at least one of peak power consumption information of the storage device and average power consumption information of the storage device within a predetermined time period.

14. The system according to claim 11, wherein: The artificial intelligence model is a reinforcement learning model.

15. The system of claim 14, wherein: The reinforcement learning model is a genetic algorithm model, a particle swarm optimization model or an ant colony optimization model.

16. The system according to claim 11, wherein: The suspend parameter includes at least one of a maximum program suspend count, a maximum erase suspend count, a suspend delay value after program resume, and a suspend delay value after erase resume, The maximum program suspension count indicates a maximum count at which a program operation can be suspended. The maximum erase suspend count indicates the maximum count at which an erase operation can be suspended. The post-programming resume pause delay value indicates the duration of a non-suspended state after a programming operation is resumed, and The post-erase resume pause delay value indicates the duration of a non-suspend state after an erase operation is resumed.

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