Image display method, host and non-transitory computer readable medium

Abstract

The invention provides an image display method. The image display method includes the following steps. A request signal for rendering a vertical synchronization signal of an image of a next frame is transmitted from an application to a processing layer of the system. In response to receiving the request signal by the processing layer, the processing layer may be configured to generate the local vertical synchronization signal without reference to the hardware vertical synchronization signal. The application may be configured to render an image of the next frame based on the local vertical synchronization signal.

Description

Technical Field

[0001] The present disclosure relates to an image display method; in particular, the present disclosure relates to an image display method, a host and a non-transitory computer-readable medium. Background Art

[0002] When an application or view is displayed by a display, the frame rate of the graphics processing unit (GPU) and the refresh rate of the display are two important factors. If there is a deviation between the frame rate of the GPU and the refresh rate of the display, tearing may be exhibited on the displayed image on the display. In order to match the frame rate of the GPU and the refresh rate of the display with each other, vertical synchronization (Vsync) may be used to synchronize the frame rate of the GPU with the refresh rate of the display. Summary of the invention

[0003] The present disclosure relates to an image display method and a host to avoid the tearing effect.

[0004] In the present disclosure, an image display method is provided. The image display method includes: transmitting a request signal of a vertical synchronization signal for rendering an image of a next frame from an application to a processing layer of a system; in response to receiving the request signal by the processing layer, generating a local vertical synchronization signal by the processing layer without referring to a hardware vertical synchronization signal; and rendering the image of the next frame by the application based on the local vertical synchronization signal.

[0005] In the present disclosure, a host is provided. The host includes a memory storing program code and a processor coupled to the memory. The processor is configured to access the program code to perform the following operations: transmitting a request signal of a vertical synchronization signal for rendering an image of a next frame from an application to a processing layer; in response to receiving the request signal by the processing layer, generating a local vertical synchronization signal by the processing layer; and rendering the image of the next frame by the application based on the local vertical synchronization signal.

[0006] Based on the above, depending on the image display method and the host, the possibility of the tearing effect occurring is reduced.

[0007] In order to make the foregoing content more understandable, several embodiments with accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0009] Figure 1ASchematic diagram of the hardware structure of the image display method according to an embodiment of the present disclosure.

[0010] Figure 1B Schematic diagram of the software structure of the image display method according to an embodiment of the present disclosure.

[0011] Figure 2 Schematic diagram of an exemplary pipeline of an image display method according to an embodiment of the present disclosure.

[0012] Figure 3 is a schematic diagram of an exemplary flow chart of an exemplary pipeline according to an embodiment of the present disclosure.

[0013] Figure 4 is a schematic flowchart of an image display method according to an embodiment of the present disclosure.

[0014] Description of Figure Numbers

[0015] 100A: Hardware structure;

[0016] 100B: Software structure;

[0017] 110: Application;

[0018] 120: processing layer;

[0019] 130: sampling layer;

[0020] 140, 240: Hardware abstraction layer;

[0021] 190: host;

[0022] 191: Processor;

[0023] 192: memory;

[0024] 195: Display;

[0025] 200: assembly line;

[0026] 210: Application layer;

[0027] 220: Display event receiver layer;

[0028] 230: Display the synchronization model layer;

[0029] 300: Flowchart;

[0030] 400: Image display method;

[0031] PRD: Software Lifecycle;

[0032] RQS: request signal;

[0033] S310, S320, S330, S340, S350, S360, S370, S380, S390, S410, S420, S430: steps;

[0034] UPD: Update signal;

[0035] V_H: hardware Vsync signal;

[0036] V_L: local Vsync signal;

[0037] V_S: software Vsync signal. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or similar components.

[0039] In the specification and claims of the present disclosure, certain terms are used to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. It is not intended herein to distinguish between components that have the same function but different names. In the following description and claims, words such as "include" and "comprising" are open-ended terms and should be interpreted as "including but not limited to...".

[0040] The term "coupling (or connection)" used throughout the entire specification of the application (including the attached claims) may refer to any direct or indirect connection member. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connecting members. The terms "first", "second" and similar terms mentioned throughout the entire specification of the application (including the attached claims) are only used to name discrete elements or to distinguish between different embodiments or scopes. Therefore, the terms should not be regarded as limiting the upper or lower limit of the number of elements and should not be used to limit the arrangement order of elements. In addition, where possible, the elements / components / steps with the same figure numbers in the drawings and embodiments represent the same or similar parts. The related descriptions of the elements / components / steps can be referenced to each other using the same figure numbers or using the same terms in different embodiments.

[0041] It should be noted that in the following embodiments, the technical features of several different embodiments may be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the present disclosure. As long as the features of each embodiment do not violate the spirit of the present disclosure or conflict with each other, they may be mixed and used together at will.

[0042] When an application or view is displayed by a display, the frame rate of the GPU and the refresh rate of the display are two important factors. If there is a deviation between the frame rate of the GPU and the refresh rate of the display, tearing may be shown on the displayed image on the display. In order to match the frame rate of the GPU and the refresh rate of the display with each other, a Vsync signal may be used to synchronize the frame rate of the GPU with the refresh rate of the display.

[0043] The traditional pipeline of the Vsync signal can start from the application layer where the application or view is located. A request for the Vsync signal of the next frame can be sent from the application layer to the processing (handler) layer (e.g., the drawing scheduler (choreographer) in the Android framework). The processing layer can send the request to the sampling layer (e.g., the SurfaceFlinger layer in the Android framework). After the sampling layer receives the request from the processing layer, the hardware Vsync signal can be sent from the hardware abstraction layer (HAL) to the sampling layer. A hardware Vsync signal can be generated based on the display. After the sampling layer receives the hardware Vsync signal, the sampling layer can calculate the software Vsync signal and provide the software Vsync signal to the processing layer. The processing layer can transmit the software Vsync signal to the application layer. After the application receives the software Vsync signal, the application layer can start drawing the content of the next frame. In this way, the frame rate of the GPU and the refresh rate of the display can be synchronized to prevent tearing.

[0044] It should be noted that inter-process communication may cause delays to the Vsync signal. For example, for a frame rate of 90, the interval between frames is 1000 milliseconds / 90 frames = 11.11 milliseconds. According to experimental data, the difference between the maximum and minimum values ​​of the hardware Vsync signal received by the sampling layer may be 0.038 milliseconds. On the other hand, the difference between the maximum and minimum values ​​of the software Vsync signal received by the processing layer may be 0.8 milliseconds. That is, when the processing layer receives the software Vsync signal, a delay to the Vsync signal may occur. Due to the inaccuracy of the software Vsync signal, the GPU may not be able to accurately start drawing the content of the next frame, thereby increasing the possibility of tearing effects and reducing the user experience. In addition, since the request for the Vsync signal is frame by frame, it can be attributed to the transmission of the Vsync signal that at least partially occupies computing power. Therefore, a technician in the field hopes to provide an effective and correct method for providing a Vsync signal to the GPU.

[0045] Figure 1AFIG. 1 is a schematic diagram of the hardware structure of the image display method according to an embodiment of the present disclosure. Figure 1A , the hardware structure 100A of the image display method may include a host 190 and a display 195 coupled to the host 190. In different embodiments, the host 190 may be implemented as various smart devices and / or computer devices, but is not limited thereto. In addition, the display 195 may be integrated into the host 190 or separated from the host 190, but is not limited thereto. The display 195 may include, for example, an organic light-emitting diode (OLED) display device, a tiny LED display device, a micro LED display device, a quantum dot (QD) LED display device, a liquid crystal display (LCD) display device, a spliced ​​display device, a foldable display device, or an electronic paper display (EPD). However, the present disclosure is not limited thereto.

[0046] In one embodiment, the host 190 may include a processor 191 and a memory 192. The processor 191 may be, for example, a GPU, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor, a plurality of microprocessors, one or more microprocessors combined with a digital signal processor core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), any other kind of integrated circuit, a state machine, an advanced RISC machine (ARM)-based processor, etc. The memory 192 is coupled to the processor 191 and may be, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, a hard disk, any kind of non-transitory computer-readable medium, other similar devices, or a combination of these devices, and may be used to store a plurality of program codes or modules.

[0047] In an embodiment of the present disclosure, the processor 191 may access the modules or program codes stored in the memory 192 to implement the image display method proposed in the present disclosure, and the details thereof are described below. However, the present disclosure is not limited thereto.

[0048] Figure 1B FIG. 1 is a schematic diagram of a software structure of an image display method according to an embodiment of the present disclosure. Figure 1B, the software structure 100B of the image display method may include an application 110 (also referred to as an application layer), a processing layer 120, a sampling layer 130, and a hardware abstraction layer (HAL) 140. The application 110, the processing layer 120, the sampling layer 130, and the hardware abstraction layer 140 may be modules and / or program codes stored in the memory 192, but are not limited thereto. In addition, the processing layer 120, the sampling layer 130, and the hardware abstraction layer 140 may be part of a system. In one embodiment, the system may be an operating system, and the operating system may be Android, iOS, or other similar systems. However, the present disclosure is not limited thereto.

[0049] In one embodiment, the application 110 and the processing layer 120 may belong to a high-level programming layer, and the sampling layer 130 and the hardware abstraction layer 140 may belong to a low-level programming layer. In one embodiment, the programming language of the high-level programming layer may be a relatively high-level programming language, and the programming language of the relatively low-level programming layer may be a low-level (e.g., native) programming language. For example, the programming language of the high-level programming layer may be one of JAVA, Objective-C, and SWIFT, and the programming language of the low-level programming layer may be one of C and C++. However, the present disclosure is not limited thereto.

[0050] In one embodiment, in an Android framework, the application 110 may be an application or a view, the processing layer 120 may be a drawing scheduler layer or a display event receiver layer, the sampling layer 130 may be a SurfaceFlinger layer or a display synchronization model layer, and the hardware abstraction layer 140 may be a HWComposer layer. In another embodiment, in an iOS framework, the application 110 may be an application or a view, the processing layer 120 may be a CADisplayLink layer in an iOS framework, the sampling layer 130 may be a SurfaceFlinger layer or a core animation layer in an iOS framework, and the hardware abstraction layer 140 may be an IOSurface layer. However, the present disclosure is not limited thereto.

[0051] refer to Figure 1B, the application 110 may send a request signal RQS for a Vsync signal for rendering an image of the next frame to the processing layer 120. After the processing layer 120 receives the request signal RQS, the processing layer 120 may be configured to generate a local Vsync signal V_L and provide the local Vsync signal V_L to the application 110. Based on the local Vsync signal V_L, the application 110 may render an image of the next frame. That is, the Vsync signal (i.e., the local Vsync signal V_L) provided to the application 110 is locally generated within the high-level programming layer rather than within the low-level programming hierarchy layer. In other words, the local Vsync signal V_L is generated without reference to the hardware Vsync signal V_H. In this way, inter-process communication is not required to render the image of the next frame, thereby reducing the possibility of tearing effects and improving user experience.

[0052] Alternatively, although the parameters for calculating the local Vsync signal V_L do not exist (for example, immediately after the processor 191 is started) or are not accurate, the processing layer 120 may be configured to send an update signal UPD for updating the parameters for calculating the local Vsync signal V_L to the sampling layer 130. More specifically, after the sampling layer 130 receives the update signal UPD, the hardware Vsync signal V_H may be transmitted from the hardware abstraction layer 140 to the sampling layer 130. The hardware Vsync signal V_H may be generated by the hardware abstraction layer 140 based on the display 195 coupled to the host 190. Based on the hardware Vsync signal and the load of the processor 191, the sampling layer 130 may be configured to generate the software Vsync signal V_S. In addition, by calculating the average interval between a plurality of frames of the hardware Vsync signal V_H, the sampling layer 130 may be configured to generate a software period PRD for each frame. Based on the software Vsync signal V_S and the software cycle PRD, the processing layer 120 may be configured to generate a local Vsync signal V_L and send the local Vsync signal V_L to the application 110. That is, the sampling layer 130 may be configured to predict (or determine) the Vsync signals of multiple future frames (e.g., another next frame and subsequent frames) based on the software Vsync signal V_S and the software cycle PRD to render images of subsequent frames. More specifically, the software Vsync signal V_S may be used as the local Vsync signal V_L of the next frame and the local Vsync signal V_L of the subsequent frame, as may be calculated based on the software Vsync signal V_S and the software cycle PRD. In other words, after obtaining the parameters for calculating the local Vsync signal V_L, the Vsync signal provided to the application 110 may be generated locally. Therefore, delays caused by inter-process communication may be prevented, thereby reducing the possibility of tearing effects and improving user experience.

[0053] In addition, after the software Vsync signal V_S and the software cycle PRD are sent to the processing layer 120, at each of the subsequent frames, the sampling layer 130 may be configured to compare the hardware Vsync signal V_H of the current frame with the software Vsync signal V_S of the previous frame (i.e., the frame corresponding to the update signal UPD) to generate an offset value. For example, the offset value may be the difference between the timing of the hardware Vsync signal V_H and the timing of the software Vsync signal V_S, but is not limited thereto. It should be noted that although the offset value is greater than the threshold value, a tearing effect may occur in the image displayed by the display 195. That is, the threshold value is determined to prevent the tearing effect from occurring in the image displayed by the display 195. Therefore, in response to the offset value being greater than the threshold value, the sampling layer 130 may be configured to generate a new set of the software Vsync signal V_S and the software cycle PRD based on the hardware Vsync signal V_H of the current frame. Then, the new set of the software Vsync signal V_S and the software cycle PRD may be transmitted to the processing layer 120. Based on the new set of software Vsync signal V_S and software period PRD, the processing layer 120 can be configured to update (or actually calibrate) the local Vsync signal V_L of the current frame. In this way, inter-process communication occurs only when the calibration condition is triggered, thereby reducing the load of the processor 191, reducing the energy consumption of the host 190 and improving the performance of the host 190.

[0054] In one embodiment, in addition to updating the parameters when the calibration condition is triggered, the parameters may be updated periodically. In other words, at a predetermined interval, the sampling layer 130 may be configured to generate a new set of software Vsync signals V_S and software cycles PRD for the current frame. Similarly, based on the new set of software Vsync signals V_S and software cycles PRD, the processing layer 120 may be configured to update (or actually calibrate) the local Vsync signal V_L for the current frame. In this way, inter-process communication occurs only when a predetermined interval has passed, thereby reducing the load on the processor 191, reducing the energy consumption of the host 190, and improving the performance of the host 190.

[0055] It should be noted that although for convenience of explanation, the number of application programs 110 is Figure 1BAlthough depicted as one in the figure, the number of applications 110 may exceed one, and the same local Vsync signal V_L′ may be used to render images. In one embodiment, the first application and the second application may be stored in the memory 192 and executed by the processor 191. A first request signal for a first Vsync signal for rendering a first image of a next frame may be transmitted from the first application to the processing layer 120. A second request signal for a second Vsync signal for rendering a second image of a next frame may be transmitted from the second application to the processing layer 120. In addition, the first application may render the first image of the next frame based on the local Vsync signal V_L′. The second application may render the second image of the next frame based on the local Vsync signal V_L′. Therefore, the first application and the second application may render images using the same local Vsync signal V_L′, thereby reducing the load of the processor 191.

[0056] Figure 2 FIG. 1 is a schematic diagram of an exemplary pipeline of an image display method according to an embodiment of the present disclosure. Figure 1A to Figure 2 , the pipeline 200 can be Figure 1A 1B is an exemplary pipeline of a software structure 100B of an image display method in FIG. In one embodiment, the pipeline 200 may include an application layer 210, a display event receiver layer 220, a display synchronization model layer 230, and a hardware abstraction layer (HAL) 240. The application layer 210, the display event receiver layer 220, the display synchronization model layer 230, and the HAL 240 may be an embodiment of the application 110, the processing layer 120, the sampling layer 130, and the hardware abstraction layer 140, respectively, but are not limited thereto.

[0057] In one embodiment, in order to keep the screen of the display 195 up to date, the command "invalidate frame" may be executed to inform the user interface (UI) rendering engine to redraw the screen. In order to inform the UI rendering engine when it is safe to draw the next frame, the application layer 210 may send an event "request next Vsync" to the display event receiver layer 220 to request a Vsync signal for the next frame. For example, the method "next Vsync" in the display event receiver 220 may receive a request for the next Vsync signal. Then, the method "next Vsync" may generate a local Vsync signal V_L and send an event "VSYNC-app'" including the local Vsync signal V_L to the method "onDraw" in the application layer 210 to draw the content of the next frame. In this way, the screen of the display 195 may be kept up to date to display content or applications or views, or to repair rendering errors.

[0058] It should be noted that at the first frame (e.g., frame 1), the method "Next Vsync" may not be ready to calculate the local Vsync signal V_L. Therefore, in response to receiving the event "Request Next Vsync", the event "Request Vre-sync" may be sent to the display synchronization model layer 230. Next, the method "updateModel" may receive the event "Hardware Vsync" including the hardware Vsync signal V_H, and based on the hardware Vsync signal V_H, generate the software Vsync signal V_S and the software period PRD. In addition, the method "updateModel" may send the event "Update VSYNC-app" including the software Vsync signal V_S and the software period PRD to the method "Next Vsync". Based on the content of the event "Update VSYNC-app", the method "Next Vsync" may now be ready to provide the event "VSYNC-app'" to the application layer 210.

[0059] On the other hand, for frames after the first frame (e.g., frame 2, frame 3, ...), the parameters for calculating the local Vsync signal V_L have been updated. Therefore, the method "nextVsync" can directly provide the event "VSYNC-app'" to the application layer 210 without involving the display synchronization model layer 230 and the HAL 240.

[0060] In addition, when the calibration condition is triggered, the method "updateModel" in the display synchronization model layer 230 may send the event "Update VSYNC-app" to the method "Re-sync" in the display event receiver layer 220. The method "Re-sync" in the display event receiver layer 220 may provide a new set of software Vsync signals V_S and software periods PRD to the method "Next Vsync" in the display event receiver layer 220. Therefore, when the event "Request Next Vsync" is received again, the method "Next Vsync" is ready to provide the event "VSYNC-app'" containing the updated local Vsync signal V_L. In one embodiment, the calibration condition may include, for example, an offset from the hardware Vsync signal V_H to the software Vsync signal V_S greater than a threshold, a predetermined interval passed, or other conditions as required by the design, but is not limited thereto.

[0061] Figure 3 FIG. 1 is a schematic diagram of an exemplary flow chart of an exemplary pipeline according to an embodiment of the present disclosure. Figures 1A to 3 , the flowchart 300 may be Figure 2300 is an exemplary flowchart of the pipeline 200 in FIG. In one embodiment, the flowchart 300 may include steps S310 to S390, but is not limited thereto. In the flowchart 300, the display event receiver layer 220 may be a graphical user interface (GUI), and the display synchronization model layer 230 may be a system service. However, the present disclosure is not limited thereto.

[0062] In step S310, in order to request parameters for calculating the local Vsync signal V_L from the display synchronization model 230, an event "request next Vre-sync" may be sent from the display event receiver 220 to the display synchronization model layer 230. In step S320, the display synchronization source may be set to enable vertical resynchronization. In step S330, after receiving the hardware Vsync signal V_H, the event "update VSYNC-app" and the Vsync offset are calculated. The event "update VSYNC-app" may include the software Vsync signal V_S and the software period PRD. The Vsync offset may be the difference between the timing of the hardware Vsync signal V_H and the timing of the software Vsync signal V_S. In response to the Vsync offset being greater than the threshold, the application layer 210 may be notified. In step S340, the event "update VSYNC-app" (including the software period PRD) may be published (sent) to the display event receiver layer 220. In step S350 , after the display event receiver layer 220 receives the event “update VSYNC-app” (including the software cycle PRD), a callback function of the application layer 210 may be executed to update the timing of the software Vsync signal V_S and the software cycle PRD.

[0063] In step S360, when the application layer 210 intends to redraw the screen, the application layer 210 may provide (publish) a callback function to the display event receiver layer 220 to run on the next frame. In step S370, after the display event receiver layer 220 receives the callback function, the callback function waits to be triggered. In step S380, when the display event receiver layer 220 receives the event "update VSYNC-app" (including the software cycle PRD), the timing of the next Vsync signal and the event "VSYNC-app'" (including the local Vsync signal V_L) may be calculated. In step S390, when the next Vsync signal and the event "VSYNC-app'" are ready, the callback function may be triggered at the timing of the event "VSYNC-app'" to draw the next frame.

[0064] Figure 4 FIG. 1 is a schematic flow chart of an image display method according to an embodiment of the present disclosure. Figure 4 , the image display method 400 may include step S410, step S420 and step S430.

[0065] In step S410, a request signal RQS for a Vsync signal for rendering an image of a next frame is transmitted from the application 110 to the processing layer 120. It should be noted that the application 110 and the processing layer 120 belong to a high-level programming layer. In step S420, in response to receiving the request signal RQS by the processing layer 120, the processing layer 120 may be configured to generate a local Vsync signal V_L. In step S430, the application 110 may be configured to render an image of a next frame based on the local Vsync signal V_L. In addition, the implementation details of the image display method 400 may refer to FIGS. 1 to 430. Figure 3 The description of the embodiment of the present invention is sufficient to obtain sufficient teachings, suggestions and implementation examples, although the details are not redundantly described in this article. Therefore, the frame rate of the GPU and the refresh rate of the display can be synchronized to prevent tearing.

[0066] In one embodiment, the storage medium stores computer program code configured to enable a processor to execute a portion or all of the image display method 400 .

[0067] In summary, according to the image display method 400 and the host 190 , inter-process communication occurs only when a calibration condition is triggered, thereby reducing the load of the processor 191 , reducing the power consumption of the host 190 , and improving the performance of the host 190 .

[0068] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the above, it is intended that the present disclosure encompasses modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. An image display method, comprising: Transmitting a request signal of a vertical synchronization signal for rendering an image of a next frame from the application to a processing layer of the system; In response to receiving the request signal by the processing layer, the processing layer generates a local vertical synchronization signal without reference to a hardware vertical synchronization signal; as well as The application program renders the image of the next frame based on the local vertical synchronization signal.

2. The image display method according to claim 1, further comprising: In response to the start of the processor, a hardware vertical synchronization signal is transmitted from the hardware abstraction layer of the system to the sampling layer of the system; generating, by the sampling layer, a software vertical synchronization signal and a software cycle based on the hardware vertical synchronization signal and the load of the processor; and The local vertical synchronization signal is generated by the processing layer based on the software vertical synchronization signal and the software cycle.

3. The image display method according to claim 2, further comprising: The local vertical synchronization signal for rendering an image of another next frame is determined based on the software vertical synchronization signal and the software cycle.

4. The image display method according to claim 2, further comprising: By the sampling layer, the hardware vertical synchronization signal is compared with the software vertical synchronization signal to generate an offset value; as well as In response to the offset value being greater than a threshold, the sampling layer generates the software vertical synchronization signal and the software cycle based on the hardware vertical synchronization signal.

5. The image display method according to claim 4, further comprising: The threshold is determined to prevent the image displayed by the display from having a tearing effect.

6. The image display method according to claim 2, further comprising: The software vertical synchronization signal and the software cycle are generated by the sampling layer at predetermined intervals based on the hardware vertical synchronization signal.

7. The image display method according to claim 1, further comprising: Sending a callback function from the application to the processing layer; as well as In response to generating the local vertical synchronization signal, the image of the next frame is rendered by executing the callback function.

8. The image display method according to claim 1, further comprising: transmitting, from the first application to the processing layer, a first request signal for a first vertical synchronization signal for rendering a first image of the next frame; transmitting, from the second application to the processing layer, a second request signal for a second vertical synchronization signal for rendering a second image of the next frame; transmitting the local vertical synchronization signal from the processing layer to the first application and the second application; Rendering the first image of the next frame by the first application based on the local vertical synchronization signal; as well as The second application renders the second image of the next frame based on the local vertical synchronization signal.

9. A host, comprising: Memory, storing program codes; as well as A processor, coupled to the memory and configured to access the program code to perform the following operations: Transmitting a request signal of a vertical synchronization signal for rendering an image of a next frame from the application to a processing layer of the system; In response to receiving the request signal by the processing layer, the processing layer generates a local vertical synchronization signal without reference to a hardware vertical synchronization signal; as well as The application program renders the image of the next frame based on the local vertical synchronization signal.

10. The host of claim 9, wherein the processor further performs the following operations: In response to the start of the processor, a hardware vertical synchronization signal is transmitted from the hardware abstraction layer of the system to the sampling layer of the system; generating, by the sampling layer, a software vertical synchronization signal and a software cycle based on the hardware vertical synchronization signal and the load of the processor; and The local vertical synchronization signal is generated by the processing layer based on the software vertical synchronization signal and the software cycle.

11. The host of claim 10, wherein the processor further performs the following operations: The local vertical synchronization signal for rendering an image of another next frame is determined based on the software vertical synchronization signal and the software cycle.

12. The host of claim 10, wherein the processor further performs the following operations: By the sampling layer, the hardware vertical synchronization signal is compared with the software vertical synchronization signal to generate an offset value; and In response to the offset value being greater than a threshold, the sampling layer generates the software vertical synchronization signal and the software cycle based on the hardware vertical synchronization signal.

13. The host of claim 12, wherein the processor further performs the following operations: The threshold is determined to prevent the image displayed by the display from having a tearing effect.

14. The host of claim 10, wherein the processor further performs the following operations: The software vertical synchronization signal and the software cycle are generated by the sampling layer at predetermined intervals based on the hardware vertical synchronization signal.

15. The host of claim 9, wherein the processor further performs the following operations: Sending a callback function from the application to the processing layer; and In response to generating the local vertical synchronization signal, the image of the next frame is rendered by executing the callback function.

16. The host of claim 9, wherein the processor further performs the following operations: transmitting, from the first application to the processing layer, a first request signal for a first vertical synchronization signal for rendering a first image of the next frame; transmitting, from the second application to the processing layer, a second request signal for a second vertical synchronization signal for rendering a second image of the next frame; transmitting the local vertical synchronization signal from the processing layer to the first application and the second application; Rendering the first image of the next frame by the first application based on the local vertical synchronization signal; as well as The second application renders the second image of the next frame based on the local vertical synchronization signal.

17. A non-transitory computer readable medium storing a program to be loaded into a processor to perform the following steps: Transmitting a request signal of a vertical synchronization signal for rendering an image of a next frame from the application to a processing layer of the system; In response to receiving the request signal by the processing layer, generating, by the processing layer, a local vertical synchronization signal without reference to a hardware vertical synchronization signal; and The application program renders the image of the next frame based on the local vertical synchronization signal.

Images