A floating point operation method, device, medium and program product for neural network

Abstract

The present invention relates to the field of computer technology, and discloses a floating-point operation method, device, medium and program product of a neural network. The method comprises: obtaining each operand of a standard floating-point format input to a floating-point operator, and unpacking each operand according to the definition of the standard floating-point format to obtain an initial sign bit value, an initial exponent bit value and an initial mantissa bit value; performing floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value and a result mantissa bit value; generating an operation result in a custom floating-point format according to the result sign bit value, the result exponent bit value and the result mantissa bit value. The scheme of this embodiment, by using a custom floating-point format in which the mantissa part is represented by a binary complement code as the output format of the floating-point operation result, can avoid the extra logic and power consumption caused by data conversion or normalization processing, and can improve the efficiency of floating-point operation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a floating-point operation method, device, medium and program product of a neural network. Background Art

[0002] With the rapid development of artificial intelligence, deep learning has become the core driving force in many fields. However, the computational complexity of deep learning, especially the number of floating-point operations of neural networks, has become a major challenge in research and application. In deep learning, especially neural networks, floating-point operations directly determine the training and reasoning speed of the model, as well as the required computing resources. Therefore, floating-point operations have become the key to evaluating the performance of neural networks and optimizing models.

[0003] At present, the existing floating-point operation method of neural network usually adopts the IEEE binary floating-point operation standard, which is adopted by many central processing units and floating-point arithmetic units. However, in the addition and subtraction operations of the IEEE binary floating-point operation standard, the mantissa represented by the original code needs to be converted into a signed number according to the sign bit, and the corresponding signed number is calculated and then converted into an unsigned mantissa. When encountering a situation where a large number of addition / subtraction calculations need to be performed, a large number of conversions will cause unnecessary logic and power consumption. Secondly, when the input of the floating-point operation is in a low-precision format and the output is in a high-precision format, the output needs to be normalized when the existing floating-point operation standard format is used for output, which will also generate additional logic and power consumption. Summary of the invention

[0004] The present invention provides a floating-point operation method, device, medium and program product for a neural network, which can avoid the extra logic and power consumption caused by data conversion or normalization processing and improve the floating-point operation efficiency.

[0005] According to one aspect of the present invention, a floating-point operation method for a neural network is provided, comprising:

[0006] Obtaining each operand in a standard floating-point format input to a floating-point operator, and unpacking each operand according to the definition of the standard floating-point format to obtain an initial sign bit value, an initial exponent bit value, and an initial mantissa bit value;

[0007] Perform floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value and a result mantissa bit value;

[0008] According to the result sign bit value, the result exponent bit value and the result mantissa bit value, an operation result in a custom floating point format in which the mantissa part is represented by a binary complement code is generated.

[0009] According to another aspect of the present invention, there is provided a floating-point operation device for a neural network, comprising:

[0010] An operand unpacking module is used to obtain each operand in a standard floating-point format input to the floating-point operator, and unpack each operand according to the definition of the standard floating-point format to obtain an initial sign bit value, an initial exponent bit value, and an initial mantissa bit value;

[0011] A floating-point operation module, used for performing floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value and a result mantissa bit value;

[0012] The operation result generating module is used to generate the operation result in a custom floating point format with the mantissa part represented by binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the floating-point operation method of the neural network described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and the computer program is used to enable a processor to implement the floating-point operation method of a neural network described in any embodiment of the present invention when executed.

[0018] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the floating-point operation method of a neural network according to any embodiment of the present invention is implemented.

[0019] The technical solution of the embodiment of the present invention obtains each operand of the standard floating-point format of the input floating-point operator, and unpacks each operand according to the definition of the standard floating-point format to obtain the initial sign bit value, the initial exponent bit value and the initial mantissa bit value; performs floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain the result sign bit value, the result exponent bit value and the result mantissa bit value; generates the operation result of the custom floating-point format in which the mantissa part is represented by the binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value; by using the custom floating-point format in which the mantissa part is represented by the binary complement code as the output format of the floating-point operation result, the extra logic and power consumption caused by data conversion or normalization processing can be avoided, and the floating-point operation efficiency can be improved.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flowchart of a floating-point operation method of a neural network provided in Embodiment 1 of the present invention;

[0023] Figure 2 This is a schematic diagram of the definition of the FP32 floating point number format provided in Embodiment 1 of the present invention;

[0024] Figure 3 2 is a schematic diagram of defining a custom floating point format CFP65 according to Embodiment 1 of the present invention;

[0025] Figure 4 is a flowchart of addition and subtraction operations of FP64 input and CFP65 output provided according to the first embodiment of the present invention;

[0026] Figure 5 is a flowchart of addition and subtraction operations in which both input and output are in CFP65 format according to Embodiment 1 of the present invention;

[0027] Figure 6 is a flow chart of addition and subtraction operations of FP64 input and FP64 output provided according to the first embodiment of the present invention;

[0028] Figure 7is a flowchart of multiplication and division operations of FP32 input and FP64 output provided according to the first embodiment of the present invention;

[0029] Figure 8 It is a custom low-precision to high-precision conversion flow chart of FP32 input and CFP65 output provided according to the first embodiment of the present invention;

[0030] Fig. 9 is a structural schematic diagram of a floating-point operation device of a neural network provided according to Embodiment 2 of the present invention;

[0031] Fig.10 It is a schematic diagram of the structure of an electronic device for implementing the floating-point operation method of a neural network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Embodiment 1

[0035] Figure 1 A flowchart of a floating-point operation method of a neural network is provided for the first embodiment of the present invention. This embodiment is applicable to the case of performing floating-point operations in a neural network. The method can be executed by a floating-point operation device of the neural network. The floating-point operation device of the neural network can be implemented in the form of hardware and / or software. Typically, the floating-point operation device of the neural network can be configured in an electronic device, such as a computer device or a server. Figure 1 As shown, the method includes:

[0036] S110, obtaining each operand in a standard floating-point format input to a floating-point operator, and unpacking each operand according to a definition of the standard floating-point format to obtain an initial sign bit value, an initial exponent bit value, and an initial mantissa bit value.

[0037] The floating point arithmetic unit may include a floating point adder / subtractor and a floating point multiplier / divider. The standard floating point format may be the IEEE binary floating point arithmetic standard (IEEE754) format, typically including FP16 (Half precision floating point), FP32 (Single precision floating point number), and FP64 (Double precision floating point).

[0038] It should be noted that the IEEE754 standard floating-point number consists of a sign bit (S), an exponent bit (E), and a mantissa bit (M). Since the sign bit is fixed, the floating-point format can be determined by using the bit width of the exponent bit and the mantissa bit. For example, FP32 can be expressed as E8M23, that is, the exponent bit width is 8 bits (bits) and the mantissa bit width is 23 bits. Among them, the sign bit, when the value is 0, indicates that the number is positive, and when the value is 1, it indicates that the number is negative. The mantissa part is represented by the original code, and the mantissa bit implies the highest bit 1, that is, the actual value is 1.M. The exponent is represented by a shift code, and the shift code = exponent bit - offset. In FP32, the offset is 127, and the exponent represents the range of -127 to 128, and when the exponent is -127 or 128, that is, when the corresponding exponent bits are all 0 or all 1, it has a special meaning.

[0039] Secondly, the minimum absolute value of FP32 is when all the mantissa bits are 0 and the exponent value is -126, which is obtained when the corresponding shift code is 0000 0001. At this time, the value represented is 1×2 -126 The maximum absolute value of FP32 is obtained when all the mantissa bits are 1 and the exponent value is 127, that is, the corresponding shift code is 1111 1110, and the value represented at this time is 1.11…×2 127 . When the exponent is -127, the exponent bits are all 0 and the mantissa bits are all 0, indicating + / -0; when the exponent is -127, the exponent bits are all 0 and the mantissa bits are not all 0, indicating a non-normalized decimal, which is used to represent a number smaller than the minimum absolute value. At this time, the highest bit implied by the mantissa code is not 1, but 0; when the exponent is 128, the exponent bits are all 1 and the mantissa bits are all 0, indicating positive and negative infinity; when the exponent is 128, the exponent bits are all 1 and the mantissa bits are not all 0, indicating non-numeric values. The definition of the FP32 floating-point format can be as follows Figure 2 shown.

[0040] In this embodiment, after obtaining operands in the standard floating-point format, the operands can be unpacked according to the definition of the standard floating-point format to obtain the initial sign bit value, initial exponent bit value and initial mantissa bit value corresponding to each operand.

[0041] S120, performing a floating-point operation according to the initial sign bit value, the initial exponent bit value, and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value, and a result mantissa bit value.

[0042] Specifically, according to the floating-point operation type corresponding to the floating-point operator, for example, floating-point addition, floating-point subtraction, floating-point multiplication, and floating-point division, corresponding floating-point operations can be performed according to the initial sign bit value, initial exponent bit value, and initial mantissa bit value corresponding to each operand to obtain the result sign bit value, result exponent bit value, and result mantissa bit value.

[0043] S130. Generate a calculation result in a custom floating-point format in which the mantissa part is represented by a binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value.

[0044] Specifically, after obtaining the current result sign bit value, result exponent bit value and result mantissa bit value, the result sign bit value, result exponent bit value and result mantissa bit value can be packaged into the final operation result according to the definition of the custom floating-point format.

[0045] Among them, the definition of the custom floating point format CFP65 can be as follows Figure 3 As shown in the figure, the custom floating-point format can include an 11-bit exponent part and a 54-bit mantissa part. The exponent part is represented by the original binary code and is provided with an offset exponent. The offset is 1023, indicating a range of 0 to 2047. When the exponent part is all 0 or all 1, it has a special meaning. The highest bit (the 53rd bit) of the mantissa part is the sign bit (S), and a decimal point is set after the second highest bit (the 52nd bit) of the mantissa part. The mantissa part is represented by the binary complement code.

[0046] Optionally, the technical solution of this embodiment may further include:

[0047] According to the formula r = Mant × 2 {exp-1023-52} The actual value r corresponding to the custom floating-point format data is calculated, where Mant represents the parsed value of the mantissa, exp represents the parsed value of the exponent, and 1023 represents the offset of the exponent.

[0048] Among them, the mantissa part is parsed in the form of complement code, and the exponent part is parsed in the original code, and both need to be parsed into integers.

[0049] It should be noted that in the custom floating point format, the same number can be represented in multiple ways. For example, 1.0 can be represented as 0x0_ffd0_0000_0000_0000 (Exp=1023, Mant

[52] =1, and the rest are 0), that is, r=2 {52} ×2 {1023-1023-52} =1.0. Alternatively, it can be expressed as 0x1_0008_0000_0000_0000 (Exp=1024, Mant

[51] =1, and the rest are 0), i.e. r=2 {51} ×2 {1024-1023-52} = 1.0. In addition to the above two, there are other equivalent expressions for 1.0, which will not be expanded here.

[0050] In addition, for 0.0, CFP65 only allows the use of all-0 encoding, which is the representation method; in addition, the number -0.0 cannot be represented in CFP65. Moreover, the CFP65 format can also represent non-numbers and infinity. When Exp is 11'h7ff (all 1s), and Mant is not 0 except S, it represents non-number; when Exp is 11'h7ff (all 1s), and Mant is 0 except S, it represents infinity. When S is 1, it represents negative infinity, and when it is 0, it represents positive infinity.

[0051] The constraints of the custom floating-point format may include:

[0052] If the parsed value of the exponent part of the current data is 2046, the highest digit value of the mantissa part is 1 and the other digit values ​​are 0, the current data is determined to be an illegal combination;

[0053] Also, if the parsed value of the exponent part of the current data is 0, the value of the least significant bit of the mantissa part is always 0.

[0054] It should be noted that in order to be compatible with the representation range of FP64, the custom floating point format needs to set certain constraints. Specifically, if the parsed value of the exponent part of the current data is 2046, the highest digit of the mantissa is 1 and the other digits are 0, that is, 0x1_FFA0_0000_0000_0000 (Exp=2046,Mant

[53] =1,the rest are 0) is an illegal combination, because the value is r=-2 {53} ×2 {2046-1023-52} =-2 {1024} , which is beyond the range of FP64.

[0055] In addition, when Exp=0, Mant[0] is always 0. This is because in FP64, when EXP=0 and the mantissa bits are not all 0, it indicates a non-standard number. At this time, the real exponent value is -1022 (1-1023), and the implicit number 1.M becomes 0.M, and the actual significant digit becomes 52 bits. In the CFP65 format, when Exp=0, the real exponent value is -1023 (0-1023). In order to match the non-standard sensitivity of FP64, when Exp=0, the mantissa bits need to be shifted left by 1 bit, so the 0th bit is fixed to 0. Based on the above constraints, CFP65 can equivalently express all value ranges of FP64 except -0, and the CFP65 value table can be shown in Table 1.

[0056] Table 1 CFP65 value table

[0057] Numeric Exponent Mantissa Positive Infinity 11'h7ff 0 Maximum positive number 11'h7fe {1'b0,53{1′b1}} 0 0 0 Maximum negative number 11'h7fe {1'b1,53'b1} Negative Infinity 11'h7ff {1'b1,53'b0} Non-Number 11'h7ff Non-zero

[0058] It should be noted that the custom floating-point format proposed in this embodiment is not limited to the one with an exponent width of 11 bits and a mantissa width of 54 bits. The same type of format can be applied to any floating-point format with an exponent width or a mantissa width greater than or equal to 2. In other words, as long as the exponent width or the mantissa width in the standard floating-point format is greater than or equal to 2 bits, the corresponding custom floating-point format can be set.

[0059] The technical solution of the embodiment of the present invention obtains each operand of the standard floating-point format of the input floating-point operator, and unpacks each operand according to the definition of the standard floating-point format to obtain the initial sign bit value, the initial exponent bit value and the initial mantissa bit value; performs floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain the result sign bit value, the result exponent bit value and the result mantissa bit value; generates the operation result of the custom floating-point format in which the mantissa part is represented by the binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value; by using the custom floating-point format in which the mantissa part is represented by the binary complement code as the output format of the floating-point operation result, the extra logic and power consumption caused by data conversion or normalization processing can be avoided, and the floating-point operation efficiency can be improved.

[0060] In an optional implementation of this embodiment, performing a floating-point operation according to the initial sign bit value, the initial exponent bit value, and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value, and a result mantissa bit value may include:

[0061] When the floating-point operator is a floating-point adder and the standard floating-point format is a 64-bit double-precision floating-point format, conditional negation, mantissa order, mantissa addition calculation, initial normalization, rounding and re-normalization are performed in sequence according to the initial sign bit value, initial exponent bit value and initial mantissa bit value of the two operands to obtain the result sign bit value, result exponent bit value and result mantissa bit value.

[0062] In a specific example, the addition and subtraction operations of FP64 input and CFP65 output can be as follows: Figure 4 As shown. Specifically, first, the two operands X and Y input to the floating-point adder are unpacked, and the unpacking includes separating the sign bit, exponent bit, and mantissa bit of each operand, and restoring the hidden 1 to obtain the initial sign bit value, initial exponent bit value, and initial mantissa bit value of each operand. Then, a conditional negation operation is performed to provide complement logic for one of the two operands. If the two operands have the same sign, the common sign can be ignored during the addition process and then added to the result; if -X is a negative operand, and the complement logic is only for the positive operand Y, Y will be complemented and the negative sign of -X will be ignored.

[0063] Furthermore, the mantissa is aligned, and according to the difference between the two exponents, the small order is aligned to the large order, and the mantissa bit values ​​after the alignment are added to obtain the calculation result. After that, the calculation result is normalized, that is, the calculation result is normalized to obtain a normalized calculation result, and the normalized calculation result is rounded, and the normalized shift and exponent adjustment are performed again to obtain the result mantissa bit value. If the output is in FP64 format at this time, when the obtained sign is a negative number, the complement must be performed to form a signed output, and this step is not required if the output is in CFP65 format. Finally, the result sign bit value, the result exponent bit value, and the result mantissa bit value can be packaged into CFP65 format to facilitate subsequent addition / subtraction calculations.

[0064] Optionally, after generating the operation result in a custom floating-point format in which the mantissa part is represented by a binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value, the method may further include:

[0065] The operation results of each custom floating-point format are accumulated and floating-point operation is performed to obtain a target operation result in the custom floating-point format, and the target operation result in the custom floating-point format is format-converted to obtain a floating-point operation result in a 64-bit double-precision floating-point format.

[0066] In this embodiment, after obtaining the CFP65 format operation result output by each floating-point adder, each CFP65 format operation result can be accumulated to obtain the target operation result in the CFP65 format; further, the target operation result can be converted into a floating-point operation result in the FP64 format.

[0067] In a specific example, the addition and subtraction operation flow with both input and output in CFP65 format can be as follows: Figure 5 Compared with the addition and subtraction operations with FP64 input format, the conversion between unsigned and signed numbers during the calculation process, that is, the conditional negation step, can be avoided.

[0068] It should be noted that, compared with the prior art, the floating point data format scheme proposed in this embodiment effectively reduces the complexity brought by the IEEE754 standard in floating point calculations (especially addition and subtraction). By using the CFP65 format during the calculation process and converting it to the IEEE 754 format after the calculation is completed, not only can the complexity of the calculation be reduced, but also the standard scheme design can be compatible.

[0069] Among them, in the IEEE754 standard, a large number of conversions between unsigned numbers and signed numbers in the accumulation or subtraction operations will waste logic and power consumption. The addition and subtraction operation process of FP64 input and FP64 output can be as follows: Figure 6 In this embodiment, the mantissa of the CFP65 format is directly represented by the complement code, so that the addition operation can be directly performed to obtain the result. Moreover, since the CFP65 format is compatible with the IEEE754 format, the operation result can also be converted into FP64 output. Figure 6 , Figure 4 The addition and subtraction operation flow of FP64 input and CFP65 output shown in the figure optimizes the output conditional negative step. Figure 5 The input CFP65 and output CFP65 addition and subtraction operation flow shown in the figure optimizes the input and output conditional negation steps.

[0070] In another optional implementation of this embodiment, performing a floating-point operation according to the initial sign bit value, the initial exponent bit value, and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value, and a result mantissa bit value may include:

[0071] When the floating-point operator is a floating-point multiplier and the standard floating-point format is a 32-bit single-precision floating-point format, the initial sign bit values ​​of the two operands are XORed to obtain a result sign bit value, the initial exponent bit values ​​of the two operands are added to obtain a result exponent bit value, and the initial mantissa bit values ​​of the two operands are multiplied to obtain a result mantissa bit value.

[0072] It should be noted that in the process of performing low-precision to high-precision operations, such as obtaining FP64 results from operations between FP32, data using the IEEE754 standard often needs to be normalized, such as Figure 7 The multiplication and division process of FP32 input and FP64 output. By adopting the CFP65 format of this embodiment, the normalization process after calculation can be omitted, thereby saving logic and power consumption. The custom low-precision to high-precision conversion process of FP32 input and CFP65 output is as follows: Figure 8 shown.

[0073] The purpose of the present invention is to propose a practical floating point format that can effectively reduce the computational complexity and be compatible with the IEEE754 standard in the process of floating point addition and subtraction operations. In the CFP65 format proposed in this embodiment, the exponent part has an offset, and the mantissa part is a fixed-point signed number, which can be compatible with all values ​​of the IEEE754 standard except -0. Moreover, in this format, the same number can be expressed in multiple ways, which can improve the flexibility of data expression.

[0074] Embodiment 2

[0075] Fig. 9 This is a schematic diagram of the structure of a floating-point operation device for a neural network provided in the second embodiment of the present invention. Fig. 9 As shown, the device includes: an operand unpacking module 210, a floating point operation module 220 and an operation result generation module 230; wherein,

[0076] The operand unpacking module 210 is used to obtain each operand in the standard floating point format input to the floating point operator, and unpack each operand according to the definition of the standard floating point format to obtain an initial sign bit value, an initial exponent bit value and an initial mantissa bit value;

[0077] A floating-point operation module 220, configured to perform floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value and a result mantissa bit value;

[0078] The operation result generating module 230 is used to generate an operation result in a custom floating point format in which the mantissa part is represented by a binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value.

[0079] The technical solution of the embodiment of the present invention obtains each operand of the standard floating-point format of the input floating-point operator, and unpacks each operand according to the definition of the standard floating-point format to obtain the initial sign bit value, the initial exponent bit value and the initial mantissa bit value; performs floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain the result sign bit value, the result exponent bit value and the result mantissa bit value; generates the operation result of the custom floating-point format in which the mantissa part is represented by the binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value; by using the custom floating-point format in which the mantissa part is represented by the binary complement code as the output format of the floating-point operation result, the extra logic and power consumption caused by data conversion or normalization processing can be avoided, and the floating-point operation efficiency can be improved.

[0080] Optionally, the custom floating-point format includes an 11-bit exponent part and a 54-bit mantissa part, the exponent part is represented by binary code, the highest bit of the mantissa part is the sign bit, and a decimal point is set after the second highest bit of the mantissa part.

[0081] Optional, custom floating-point format constraints include:

[0082] If the parsed value of the exponent part of the current data is 2046, the highest digit value of the mantissa part is 1 and the other digit values ​​are 0, the current data is determined to be an illegal combination;

[0083] Also, if the parsed value of the exponent part of the current data is 0, the value of the least significant bit of the mantissa part is always 0.

[0084] Optionally, the floating point computing device of the neural network further includes:

[0085] The actual value calculation module is used to calculate the actual value according to the formula r = Mant × 2 {exp-1023-52} The actual value r corresponding to the custom floating-point format data is calculated, where Mant represents the parsed value of the mantissa, exp represents the parsed value of the exponent, and 1023 represents the offset of the exponent.

[0086] Optionally, the floating-point operation module 220 is specifically used to perform conditional negation, mantissa order calculation, mantissa addition calculation, initial normalization, rounding and re-normalization in sequence according to the initial sign bit value, initial exponent bit value and initial mantissa bit value of the two operands when the floating-point operator is a floating-point adder and the standard floating-point format is a 64-bit double-precision floating-point format, so as to obtain the result sign bit value, result exponent bit value and result mantissa bit value.

[0087] Optionally, the floating point computing device of the neural network further includes:

[0088] The calculation result format conversion module is used to perform cumulative floating-point calculations on the calculation results of each custom floating-point format to obtain a target calculation result in the custom floating-point format, and to perform format conversion on the target calculation result in the custom floating-point format to obtain a floating-point calculation result in a 64-bit double-precision floating-point format.

[0089] Optionally, the floating-point operation module 220 is specifically used to perform an XOR operation on the initial sign bit values ​​of the two operands to obtain a result sign bit value, and to perform an addition operation on the initial exponent bit values ​​of the two operands to obtain a result exponent bit value, and to perform a multiplication operation on the initial mantissa bit values ​​of the two operands to obtain a result mantissa bit value when the floating-point operator is a floating-point multiplier and the standard floating-point format is a 32-bit single-precision floating-point format.

[0090] The floating-point operation device of the neural network provided in the embodiment of the present invention can execute the floating-point operation method of the neural network provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0091] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0092] Embodiment 3

[0093] Fig.10 A schematic diagram of the structure of an electronic device 30 that can be used to implement an embodiment of the present invention is shown. The electronic device 30 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 30 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0094] like Fig.10As shown, the electronic device 30 includes at least one processor 31, and a memory connected to the at least one processor 31, such as a read-only memory (ROM) 32, a random access memory (RAM) 33, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 31 can perform various appropriate actions and processes according to the computer program stored in the read-only memory 32 or the computer program loaded from the storage unit 38 to the random access memory 33. In the RAM 33, various programs and data required for the operation of the electronic device 30 can also be stored. The processor 31, the ROM 32 and the RAM 33 are connected to each other through a bus 34. The input / output (I / O) interface 35 is also connected to the bus 34.

[0095] A number of components in the electronic device 30 are connected to the I / O interface 35, including: an input unit 36, such as a keyboard, a mouse, etc.; an output unit 37, such as various types of displays, speakers, etc.; a storage unit 38, such as a disk, an optical disk, etc.; and a communication unit 39, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 39 allows the electronic device 30 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0096] The processor 31 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 31 include, but are not limited to, a central processing unit, a graphics processing unit, various special artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any appropriate processors, controllers, microcontrollers, etc. The processor 31 performs the various methods and processes described above, such as floating-point arithmetic methods of neural networks.

[0097] In some embodiments, the floating-point operation method of the neural network may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 38. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 30 via the ROM 32 and / or the communication unit 39. When the computer program is loaded into the RAM 33 and executed by the processor 31, one or more steps of the floating-point operation method of the neural network described above may be performed. Alternatively, in other embodiments, the processor 31 may be configured to execute the floating-point operation method of the neural network in any other appropriate manner (e.g., by means of firmware).

[0098] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays, application specific integrated circuits, application specific standard products, systems on a chip, load programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0099] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0100] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0101] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device 30 having: a display device (e.g., a cathode ray tube or a liquid crystal display) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the electronic device 30. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0102] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area networks, wide area networks, blockchain networks, and the Internet.

[0103] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other. The server may be a cloud server.

[0104] This embodiment may also include a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the floating-point operation method of the neural network provided by any embodiment of the present invention.

[0105] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0106] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A floating point operation method for a neural network, characterized in that: include: Obtaining each operand in a standard floating-point format input to a floating-point operator, and unpacking each operand according to the definition of the standard floating-point format to obtain an initial sign bit value, an initial exponent bit value, and an initial mantissa bit value; Perform floating-point operation according to the initial sign bit value, the initial exponent bit value and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value and a result mantissa bit value; According to the result sign bit value, the result exponent bit value and the result mantissa bit value, an operation result in a custom floating point format in which the mantissa part is represented by a binary complement code is generated.

2. The method according to claim 1, characterized in that The custom floating-point format includes an 11-bit exponent part and a 54-bit mantissa part. The exponent part is represented by binary code, the highest bit of the mantissa part is the sign bit, and a decimal point is set after the second highest bit of the mantissa part.

3. The method according to claim 2, characterized in that Constraints on custom floating-point formats include: If the parsed value of the exponent part of the current data is 2046, the highest digit value of the mantissa part is 1 and the other digit values ​​are 0, the current data is determined to be an illegal combination; Also, if the parsed value of the exponent part of the current data is 0, the value of the least significant bit of the mantissa part is always 0.

4. The method according to claim 1, characterized in that: Also includes: According to the formula r = Mant × 2 {exp-1023-52} The actual value r corresponding to the custom floating-point format data is calculated, where Mant represents the parsed value of the mantissa, exp represents the parsed value of the exponent, and 1023 represents the offset of the exponent.

5. The method according to claim 1, characterized in that Performing a floating-point operation according to the initial sign bit value, the initial exponent bit value, and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value, and a result mantissa bit value, including: When the floating-point operator is a floating-point adder and the standard floating-point format is a 64-bit double-precision floating-point format, conditional negation, mantissa order, mantissa addition calculation, initial normalization, rounding and re-normalization are performed in sequence according to the initial sign bit value, initial exponent bit value and initial mantissa bit value of the two operands to obtain the result sign bit value, result exponent bit value and result mantissa bit value.

6. The method according to claim 5, characterized in that After generating the operation result in a custom floating-point format in which the mantissa part is represented by a binary complement code according to the result sign bit value, the result exponent bit value and the result mantissa bit value, the method further includes: The operation results of each custom floating-point format are accumulated and floating-point operation is performed to obtain a target operation result in the custom floating-point format, and the target operation result in the custom floating-point format is format-converted to obtain a floating-point operation result in a 64-bit double-precision floating-point format.

7. The method according to claim 1, characterized in that Performing a floating-point operation according to the initial sign bit value, the initial exponent bit value, and the initial mantissa bit value to obtain a result sign bit value, a result exponent bit value, and a result mantissa bit value, including: When the floating-point operator is a floating-point multiplier and the standard floating-point format is a 32-bit single-precision floating-point format, the initial sign bit values ​​of the two operands are XORed to obtain a result sign bit value, the initial exponent bit values ​​of the two operands are added to obtain a result exponent bit value, and the initial mantissa bit values ​​of the two operands are multiplied to obtain a result mantissa bit value.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor, and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the floating-point operation method of the neural network according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is used to enable a processor to implement the floating-point operation method of a neural network according to any one of claims 1 to 6 when executed.

10. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the floating-point operation method of the neural network according to any one of claims 1 to 6.

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