Event processing method, device, electronic device and computer-readable storage medium

Abstract

The present disclosure provides an event processing method, device, electronic device and computer-readable storage medium, the method comprising: obtaining the discrete events to be processed of each processing unit in the chip system, wherein each discrete event to be processed carries a timestamp; storing the discrete events to be processed of different event processing clusters into the event queues of the corresponding event processing clusters, wherein one event processing cluster corresponds to one event queue; using different sub-threads to process each event queue in parallel, wherein the discrete events to be processed are read from the event queue to the sub-thread according to the timestamp, and the sub-thread is used to execute the discrete events to be processed. Through the above technical solution, it can be avoided that when processing discrete events, all events can only be processed serially in a single thread, resulting in low processing efficiency.

Description

Technical Field

[0001] The present disclosure relates to the technical field of event processing, and in particular to an event processing method, device, electronic device and computer-readable storage medium. Background Art

[0002] Computer architecture simulation technology is a means of using software methods to virtualize computer system hardware, run real applications on the simulator, and output statistical data of applications or virtual machines for testers to analyze. Simulation technology runs through the entire design and development cycle of computer systems. Simulators are very useful tools in the fields of computer science and information technology. They make many complex and costly tasks more feasible. With the development of technology, the accuracy and functionality of simulators are also constantly improving.

[0003] In the prior art, when conducting computer architecture research or performance tuning, a large number of simulation experiments are often required. Improving the simulation speed of the simulator can shorten the experimental cycle and enable researchers to obtain results faster. However, when simulating the execution of discrete events, all events can only be processed serially in a single thread. This makes it impossible to fully utilize the computer's multi-core resources when simulating a hierarchical multi-core system, resulting in low simulation efficiency. Summary of the invention

[0004] The embodiments of the present disclosure provide an event processing method, device, electronic device and computer-readable storage medium, which can avoid the situation where all events can only be processed serially in a single thread when processing discrete events, resulting in low processing efficiency.

[0005] According to one aspect of the present disclosure, an event processing method is provided for testing a chip system, wherein the chip system includes multiple event processing clusters, and the event processing cluster includes multiple processing units. The method includes: obtaining discrete events to be processed of each processing unit in the chip system, wherein each discrete event to be processed carries a timestamp; storing the discrete events to be processed of different event processing clusters into event queues of corresponding event processing clusters, respectively, wherein one event processing cluster corresponds to one event queue; and using different sub-threads to process each event queue in parallel, wherein the discrete events to be processed are read from the event queue to the sub-thread according to the timestamp, and the discrete events to be processed are executed by using the sub-thread.

[0006] Optionally, storing the to-be-processed discrete events of different event processing clusters into the event queues of corresponding event processing clusters respectively includes: obtaining queue index information of the event processing cluster; and storing the to-be-processed discrete events in the event processing cluster into the event queues of corresponding event processing clusters according to the queue index information.

[0007] Optionally, reading the to-be-processed discrete event from the event queue to the sub-thread according to the timestamp, and using the sub-thread to execute the to-be-processed discrete event, includes: obtaining the current running time; matching the current running time with the timestamp of the to-be-processed discrete event; when the current running time matches the timestamp, reading the to-be-processed discrete event corresponding to the timestamp from the event queue to the sub-thread corresponding to the event queue; and executing the to-be-processed discrete event through the sub-thread.

[0008] Optionally, when there are multiple sub-threads corresponding to the event queue, executing the processing of the discrete event to be processed by the sub-thread includes: processing the discrete event to be processed in parallel by the multiple sub-threads.

[0009] Optionally, reading the to-be-processed discrete events corresponding to the timestamp from the event queue to the sub-thread corresponding to the event queue includes: determining the number of the to-be-processed discrete events corresponding to the timestamp to obtain the number of to-be-processed events; splitting the sub-thread from a preset main thread according to the number of to-be-processed events; and reading the to-be-processed discrete events into the sub-thread.

[0010] Optionally, when there is one sub-thread corresponding to the event queue, executing the processing of the discrete events to be processed by the sub-thread includes: executing the corresponding discrete events to be processed respectively by the sub-thread.

[0011] Optionally, the sub-thread is split from a preset main thread, and after reading the discrete event to be processed from the event queue to the sub-thread according to the timestamp, and using the sub-thread to execute the discrete event to be processed, the method also includes: obtaining a synchronization time node of the main thread; and synchronizing the main thread and the sub-thread according to the synchronization time node.

[0012] Optionally, each of the discrete events to be processed also carries a priority. After the discrete events to be processed of different event processing clusters are respectively stored in the event queues of the corresponding event processing clusters, the method further includes: comparing the priorities of the discrete events to be processed in the event queues to obtain priority sorting information; determining the execution order of the discrete events to be processed according to the priority sorting information; reading the corresponding discrete events to be processed from the event queue to the sub-thread according to the execution order, and using the sub-thread to execute the discrete events to be processed.

[0013] According to one aspect of the present disclosure, an event processing device is proposed, which is used to test a chip system, wherein the chip system includes multiple event processing clusters, and the event processing cluster includes multiple processing units. The event processing device includes: an acquisition unit, used to acquire the to-be-processed discrete events of each of the processing units in the chip system, wherein each of the to-be-processed discrete events carries a timestamp; a transfer unit, used to store the to-be-processed discrete events of different event processing clusters into the event queues of the corresponding event processing clusters, respectively, wherein one event processing cluster corresponds to one event queue; an execution unit, used to process each of the event queues in parallel using different sub-threads, wherein the to-be-processed discrete events are read from the event queue to the sub-thread according to the timestamp, and the to-be-processed discrete events are executed using the sub-thread.

[0014] According to one aspect of the present disclosure, an electronic device is proposed, which includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein the program implements the event processing method described above when executed by the processor.

[0015] According to one aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the event processing method as described above.

[0016] The present disclosure proposes an event processing method, device, electronic device and computer-readable storage medium, the method comprising: obtaining the discrete events to be processed of each processing unit in the chip system, wherein each of the discrete events to be processed carries a timestamp; then storing the discrete events to be processed of different event processing clusters into the event queues of the corresponding event processing clusters, wherein one event processing cluster corresponds to one event queue; finally, using different sub-threads to process each event queue in parallel, wherein the process of using different sub-threads to process each event queue in parallel includes: reading the discrete events to be processed from the event queue to the sub-thread according to the timestamp, and using the sub-thread to execute the discrete events to be processed. In the present disclosure, first, the discrete events to be processed generated by each processing unit in the chip system are collected; then, the discrete events to be processed in an event processing cluster are stored in an event queue corresponding to the event processing cluster; then, the sub-threads corresponding to each event queue can parallelly process the discrete events to be processed in the event queue according to the timestamp carried by each discrete event to be processed, and different sub-threads are independent of each other in the process of executing the discrete events to be processed. Therefore, the processing efficiency of discrete events can be greatly accelerated, and the testing efficiency of the chip system can be accelerated, avoiding the problem of low processing efficiency caused by all events being processed serially in a single thread when processing discrete events as in the past.

[0017] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by practicing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0019] Figure 1 is a system architecture diagram of a chip system tested by the event processing method of an embodiment of the present disclosure;

[0020] Figure 2 is a schematic diagram of the construction of an event processing cluster according to an embodiment of the present disclosure;

[0021] Figure 3 is a main flow chart of an event processing method according to an embodiment of the present disclosure;

[0022] Figure 4 yes Figure 3A sub-flowchart of step S202;

[0023] Figure 5 yes Figure 3 A sub-flow chart of step S203;

[0024] Figure 6 yes Figure 5 A sub-flowchart of step S404;

[0025] Figure 7 It is a schematic diagram of multiple sub-threads processing discrete events to be processed in the event queue;

[0026] Figure 8 yes Figure 5 A sub-flowchart of step S403;

[0027] Fig. 9 yes Figure 5 Another sub-flow chart of step S404;

[0028] Fig.10 It is a schematic diagram of a single sub-thread processing discrete events to be processed in the event queue;

[0029] Fig.11 It is a sub-flow chart after executing step S203;

[0030] Fig.12 It is a sub-flow chart after executing step S202;

[0031] Fig.13 is a flow chart of processing events generated by a chip system according to an embodiment of the present disclosure;

[0032] Fig.14 is a flow chart of processing events generated by a functional module according to an embodiment of the present disclosure;

[0033] Fig.15 is a schematic diagram of the structure of an event processing device proposed according to an embodiment of the present disclosure;

[0034] Fig.16 It is a schematic diagram of the structure of an electronic device proposed according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are not used to limit the present disclosure.

[0036] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0037] Central Processing Unit (CPU): The CPU is the computing and control core of the computer system and is the final execution unit for information processing and program running. The CPU is the brain of the computer, responsible for executing program instructions and processing data. The CPU is used to execute program instructions, process data operations and control other hardware components of the computer. Among them, the core is the physical unit of the CPU, which can execute instructions independently. The thread is the smallest unit that the operating system can schedule, and modern CPUs support multi-threading technology. The CPU generates heat during operation and requires a cooling system to keep it working at a safe temperature. Among them, the CPU includes an arithmetic logic unit, a control unit, registers and cache; the arithmetic logic unit is responsible for performing all arithmetic and logical operations; the control unit is used to fetch instructions from the memory, determine the order of instructions, and control other hardware components; the register is a small storage area inside the CPU, which is used to store instructions and data to speed up processing; the cache is a fast memory inside the CPU, which is used to temporarily store frequently accessed data.

[0038] Chip: A chip, also known as an integrated circuit, is a miniature electronic device or component that integrates many electronic components on semiconductor materials to achieve specific electronic functions. Chips can be divided into analog chips, digital chips, and mixed-signal chips; analog chips are used to process analog signals, such as sound and light; digital chips are used to process digital signals, such as computer processors; mixed-signal chips are used to process analog and digital signals at the same time. Chips are widely used in many fields such as computers, smart phones, automobiles, medical equipment, and industrial control systems.

[0039] Thread: A thread is the smallest unit that the operating system can schedule operations. A thread is contained in a process and is the actual operating unit in the process. A thread itself does not own system resources, but only has a few resources that are essential for operation. However, a thread can share all the resources owned by the process with other threads belonging to the same process. Threads are lightweight, and the cost of creating and destroying them is much less than that of processes. Threads within the same process can share the resources of the process, such as the memory address space. Threads can improve the concurrency of programs and allow multiple threads to run simultaneously. Threads are the basic units of independent scheduling and dispatching, and each thread has its own program counter, register set, etc. Threads have their own program counter, registers, and stack, etc., and can share the memory space of the process. The creation and management of threads is an important concept in modern operating systems and programming languages, allowing programs to perform multitasking in a more efficient way; on multi-core processors, threads can be scheduled by the operating system to different processors for parallel execution, thereby improving the execution efficiency of the program. Thread programming needs to consider synchronization and mutual exclusion issues to avoid race conditions and deadlocks.

[0040] Event queue: An event queue is a first-in-first-out data structure that stores a series of events waiting to be processed by the system; each event usually contains information such as event type, timestamp, event source, and event data. In the event-driven programming model, the event queue is used to store all pending events. The program will take events from the queue and execute the corresponding callback function or processing logic according to the event type. Event queues can be used to process tasks asynchronously, putting time-consuming operations into a queue and then processing them by a dedicated thread or process to avoid blocking the main thread. In a multi-threaded environment, event queues can be used to synchronize operations between different threads to ensure that events are processed in the correct order. Among them, event queues can be implemented using data structures such as arrays, linked lists, or priority queues. The specific choice depends on the requirements of event processing, such as whether events need to be processed according to priority. In some systems, the event queue may contain an event distributor, which is responsible for taking events from the queue and distributing them to the corresponding event handlers. Event queues are an indispensable part of modern software architecture. They improve the responsiveness and modularity of programs and enable events to be processed efficiently and orderly.

[0041] Event: An event refers to an action or occurrence that can be detected in a system. An event is an instantaneous occurrence in the system, which usually results in a state change or an action that needs to be responded to. It can be a user operation, system behavior, external signal, etc. Among them, events can be roughly divided into user events, system events, timed events, and application events; user events can include mouse clicks, keyboard input, and touch screen, etc.; system events can include file reading and writing completion, network connection establishment, and hardware interruption, etc.; timed events can include timer expiration, periodic reports, etc.; application time can include state changes within the application, events triggered by business logic, etc. Event processing is often asynchronous, which means that the generation and processing of events can not block other parts of the program.

[0042] In the prior art, when conducting computer architecture research or performance tuning, a large number of simulation experiments are often required. Improving the simulation speed of the simulator can shorten the experimental cycle and enable researchers to obtain results faster. However, when simulating the execution of discrete events, all events can only be processed serially in a single thread. This makes it impossible to fully utilize the computer's multi-core resources when simulating a hierarchical multi-core system, resulting in low simulation efficiency.

[0043] Based on this, the present disclosure proposes an event processing method, device, electronic device and computer-readable storage medium, which can avoid the situation where all events can only be processed serially in a single thread when processing discrete events, resulting in low processing efficiency.

[0044] Description of the system architecture of the present disclosure embodiment

[0045] Figure 1It is a system architecture diagram of the chip system 100 tested by the event processing method of the embodiment of the present disclosure. The chip system 100 is a hierarchical structure. The chip system 100 includes a subsystem control module 110 and multiple subsystems 120. Each subsystem 120 includes a control logic processing unit 130 and multiple secondary subsystems 140, and each secondary subsystem 140 includes an event processing cluster 150 and a functional module 160. Each subsystem 120 is connected to the subsystem control module 110, and each secondary subsystem 140 inside the subsystem 120 is connected to the control logic processing unit 130 of the subsystem 120. Among them, the chip system 100 may include multiple subsystems 120, and the number of subsystems 120 is not limited; a subsystem 120 may also include multiple secondary subsystems 140, and the number of secondary subsystems 140 is not limited. Among them, the subsystem control module 110 serves as a bridge connecting different subsystems 120, and can provide high-speed data transmission and interface management functions. The control logic processing unit 130 in the subsystem 120 can provide physical connections and data transmission channels between the secondary subsystems 140 to ensure the coordinated operation of the entire chip system 100. In addition, the secondary subsystem 140 in the embodiment of the present disclosure can be a computing unit, which is a basic unit for performing computing tasks.

[0046] It is worth noting that the functional module 160 may include a scalar unit, a vector unit, a copy engine and a tensor core processing unit, etc.; wherein the scalar unit is used to perform scalar operations, the vector unit is used to perform vector operations, the copy engine is used to perform copy operations, and the tensor core processing unit is used to perform matrix multiplication and accumulation operations.

[0047] Figure 2It is a schematic diagram of the structure of the event processing cluster of the embodiment of the present disclosure. The chip system 100 includes multiple event processing clusters 150, each event processing cluster 150 includes multiple processing units 151, each processing unit 151 in the event processing cluster 150 can generate a number of pending events, and the pending events generated by each processing unit 151 do not have data dependencies, that is, the data coupling of the pending events is loose, and it can be considered that the data coupling of these pending events is loose, so the pending events generated by multiple processing units 151 in the same event processing cluster 150 are also called pending discrete events. And an event queue is configured for each event processing cluster 150, and the event queue is used to store and process the pending discrete events in this event processing cluster 150, so as to make prerequisite preparations for subsequent event execution. It is worth noting that the chip system 100, the functional module 160 and the processing unit 151 in the event processing cluster 150 can all generate events; and the events generated by the chip system 100 and the functional module 160 will be stored in the main event queue of the chip system 100, while the events generated by each processing unit 151 in the event processing cluster 150 will only be stored in the event queue corresponding to the event processing cluster 150.

[0048] For example, Figure 2 The chip system 100 includes four event processing clusters 150, which does not mean that a chip system 100 can only include four event processing clusters 150. The number of event processing clusters 150 can be two, three, or five, etc. The number of event processing clusters 150 is not limited here. Figure 2 Each event processing cluster 150 includes four processing units 151, which does not mean that each event processing cluster 150 can only have four processing units 151. The number of processing units 151 can be two, three, or five, etc. The number of processing units 151 in an event processing cluster 150 is not limited here. Figure 2The events generated by each processing unit 151 in an event processing cluster 150 have no data dependency, therefore, the events without dependency are stored in an event queue, thereby effectively reducing the synchronization time points of multi-threaded execution events. Moreover, in an event queue, all events at the same time do not need synchronization time overhead, that is, they can be divided into different threads for execution, thereby improving parallelism. Moreover, the clock frequency in each event processing cluster 150 can be different, that is, the entire chip system does not need to maintain a shared time axis, so that each event processing cluster 150 in the chip system has asynchronousness during the event processing process. There is no dependency on the data of the discrete events to be processed in each event processing cluster 150, and each event processing cluster 150 does not need to follow the same clock cycle, therefore, each event processing cluster 150 has independence during the event processing process, and then each event processing cluster 150 can process the discrete events to be processed in parallel to speed up the event processing efficiency.

[0049] It is worth noting that the processing unit 151 of the embodiment of the present disclosure can be a central processing unit or a chip, and both the central processing unit and the chip can generate their own events. For example, the events generated by the central processing unit may include instruction cycle events, interrupt events, exception events, clock cycle events, cache events, branch prediction events, power consumption and temperature events, multi-core coordination events, instruction pipeline events and security events. Instruction cycle events include fetching instructions, decoding, executing instructions, accessing memory and writing back registers, etc.; interrupt events include external interrupts and internal interrupts; exception events include hardware failures and program running errors, etc.; clock cycle events include status register update processing and the number of instruction counters increased, etc.; cache events include cache hits and cache misses, etc.; branch prediction events include the result of the central processing unit correctly predicting the branch instruction and the result of the central processing unit incorrectly predicting the branch instruction; power consumption and temperature events include dynamic power consumption and temperature warnings, etc.; multi-core coordination events include inter-core communication and lock and synchronization mechanisms, etc.; instruction pipeline events include pipeline conflict events; security events include execution of secure boot events and code signature verification events. The events generated by the chip may include logic operation events, data storage events, signal transmission events, power consumption management events and interrupt events. Logic operation events mean that the chip performs various logic operations by controlling the switching state of transistors; data storage events mean that the chip can store and process information, including temporary data storage and long-term data storage; signal transmission events mean that the signals inside the chip are transmitted through the interconnection network, and these signal transmissions realize communication between different functional modules; power consumption management events mean that the power management circuit inside the chip is responsible for converting the external power supply into voltage and current suitable for use by various parts of the chip, ensuring the stability of the chip under different working conditions; interrupt events mean that the chip can respond to external or internal interrupt signals. These signals can come from external devices or state changes inside the chip, triggering specific handlers.

[0050] It is worth noting that the event processing method of the embodiment of the present disclosure can be applied to the field of simulation acceleration, and the application scenario of the event processing method is a scenario with multiple processing units 151; through the event processing method of the embodiment of the present disclosure, the rate of simulation testing can be accelerated, and R&D personnel can verify and optimize the system architecture more quickly, thereby improving R&D efficiency and shortening the time from product design to market; and reducing simulation time means reducing computing resources and energy consumption, thereby reducing R&D costs; the acceleration of simulation rate can greatly improve R&D efficiency and also greatly enhance the testing experience of R&D personnel.

[0051] Overall implementation of the event processing method of the present disclosure

[0052] The present disclosure provides an event processing method for testing a chip system, wherein the chip system includes multiple event processing clusters, and the event processing clusters include multiple processing units. Figure 3 , event handling methods include:

[0053] Step S201, obtaining discrete events to be processed of each processing unit in the chip system, wherein each discrete event to be processed carries a timestamp;

[0054] Step S202, storing the discrete events to be processed of different event processing clusters into the event queues of the corresponding event processing clusters, wherein one event processing cluster corresponds to one event queue;

[0055] Step S203: using different sub-threads to process each event queue in parallel, wherein the discrete events to be processed are read from the event queue to the sub-threads according to the timestamps, and the discrete events to be processed are executed by the sub-threads.

[0056] Specifically, in the present disclosure, the processing unit can be a central processing unit or a chip, and multiple central processing units or chips can form an event processing cluster. Each event processing cluster divided in the chip system will correspond to an event queue, and the event queue is used to store the discrete events to be processed generated by each processing unit in the corresponding event processing cluster. It is worth noting that the method for processing events disclosed in the present disclosure is to simulate and test discrete events, which is used to simulate the occurrence and evolution of discrete events to evaluate the behavior and performance of the system. Discrete event simulation is a method of predicting system changes based on the law of event changes at discrete time points. The advantages of discrete event simulation include the ability to simulate the behavior and interaction of complex systems, evaluate the impact of different strategies on system performance, and allow experiments in a virtual environment.

[0057] In step S201, each processing unit in the event processing cluster can generate a discrete event to be processed, and the discrete event to be processed generated by each processing unit will carry a timestamp; wherein, the timestamp is used to represent the expectation to execute the processing of the discrete event to be processed at the corresponding time node. A processing unit can generate multiple discrete events to be processed, and the number is not limited here. Moreover, at a certain moment, a processing unit in an event processing cluster may not generate a discrete event to be processed. Among them, the discrete event to be processed in the example of the present disclosure is a discrete event that needs to be processed. There is no dependency between the discrete event and other events in the data. The two events can be processed at the same time, and the two can be independent of each other during the processing process.

[0058] Exemplarily, there are two event processing clusters in a chip system, which are the first event processing cluster and the second event processing cluster; there are two processing units in the first event processing cluster, which are the first processing unit and the second processing unit; there are also two processing units in the second event processing cluster, which are the third processing unit and the fourth processing unit; wherein, during an event processing process, the first processing unit generates a first event to be processed due to the need to read data, and the second processing unit generates a second event to be processed due to reading instructions; the third processing unit generates a third event to be processed due to the need to decode; the fourth processing unit generates a fourth event to be processed due to the need to access memory Event; Since the first pending event generated by the first processing unit and the second pending event generated by the second processing unit have no data dependency, the third pending event generated by the third processing unit and the fourth pending event generated by the fourth processing unit have no data dependency, and the first pending event has no data dependency with the third pending event and the fourth pending event, and the second pending event has no data dependency with the third pending event and the fourth pending event, therefore, the first pending event, the second pending event, the third pending event and the fourth generation processing event obtained from the two event processing clusters can be collectively referred to as pending discrete events. Moreover, the first event processing cluster and the second event processing cluster in the present disclosure are only for the purpose of more clearly explaining the technical solutions of the embodiments of the present disclosure, and do not mean that the two belong to different types of event processing clusters. Similar descriptions in the present disclosure are also based on the above reasons and will not be repeated.

[0059] In an embodiment of the present disclosure, the to-be-processed discrete events obtained from each processing unit of the event processing cluster will carry timestamps; for example, in a chip system including two event processing clusters, namely the first event processing cluster and the second event processing cluster; the first event processing cluster includes a first processing unit and a second processing unit, and the second event processing cluster includes a third processing unit and a fourth processing unit; wherein, the first processing unit generates a first to-be-processed discrete event due to the execution of an instruction, the second processing unit generates a second to-be-processed discrete event due to the update processing of the register state, the third processing unit generates a third to-be-processed discrete event due to an internal interruption, and the fourth processing unit generates a fourth to-be-processed discrete event due to a cache hit; and the first to-be-processed discrete event carries a first timestamp t0, that is, it is expected to execute the first to-be-processed discrete event at the moment of t0; the second to-be-processed discrete event carries a second timestamp t1, that is, it is expected to execute the second to-be-processed discrete event at the moment of t1; the third to-be-processed discrete event carries a third timestamp t3, that is, it is expected to execute the third to-be-processed discrete event at the moment of t3; the fourth to-be-processed discrete event carries a fourth timestamp t4, that is, it is expected to execute the fourth to-be-processed discrete event at the moment of t4; for different event processing clusters, in the case of t0 < t1, the first to-be-processed discrete event will be executed first; in the case of t4 < t3, the fourth to-be-processed discrete event will be executed first.

[0060] In step S202, after obtaining the to-be-processed discrete events in each event processing cluster, the obtained to-be-processed discrete events can be stored in the event queue of the event processing cluster corresponding to the to-be-processed discrete events. Each event processing cluster corresponds to an event queue, so as to prepare the premise for subsequent parallel event processing. It should be noted that each event processing cluster divided in the chip system corresponds to an event queue, and the to-be-processed discrete events obtained in an event processing cluster are all stored in the event queue corresponding to the event processing cluster.

[0061] Exemplarily, a chip system includes three event processing clusters, namely a first event processing cluster, a second event processing cluster and a third event processing cluster. The first event processing cluster is bound to a first event queue, the second event processing cluster is bound to a second event queue, and the third event processing cluster is bound to a third event queue. The first event processing cluster includes a first processing unit and a second processing unit, the second event processing cluster includes a third processing unit and a fourth processing unit, and the third event processing cluster includes a fifth processing unit and a sixth processing unit. Therefore, the discrete events to be processed subsequently obtained from the first processing unit and the second processing unit will be stored in the first event queue, and the discrete events to be processed obtained from the third processing unit and the fourth processing unit will be stored in the second event queue; the discrete events to be processed obtained from the fifth processing unit and the sixth processing unit will be stored in the third event queue.

[0062] It is worth noting that each event processing cluster corresponds to an event queue, and the discrete events to be processed obtained in an event processing cluster will be stored in the event queue corresponding to the event processing cluster, in preparation for the subsequent parallel processing of the event queue. Since the discrete events to be processed obtained in each event processing cluster will be stored in the corresponding event queue, the discrete events to be processed in each event queue can be processed independently in the future to achieve parallel processing, which can greatly improve the execution efficiency of events, thereby greatly improving the efficiency of simulation.

[0063] In step S203, after the discrete events to be processed are stored in the corresponding event queue, the sub-threads can be used to execute the discrete events to be processed in the event queue; and each event queue will correspond to at least one sub-thread; using the sub-threads, the discrete events to be processed in different event queues can be processed in parallel to speed up the processing efficiency of the discrete events to be processed, thereby greatly improving the efficiency of the simulation, and also improving the test efficiency of the chip system, bringing a good test experience to the test developers. And in the process of using different sub-threads to process each event queue in parallel, the corresponding discrete events to be processed can be read from the event queue into the sub-thread according to the timestamp of the discrete events to be processed in the event queue, and then the discrete events to be processed can be processed by the sub-threads later.

[0064] It is worth noting that the sub-thread is obtained by splitting the main thread, that is, the sub-thread is created by the main thread. In some embodiments, a main thread can create one or more sub-threads to execute parallel tasks. In the embodiment of the present disclosure, an event queue bound to an event processing cluster corresponds to at least one sub-thread, and in the process of event processing, different sub-threads can simultaneously process the discrete events to be processed in the corresponding event queue in parallel, so that the processing rate of discrete events can be improved, and then the simulation rate can be accelerated, which brings a better testing experience to R&D personnel.

[0065] Exemplarily, a chip system has two event processing clusters, namely a first event processing cluster and a second event processing cluster. The first event processing cluster is bound to a first event queue, and the second event processing cluster is bound to a second event queue. The first event queue corresponds to a first sub-thread, and the second event queue corresponds to a second sub-thread. In the process of event processing, the first sub-thread can process the discrete events to be processed in the first event queue alone, and the second sub-thread can process the discrete events to be processed in the second event queue alone. Furthermore, the first sub-thread and the second sub-thread can execute and process the discrete events to be processed in the first event processing cluster and the second event processing cluster in parallel. In addition, there are The first discrete event to be processed and the second discrete event to be processed, the second event queue stores the third discrete event to be processed and the fourth discrete event to be processed, the timestamps of the first discrete event to be processed and the third discrete event to be processed are both t0, and the timestamps of the second discrete event to be processed and the fourth discrete event to be processed are both t1; when the time t0 arrives, the first discrete event to be processed will be read into the first sub-thread and the third discrete event to be processed will be read into the second sub-thread, and then the first discrete event to be processed will be processed by the first sub-thread and the third discrete event to be processed will be processed by the second sub-thread, so that the first sub-thread and the second sub-thread can be used to process the events in parallel, which greatly speeds up the processing rate of the events. Similarly, when the time t1 arrives, the second discrete event to be processed will be read into the first sub-thread and the fourth discrete event to be processed will be read into the second sub-thread, and then the second discrete event to be processed will be processed by the first sub-thread and the fourth discrete event to be processed will be processed by the second sub-thread.

[0066] In step S201 to step S203, in the process of testing the chip system using the event processing method of the embodiment of the present disclosure, firstly, the discrete events to be processed are obtained from each processing unit in the event processing cluster, wherein each discrete event to be processed will carry a timestamp; then the discrete events to be processed of different event processing clusters are stored in the event queues of the corresponding event processing clusters, wherein each event processing cluster will correspond to an event queue; then different sub-threads are used to process each event queue in parallel, wherein, in the process of using different sub-threads to process each event queue in parallel, the discrete events to be processed can be read from the event queue to the corresponding sub-thread according to the timestamp of the discrete events to be processed, and the sub-thread can execute the read discrete events to be processed. Each event processing cluster will correspond to an event queue, and each event queue will correspond to at least one sub-thread, so that the sub-threads are relatively independent in the process of processing the discrete events to be processed in each event queue, so that different event queues can be processed in parallel to speed up the processing rate of events and improve the speed of simulation testing.

[0067] Exemplarily, in a chip system, two event processing clusters are included, namely, a first event processing cluster and a second event processing cluster, the first event processing cluster includes a first processing unit, a second processing unit and a third processing unit, and the second event processing cluster includes a fourth processing unit and a fifth processing unit; the first processing unit generates a first discrete event to be processed, and the timestamp of the first discrete event to be processed is t0, the second processing unit generates a second discrete event to be processed, and the timestamp of the second discrete event to be processed is t1, and the third processing unit does not generate a discrete event to be processed; the fourth processing unit generates a third discrete event to be processed, and the timestamp of the third discrete event to be processed is t1, and the fifth processing unit generates a fourth discrete event to be processed, and the timestamp of the fourth discrete event to be processed is t0; the first event processing cluster is bound to a first event queue, and the second event processing cluster A second event queue is bound, the first discrete event to be processed and the second discrete event to be processed are stored in the first event queue, and the third discrete event to be processed and the fourth discrete event to be processed are stored in the second event queue; the first event queue corresponds to the first sub-thread, and the second event queue corresponds to the second sub-thread; in the event processing process, when the time t0 arrives, the first sub-thread will read the first discrete event to be processed from the first event queue, and the second sub-thread will read the fourth discrete event to be processed from the second event queue, and then the first sub-thread executes the read first discrete event to be processed, and the second sub-thread executes the read fourth discrete event to be processed, and then the first sub-thread and the second sub-thread can simultaneously process the discrete events in the first event queue and the second event queue in parallel, which greatly improves the event processing efficiency.

[0068] It is worth noting that in some embodiments of the present disclosure, an event queue may also correspond to multiple sub-threads, and the multiple sub-threads may process multiple pending discrete events in the event queue in parallel to further speed up the event processing efficiency. Exemplarily, an event queue has a first pending discrete event, a second pending discrete event, and a third pending discrete event, and the event queue is allocated with a first sub-thread, a second sub-thread, and a third sub-thread to process the related pending discrete events; during the event processing, the first sub-thread may process the first pending discrete event, the second sub-thread may process the second pending discrete event, and the third sub-thread may process the third pending discrete event, and the three sub-threads may process the three pending discrete events in parallel, which may further improve the event processing efficiency.

[0069] In one embodiment, referring to Figure 4 , step S202 includes:

[0070] Step S301, obtaining queue index information of the event processing cluster;

[0071] Step S302: storing the discrete events to be processed in the event processing cluster into the event queue of the corresponding event processing cluster according to the queue index information.

[0072] In step S301, when storing the pending discrete events of different event processing clusters into the event queues of the corresponding event processing clusters respectively, it is necessary to first obtain the queue index information of the event processing cluster, and the queue index information of each event processing cluster is unique, so that the pending discrete events generated by the processing units in an event processing cluster can be accurately stored in the event queue corresponding to the event processing cluster.

[0073] Exemplarily, a chip system includes a first event processing cluster and a second event processing cluster, the queue index information of the first event processing cluster is 01, the queue index information of the second event processing cluster is 02, and the event queue corresponding to the queue index information 01 is the first event queue, and the event queue corresponding to the queue index information 02 is the second event queue. Therefore, the discrete events to be processed collected in the first event processing cluster will be stored in the first event queue corresponding to the queue index information 01, and the discrete events to be processed collected in the second event processing cluster will be stored in the second event queue corresponding to the queue index information 02.

[0074] In step S302, after obtaining the queue index information corresponding to the event processing cluster, the to-be-processed discrete events in the event processing cluster can be stored in the event queue of the corresponding event processing cluster according to the obtained queue index information, so as to prepare for the subsequent discrete event parallel processing. Exemplarily, the chip system includes a first event processing cluster, a second event processing cluster and a third event processing cluster, the queue index information of the first event processing cluster is 01, the queue index information of the second event processing cluster is 02, and the queue index information of the third event processing cluster is 03, the queue index information 01 corresponds to the first event queue, the queue index information 02 corresponds to the second event queue, and the queue index information 03 corresponds to the third event queue, so the to-be-processed discrete events obtained in the first event processing cluster will be stored in the first event queue corresponding to the queue index information 01, the to-be-processed discrete events obtained in the second event processing cluster will be stored in the second event queue corresponding to the queue index information 02, and the to-be-processed discrete events obtained in the third event processing cluster will be stored in the third event queue corresponding to the queue index information 03.

[0075] In step S301 to step S302, in the process of storing the pending discrete events in different event processing clusters into the event queues of the corresponding event processing clusters, the queue index information of each event processing cluster can be obtained first, and then when the pending discrete events are obtained in the event processing cluster, the event queue to be stored can be determined according to the queue index of the corresponding event processing cluster, so that the pending discrete events can be accurately stored in the corresponding event queue, so as to make the prerequisite preparation for the subsequent parallel processing of events. Exemplarily, a chip system includes three event processing clusters, which are respectively a first event processing cluster, a second event processing cluster and a third event processing cluster. The queue index information of the first event processing cluster is 01, the queue index information of the second event processing cluster is 02, and the queue index information of the third event processing cluster is 03. Queue index information 01 corresponds to the first event queue, queue index information 02 corresponds to the second event queue, and queue index information 03 corresponds to the third event queue; the first event processing cluster includes a first processing unit and a second processing unit, the second event processing cluster includes a third processing unit and a fourth processing unit, and the third event processing cluster includes a fifth processing unit and a sixth processing unit, and thus the discrete events to be processed generated by the first processing unit and the second processing unit are stored in the first event queue corresponding to the queue index information 01; the discrete events to be processed generated by the third processing unit and the fourth processing unit are stored in the second event queue corresponding to the queue index information 02; the discrete events to be processed generated by the fifth processing unit and the sixth processing unit are stored in the third event queue corresponding to the queue index information 03, so as to prepare for subsequent parallel processing of event queues.

[0076] In one embodiment, referring to Figure 5 , step S203 includes:

[0077] Step S401, obtaining the current running time;

[0078] Step S402, matching the current running time with the timestamp of the discrete event to be processed;

[0079] Step S403, when the current running time matches the timestamp, the to-be-processed discrete event corresponding to the timestamp is read from the event queue to the sub-thread corresponding to the event queue;

[0080] Step S404: executing the discrete event to be processed through the child thread.

[0081] In step S401, during event processing, the current running time must first be obtained, so that the current running time can be matched and compared with the timestamp of each discrete event to be processed, thereby triggering the execution of the corresponding discrete event to be processed.

[0082] In step S402, after obtaining the current running time, the current running time can be matched and compared with the timestamp of the discrete event to be processed, and then the corresponding discrete event to be processed can be matched and selected from the event queue to prepare for processing the corresponding discrete event to be processed. Exemplarily, a chip system includes a first event processing cluster and a second event processing cluster, the first event processing cluster includes a first processing unit, a second processing unit and a third processing unit, and the second event processing cluster includes a fourth processing unit and a fifth processing unit; the first processing unit generates a first discrete event to be processed, the second processing unit generates a second discrete event to be processed, the third processing unit generates a third discrete event to be processed, the fourth processing unit generates a fourth discrete event to be processed, and the fifth processing unit generates a fifth discrete event to be processed; the first discrete event to be processed carries a timestamp t1, the second discrete event to be processed carries a timestamp t2, the third discrete event to be processed carries a timestamp t3, the fourth discrete event to be processed carries a timestamp t1, and the fifth discrete event to be processed carries a timestamp t2; when the current running time is t1, the first discrete event to be processed and the fourth discrete event to be processed corresponding to the current running time t1 can be matched; when the current running time is t2, the second discrete event to be processed and the fifth discrete event to be processed corresponding to the current running time t2 can be matched. Through the above settings, the discrete events to be processed that need to be processed can be accurately selected.

[0083] In step S403, the current running time is matched and compared with the timestamp of each discrete event to be processed; when the current running time matches the timestamp of the discrete event to be processed, the discrete event to be processed corresponding to the matched timestamp will be read from the corresponding event queue for processing, and the discrete event to be processed will be read into the subthread corresponding to the event queue, so that the subthread can execute the corresponding discrete event to be processed. Exemplarily, an event processing cluster includes a first processing unit and a second processing unit, the first event processing cluster is bound to a first event queue, the first event queue corresponds to a first subthread, the first processing unit generates a first discrete event to be processed, the first discrete event to be processed carries a timestamp t1, and the second processing unit generates a second discrete event to be processed, the second discrete event to be processed carries a timestamp t2; when the current running time is t1, the first discrete event to be processed corresponding to the current running time t1 will be read from the first event queue into the first subthread, and the first discrete event to be processed can be executed by the first subthread later.

[0084] In step S404, when the discrete events to be processed are read into the corresponding sub-threads, the sub-threads can be used to execute the read discrete events to be processed. It is worth noting that when different sub-threads read the discrete events to be processed, they will execute the read discrete events to be processed, and the different sub-threads will not be affected by each other in the process of event processing, thereby realizing parallel processing of events; illustratively, the first sub-thread reads the first discrete event to be processed, and the second sub-thread reads the second discrete event to be processed, and the timestamp carried by the first discrete event to be processed is t1, and the timestamp carried by the second discrete event to be processed is also t1, therefore, the first sub-thread can execute the first discrete event to be processed and the second sub-thread can execute the second discrete event to be processed at the same time, so as to realize parallel processing of events and speed up the processing efficiency of events.

[0085] In step S401 to step S404, in the process of reading the discrete event to be processed from the event queue to the sub-thread according to the timestamp, and using the sub-thread to execute the discrete event to be processed, the current running time can be obtained first, and then the current running time and the timestamp of the discrete event to be processed are matched and compared; then, when the current running time matches the timestamp, the discrete event to be processed corresponding to the timestamp will be read from the event queue to the sub-thread corresponding to the event queue, and finally the discrete event to be processed can be executed by the sub-thread; and different sub-threads are not interfered with each other in the process of processing the corresponding discrete events to be processed, so different sub-threads can process the discrete events to be processed in parallel, thereby greatly improving the processing efficiency of the events.

[0086] It is worth noting that the event queue of the embodiment of the present disclosure can be in the form of a two-level linked list, the first level linked list of the two-level linked list is different running times, and the second level linked list is all the pending discrete events that need to be executed under the corresponding running time; illustratively, the first level linked list of the two-level linked list includes running time t0, running time t1 and running time t2, and the second level linked list of the two-level linked list includes the first pending discrete event, the second pending discrete event and the third pending discrete event that need to be executed when the running time is t0; the fourth pending discrete event and the fifth pending discrete event that need to be executed when the running time is t1; and the sixth pending discrete event and the seventh pending discrete event that need to be executed when the running time is t2. The running time of the first level linked list in the two-level linked list can be understood as the timestamp of each pending discrete event. It is also stipulated that the pending discrete event corresponding to the next running time can only be processed when all the pending discrete events corresponding to the previous running time have been processed, so that the processing of events can be guaranteed to be more reliable and there will be no event processing congestion.

[0087] Exemplarily, during a simulation test, it is necessary to test the event processing performance of a chip system composed of multiple central processing units; the chip system includes four central processing units, namely a first central processing unit, a second central processing unit, a third central processing unit and a fourth central processing unit, the first central processing unit and the second central processing unit constitute a first event processing cluster, the third central processing unit and the fourth central processing unit constitute a second event processing cluster, the first event processing cluster is bound to a first event queue, the second event processing cluster is bound to a second event queue, the first event queue corresponds to a first sub-thread, and the second event queue corresponds to a second sub-thread; the first central processing unit generates a first discrete event to be processed due to reading an instruction, the second central processing unit generates a second discrete event to be processed due to accessing memory, the third central processing unit generates a third discrete event to be processed due to a program running error, and the fourth central processing unit generates a fourth discrete event to be processed due to writing back to a register. Event; the timestamp carried by the first discrete event to be processed is t0, the timestamp carried by the second discrete event to be processed is t1, the timestamp carried by the third discrete event to be processed is t1, and the timestamp carried by the fourth discrete event to be processed is t0; when the current running time is t0, the first sub-thread will read the first discrete event to be processed from the first event queue, and the second sub-thread will read the fourth discrete event to be processed from the second event queue, and then the first sub-thread can execute the first discrete event to be processed, and the second sub-thread can execute the fourth discrete event to be processed. The process of the first sub-thread processing the discrete events to be processed in the first event queue and the process of the second sub-thread processing the discrete events to be processed in the second event queue do not affect each other, so that the discrete events to be processed can be processed in parallel well, so as to speed up the simulation test rate and bring a good testing experience to R&D testers. And when the first and fourth discrete events to be processed corresponding to timestamp t0 are processed completely and the current running time is t1, the first sub-thread will read the second discrete event to be processed from the first event queue, and the second sub-thread will read the third discrete event to be processed from the second event queue. Then the first sub-thread can execute the second discrete event to be processed, and the second sub-thread can execute the third discrete event to be processed. That is, the event corresponding to the previous moment can be processed only when the event corresponding to the next moment is processed completely, thereby ensuring the accuracy and reliability of event processing and improving the precision of event processing.

[0088] In one embodiment, referring to Figure 6 , when there are multiple child threads corresponding to the event queue, step S404 includes:

[0089] Step S501: Processing discrete events to be processed in parallel through multiple sub-threads.

[0090] In step S501, when there are multiple sub-threads corresponding to the event queue, multiple sub-threads can be used to process the discrete events to be processed in the event queue in parallel, so as to further speed up the processing efficiency of the events, thereby greatly improving the efficiency of the simulation test. For example, there are five discrete events to be processed in an event queue, and the sub-threads corresponding to the event queue are also exactly five, so each sub-thread can be assigned to process one discrete event to be processed, so as to realize parallel processing of multiple discrete events to be processed in a single event queue, so as to further speed up the processing efficiency of the events and speed up the simulation.

[0091] For example, Figure 7 A schematic diagram of multiple sub-threads processing discrete events to be processed in an event queue. Under different running times, each sub-thread obtained by splitting the main thread can independently process discrete events to be processed in the event queue, that is, multiple sub-threads can process discrete events to be processed in the event queue in parallel; through such a setting, the processing efficiency of each discrete event to be processed in the event queue can be further improved. Figure 7 In the example, each sub-thread is split from the main thread, where the main thread can be determined by the server on the test end. For example, if a server has 256 core processing units, the main thread generated by the server can only be split into 256 sub-threads at most. Figure 7 It shows that child thread 0 processes event 0, child thread 1 processes event 1, child thread i processes event i, etc.; in the actual application process, child thread 0 is not only able to process event 0, child thread 0 can also process event 1, and child thread 1 is not only able to process event 1, child thread 1 can also process event 0, that is, each event in the event queue does not need to be assigned to a specific child thread, as long as the child thread is in an idle state, the child thread can process new events, and the child thread has no specific directionality with the events in the event queue.

[0092] Exemplarily, in a chip system, there are two event processing clusters, namely the first event processing cluster and the second event processing cluster, the first event processing cluster is bound to the first event queue, the second event processing cluster is bound to the second event queue, the first event processing cluster includes the first processing unit, the second processing unit and the third processing unit, the second event processing cluster includes the fourth processing unit and the fifth processing unit; the first event queue corresponds to three sub-threads, namely the first sub-thread, the second sub-thread and the third sub-thread; the second event queue corresponds to two sub-threads, namely the fourth sub-thread and the fifth sub-thread; in the process of event processing, the first processing unit generates a first discrete event to be processed, the second processing unit generates a second discrete event to be processed, the third processing unit generates a third discrete event to be processed, the fourth processing unit generates a fourth discrete event to be processed, and the fifth processing unit generates a fifth discrete event to be processed; the first discrete event to be processed, the second discrete event to be processed, the third discrete event to be processed, the fourth discrete event to be processed, and the fifth discrete event to be processed. The second and third discrete events to be processed are both stored in the first event queue, and the fourth and fifth discrete events to be processed are both stored in the second event queue; and the timestamps of the first, second, third, fourth and fifth discrete events to be processed are all t0. Therefore, when the current running time is t0, the first discrete event to be processed can be read into the first sub-thread, the second discrete event to be processed can be read into the second sub-thread, the third discrete event to be processed can be read into the third sub-thread, the fourth discrete event to be processed can be read into the fourth sub-thread, and the fifth discrete event to be processed can be read into the fifth sub-thread; then the first sub-thread, the second sub-thread, the third sub-thread, the fourth sub-thread and the fifth sub-thread can process their respective discrete events to be processed in parallel, thereby greatly accelerating the processing efficiency of events and improving the efficiency of simulation testing.

[0093] In one embodiment, referring to Figure 8 , step S403 includes:

[0094] Step S601, determining the number of discrete events to be processed corresponding to the timestamp to obtain the number of events to be processed;

[0095] Step S602, dividing a preset main thread into sub-threads according to the number of events to be processed;

[0096] Step S603: read the discrete events to be processed into the child thread.

[0097] In step S601, when the current running time matches the timestamp, the to-be-processed discrete event corresponding to the timestamp can be read from the event queue to the sub-thread corresponding to the event queue. First, the number of to-be-processed discrete events corresponding to the timestamp matching the current running time in an event queue is determined and processed, and then the number of to-be-processed events can be obtained, so as to prepare for the subsequent sub-thread allocation. Exemplarily, there are five to-be-processed discrete events in an event queue, namely, the first to-be-processed discrete event, the second to-be-processed discrete event, the third to-be-processed discrete event, the fourth to-be-processed discrete event and the fifth to-be-processed discrete event, and the timestamp carried by the first to-be-processed discrete event is t1, the timestamp carried by the second to-be-processed discrete event is t2, the timestamp carried by the third to-be-processed discrete event is t1, the timestamp carried by the fourth to-be-processed discrete event is t1, and the timestamp carried by the fifth to-be-processed discrete event is t2. Therefore, when the current running time is t1, the first to-be-processed discrete event, the third to-be-processed discrete event and the fourth to-be-processed discrete event can be selected from the event queue. Therefore, the number of to-be-processed events determined at this time is 3.

[0098] In step S602, when it is determined that the number of pending events is obtained, a corresponding number of sub-threads can be obtained from the pre-set main thread according to the number of pending events, so that the sub-threads obtained by the division can be used to perform parallel processing on the matched selected discrete events to be processed, which can greatly speed up the processing efficiency of events, improve the response speed and throughput; the thread allocation processing is performed according to the number of pending events, so that the creation of threads can be more flexible, and relevant computing resources can be saved while maintaining high concurrency. Exemplarily, when it is determined that the number of pending events is 3, 3 sub-threads can be created from the main thread, and then the 3 sub-threads created can perform parallel processing on the selected discrete events to be processed. At each running time, a corresponding number of sub-threads can be dynamically created according to the number of discrete events to be processed, so that the event processing process can be more flexible.

[0099] In step S603, after the main thread is divided to obtain sub-threads, the selected discrete events to be processed can be read one-to-one into the sub-threads, so that the sub-threads can be used to process the discrete events to be processed in parallel later to speed up the processing efficiency of the events. Exemplarily, a first discrete event to be processed, a second discrete event to be processed, and a third discrete event to be processed are selected from an event queue, and then the first sub-thread, the second sub-thread, and the third sub-thread are allocated from the pre-set main thread, and then the first discrete event to be processed can be read to obtain the first sub-thread, the second discrete event to be processed can be read to obtain the second sub-thread, and the third discrete event to be processed can be read to obtain the third sub-thread, and then the first sub-thread, the second sub-thread, and the third sub-thread can process the corresponding discrete events to be processed in parallel.

[0100] In step S601 to step S603, in the process of reading the to-be-processed discrete events corresponding to the timestamp from the event queue to the sub-thread corresponding to the event queue, the number of to-be-processed discrete events corresponding to the timestamp can be determined and processed to obtain the number of to-be-processed events; then, the sub-threads are obtained by splitting from the preset main thread according to the number of to-be-processed events; subsequently, the to-be-processed discrete events can be read into the split sub-threads to prepare for subsequent event processing. Exemplarily, an event queue stores a first discrete event to be processed, a second discrete event to be processed, and a third discrete event to be processed. The timestamp carried by the first discrete event to be processed is t1, the timestamp carried by the second discrete event to be processed is t2, and the timestamp carried by the third discrete event to be processed is t1; when the current running time is t1, the first discrete event to be processed and the second discrete event to be processed will be matched and selected from the event queue. At this time, the number of events to be processed is 2, so the first sub-thread and the second sub-thread can be split from the main thread. Subsequently, the first discrete event to be processed can be read into the first sub-thread, and the second discrete event to be processed can be read into the second sub-thread. Then, the first sub-thread and the second sub-thread can process the discrete events to be processed in parallel, thereby improving the processing efficiency of the events. It is worth noting that in the above embodiment, the first discrete event to be processed can also be read into the second sub-thread, and the second discrete event to be processed can be read into the first sub-thread. It is only necessary to read the discrete event to be processed into an idle sub-thread, and it is not necessary to read the discrete event to be processed into a specific sub-thread for processing.

[0101] In one embodiment, referring to Fig. 9 , when there is one child thread corresponding to the event queue, step S404 further includes:

[0102] Step S701: Execute and process corresponding discrete events to be processed respectively through sub-threads.

[0103] In step S701, when the event queue is bound to only one sub-thread, the sub-thread can be used to execute the processing of the pending discrete events in the corresponding event queue; since a chip processing system includes multiple event processing clusters, and each event processing cluster is bound to an event queue, the process of processing the pending discrete events in each event queue is relatively independent. Therefore, the process of processing the pending discrete events in a chip processing system can also be considered as a parallel method; it is worth noting that at a certain running time, multiple pending discrete events can be selected from the event queue, but because the event queue only corresponds to one sub-thread, the sub-thread can be used to process the selected multiple pending discrete events in turn to maintain the reliability of event processing. Exemplarily, a chip system includes two event processing clusters, namely a first event processing cluster and a second event processing cluster, the first event processing cluster is bound to a first event queue, and the second event processing cluster is bound to a second event queue; the first event queue stores a first discrete event to be processed and a second discrete event to be processed, the first discrete event to be processed carries a timestamp of t0, and the second discrete event to be processed carries a timestamp of t1; the second event queue stores a third discrete event to be processed and a fourth discrete event to be processed, the third discrete event to be processed carries a timestamp of t0, and the fourth discrete event to be processed carries a timestamp of t1; the first event queue corresponds to a first sub-thread, and the second event queue corresponds to a second sub-thread; when the current running time is t0, the first sub-thread can be used to process the first discrete event to be processed, and the second sub-thread can be used to process the third discrete event to be processed, and the first sub-thread and the second sub-thread are relatively independent in the process of event processing, so that parallel processing of discrete events to be processed can be achieved.

[0104] For example, Fig.10A schematic diagram of a single sub-thread processing a pending discrete event in an event queue. At different running times, each event queue will be assigned a sub-thread to process the pending discrete event, and different sub-threads will not affect each other during the event processing process; event processing cluster 0 is assigned sub-thread 0, event processing cluster 1 is assigned sub-thread 1, and event processing cluster N is assigned sub-thread N, that is, each event processing cluster will be assigned a sub-thread, and a sub-thread is used to process the pending discrete event generated in an event processing cluster; a sub-thread selects the corresponding pending discrete event from the corresponding event queue according to different timestamps, and executes the corresponding pending discrete event; in the process of executing the pending discrete events of different event processing clusters, there will be no mutual influence. Therefore, through the above settings, it is also possible to achieve parallel processing of the pending discrete events in a chip system, and also improve the event processing efficiency.

[0105] In one embodiment, referring to Fig.11 The child thread is obtained by dividing the preset main thread, and after step S203, the following steps are further included:

[0106] Step S801, obtaining the synchronization time node of the main thread;

[0107] Step S802: synchronize the main thread and the child thread according to the synchronization time node.

[0108] In step S801, each event processing cluster is bound to an event queue, which is used to store and process the pending discrete events generated by the processing units in the event processing cluster. Each event queue corresponds to at least one child thread, and the child thread in the present disclosure is created by the main thread. A synchronization time node can be set on the main thread; the synchronization time node on the main thread can ensure that multiple threads can be executed in a predetermined order to prevent race conditions; when multiple threads access shared resources, synchronization can ensure data consistency to prevent one thread from reading or modifying data while another thread is also modifying it at the same time; by reasonably setting synchronization points, the occurrence of deadlock can also be reduced or avoided. Deadlock refers to two or more threads waiting for each other to release data, resulting in the inability of the program to continue execution.

[0109] In step S802, a synchronization time node can be set in advance on the main thread. When the current running time reaches the synchronization time node, the main thread and the child thread created by the main thread will be synchronized, which can avoid race conditions and deadlock problems, and ensure the stability and reliability of subsequent event processing. It is worth noting that the synchronization time node of the main thread can be set in advance. During the event processing process, when the current running time reaches the preset synchronization time node, the main thread will synchronize with each child thread to make the subsequent event processing more stable and reliable.

[0110] In step S801 to step S802, after using the child thread to process the discrete event to be processed, the synchronization time node of the main thread can also be obtained; and subsequently the main thread and each child thread can be synchronized according to the synchronization time node of the main thread to ensure the stability and reliability of event processing. Exemplarily, a chip system includes a first event processing cluster and a second event processing cluster, the first event processing cluster includes a first processing unit, a second processing unit and a third processing unit, the second event processing cluster includes a fourth processing unit and a fifth processing unit, the first event processing cluster is bound to a first event queue, the second event processing cluster is bound to a second event queue, the first event queue corresponds to a first sub-thread, the second event queue corresponds to a second sub-thread, and the first sub-thread and the second sub-thread are both created by the main thread; before processing the discrete events to be processed in the first event processing cluster and the second event processing cluster, a synchronization time node t100 can be set on the main thread, and when the first sub-thread and the second sub-thread are subsequently used to execute the relevant discrete events to be processed, when the current running time reaches the synchronization time node t100, the first sub-thread and the second sub-thread will be synchronized with the main thread to ensure that the subsequent processing of the discrete events to be processed can be more stable and reliable. It is worth noting that the synchronization time node of the main thread can be set by the test development personnel according to the actual test needs, and the setting of the synchronization time node can avoid the occurrence of deadlock to ensure the reliability and stability of the processing of the discrete events to be processed.

[0111] In one embodiment, referring to Fig.12 Each discrete event to be processed also carries a priority, and after step S202, the following steps are further included:

[0112] Step S901, comparing the priorities of the discrete events to be processed in the event queue to obtain priority sorting information;

[0113] Step S902, determining the execution order of the discrete events to be processed according to the priority sorting information;

[0114] Step S903, reading corresponding discrete events to be processed from the event queue to the child thread according to the execution order, and using the child thread to execute the discrete events to be processed.

[0115] In step S901, after the to-be-processed discrete events of different event processing clusters are stored in the event queues of the corresponding event processing clusters, since each to-be-processed discrete event also carries a priority, the priorities of the to-be-processed discrete events in the same event queue can be compared and processed, and then the priority sorting information associated with the priorities of each to-be-processed discrete event in the same event queue can be obtained, so as to prepare for the subsequent processing of the to-be-processed discrete events. Exemplarily, an event queue stores the first to-be-processed discrete event, the second to-be-processed discrete event, and the third to-be-processed discrete event. The priority carried by the first to-be-processed discrete event is 001, the priority carried by the second to-be-processed discrete event is 000, and the priority carried by the third to-be-processed discrete event is 002. Therefore, in this case, the event with the highest priority in the event queue is the second to-be-processed discrete event, followed by the first to-be-processed discrete event, and the event with the lowest priority is the third to-be-processed discrete event; it is worth noting that the smaller the value used to represent the priority of the to-be-processed discrete event, the higher the priority of the to-be-processed discrete event.

[0116] In step S902, when the priority sorting information of an event queue is determined, the execution order of the discrete events to be processed can be determined according to the priority sorting information of the event queue. The discrete event to be processed with the highest priority in the event queue is processed first by the corresponding child thread, and the discrete event to be processed with the lowest priority in the event queue is processed last by the corresponding child thread. For example, an event queue stores the first discrete event to be processed, the second discrete event to be processed, the third discrete event to be processed, and the fourth discrete event to be processed. The priority of the first discrete event to be processed is 000, the priority of the second discrete event to be processed is 003, the priority of the third discrete event to be processed is 002, and the priority of the fourth discrete event to be processed is 001; therefore, in the event queue, the order of priority from high to low is: the first discrete event to be processed, the fourth discrete event to be processed, the third discrete event to be processed, and the second discrete event to be processed; in the subsequent process of processing each discrete event to be processed in the event queue, the related discrete events to be processed can be processed in the following order: the first discrete event to be processed, the fourth discrete event to be processed, the third discrete event to be processed, and the second discrete event to be processed. The execution order of the discrete events to be processed is determined based on the priorities of different discrete events to be processed. Prioritizing the most important events can ensure that the key event tasks are completed in time, thereby improving the overall event processing efficiency. Through priority sorting, limited resources can be allocated more reasonably to achieve maximum benefits.

[0117] In step S903, after determining the execution order, the corresponding discrete events to be processed can be read from the event queue into the subthread according to the execution order, and then the subthread can be used to execute the discrete events to be processed, and the discrete events to be processed with relatively high priority are processed first, so that important events can be processed first, and resources can be reasonably allocated to achieve maximum benefits. Exemplarily, an event queue includes a first discrete event to be processed, a second discrete event to be processed, and a third discrete event to be processed, and after the priority comparison processing of each discrete event to be processed, the execution order obtained is: the second discrete event to be processed, the third discrete event to be processed, and the first discrete event to be processed; therefore, in the process of reading the discrete events to be processed in the event queue into the subthread corresponding to the event queue, and using the subthread to process the corresponding discrete events to be processed, the second discrete event to be processed can be read into the subthread first, and then the subthread can be used to execute the second discrete event to be processed.

[0118] In step S901 to step S903, after the pending discrete events of different event processing clusters are respectively stored in the event queues of the corresponding event processing clusters, the priorities of the pending discrete events in the event queues can be compared, so as to obtain the priority sorting information of the event queue; then, the execution order of the pending discrete events in the event queue is determined according to the obtained priority sorting information; finally, the corresponding pending discrete events can be read from the event queue according to the execution order to the sub-thread, and finally, the corresponding pending discrete events can be processed according to the sub-thread; by setting the execution order of the discrete events to be processed by priority, limited resources can be allocated more reasonably and efficiency can be improved. Exemplarily, in a chip system, two event processing clusters are included, namely a first event processing cluster and a second event processing cluster. The first event processing cluster is bound to a first event queue, and the second event processing cluster is bound to a second event queue. The first event queue corresponds to a first sub-thread, and the second event queue corresponds to a second sub-thread. The first event queue stores a first discrete event to be processed and a second discrete event to be processed. The priority of the first discrete event to be processed is 000, and the priority of the second discrete event to be processed is 001. The second event queue stores a third discrete event to be processed and a fourth discrete event to be processed. The priority of the third discrete event to be processed is 003, and the priority of the fourth discrete event to be processed is 002. In the subsequent event processing process, the first sub-thread can first process the first discrete event to be processed in the first event queue, and then process the second discrete event to be processed. The second sub-thread can first process the fourth discrete event to be processed, and then process the third discrete event to be processed.

[0119] In a possible implementation manner, there are five pending discrete events in an event queue, namely, a first pending discrete event, a second pending discrete event, a third pending discrete event, a fourth pending discrete event and a fifth pending discrete event, and the event queue corresponds to three sub-threads, namely, a first sub-thread, a second sub-thread and a third sub-thread; and the priority of the pending discrete events in the event queue is in the following order from high to low: the second pending discrete event, the third pending discrete event, the first pending discrete event, the fifth pending discrete event and the fourth pending discrete event; therefore, in the subsequent event processing process, the second pending discrete event can be first read into the first sub-thread, the third pending discrete event can be read into the second sub-thread, and the first pending discrete event can be read into the third sub-thread; when any of the three sub-threads has executed the previous pending discrete event, the fifth pending discrete event will be read into the corresponding sub-thread first, and finally the fourth pending discrete event will be read into the idle sub-thread.

[0120] In one embodiment, referring to Fig.13 As shown, the chip system further includes a subsystem control module and multiple subsystems, the multiple subsystems are all connected to the subsystem control module, each subsystem includes a control logic processing unit and multiple secondary subsystems, the multiple secondary subsystems are all connected to the control logic processing unit, and each secondary subsystem includes a functional module and an event processing cluster; the event processing method of the embodiment of the present disclosure also includes: step S1001, obtaining a first task event of the chip system, wherein the first task event carries tag information and a timestamp;

[0121] Step S1002, allocating the first task event to a corresponding functional module or event processing cluster according to the tag information; and storing the first task event in a main event queue of the chip system;

[0122] Step S1003 , reading the corresponding first task event from the main event queue according to the timestamp, and executing the first task event using the corresponding functional module or event processing cluster.

[0123] In step S1001, the chip system can send a first task event to the subsystem to control and process the subsystem in the chip system; and the first task event carries marking information, through which the first task event can be assigned to the secondary subsystem of the corresponding subsystem; the timestamp carried by the first task event can determine the execution time of the event. Exemplarily, a chip system includes two subsystems, namely, a first subsystem and a second subsystem, the first subsystem includes a first subsystem and a second subsystem, the second subsystem includes a third subsystem and a fourth subsystem, the first subsystem includes a first event processing cluster and a first functional module, the second subsystem includes a second event processing cluster and a second functional module, the third subsystem includes a third event processing cluster and a third functional module, and the fourth subsystem includes a fourth event processing cluster and a fourth functional module; the first event processing cluster can be marked as 111, the first functional module can be marked as 112, the second event processing cluster can be marked as 121, the second functional module can be marked as 122, the third event processing cluster can be marked as 211, the third functional module can be marked as 212, the fourth event processing cluster can be marked as 221, and the fourth functional module can be marked as 222. Therefore, in the subsequent event allocation process, the allocation can be carried out according to the marking information carried on the first task event. For example, the marking information carried on the first task event is 122, and finally the first task event will be sent to the second functional module for execution and processing.

[0124] In step S1002, the first task event can be assigned to the event processing cluster or functional module of the corresponding secondary subsystem of the corresponding subsystem according to the marking information carried by the first task event; and the chip system is also provided with a main event queue, and the first task event generated by the chip system will be stored in the main event queue of the chip system, and then the event can be read from the main event queue according to the timestamp carried by the first task event, so as to facilitate subsequent event processing.

[0125] In step S1003, in the process of processing the first task event, the corresponding first task event can be read from the main event queue of the chip system according to the timestamp carried by the first task event, and the first task event can also be executed and processed by the assigned functional module or the processing unit in the event processing cluster. Exemplarily, the timestamp carried by one first task event is t0, and the timestamp carried by another first task event is t1, and the first task event with the timestamp t0 is assigned to the first functional module of the chip system, and the first task event with the timestamp t1 is assigned to the second functional module of the chip system; the first task event with the timestamp t0 and the first task event with the timestamp t1 are both stored in the main event queue of the chip system. When the time t0 arrives, the first task event with the timestamp t0 can be read from the main event queue, and the first task event can be executed and processed by the assigned first functional module; similarly, when the time t1 arrives, the first task event with the timestamp t1 can be read from the main event queue, and the first task event can be executed and processed by the assigned second functional module.

[0126] In step S1001 to step S1003, in the process of processing the first task event generated by the chip system, the first task event of the chip system is first obtained; then, the first task event is assigned to the corresponding functional module or event processing cluster according to the mark information carried by the first task event, and the first task event is also stored in the main event queue of the chip system; subsequently, the corresponding first task event can be read from the main event queue according to the timestamp, and the first task event can be executed and processed using the corresponding functional module or event processing cluster, so that the first task event can be executed and processed well. Exemplarily, a chip system includes two subsystems, namely a first subsystem and a second subsystem, the first subsystem includes a first secondary subsystem and a second secondary subsystem, the second subsystem includes a third secondary subsystem and a fourth secondary subsystem, the first secondary subsystem includes a first event processing cluster and a first functional module, the second secondary subsystem includes a second event processing cluster and a second functional module, the third secondary subsystem includes a third event processing cluster and a third functional module, and the fourth secondary subsystem includes a fourth event processing cluster and a fourth functional module; the first event processing cluster can be marked as 111, the first functional module can be marked as 112, the second event processing cluster can be marked as 121, the second functional module can be marked as 122, the third event processing cluster can be marked as 211, the third functional module can be marked as 212, the fourth event processing cluster can be marked as 221, and the fourth functional module can be marked as 222. When the tag information carried by a first task event is 222 and the timestamp is t1, the first task event can be assigned to the fourth functional module of the chip system according to the tag information 222, and the first task event will also be stored in the main event queue of the chip system; when the time t1 arrives, the first task event can be read from the main event queue, and the fourth functional module of the chip system executes and processes the first task event.

[0127] In one embodiment, referring to Fig.14 As shown, the event processing method of the embodiment of the present disclosure also includes:

[0128] Step S1101, obtaining a second task event of a functional module, wherein the second task event carries a timestamp;

[0129] Step S1102, storing the second task event in the main event queue of the chip system;

[0130] Step S1103 , reading the corresponding second task event from the main event queue according to the timestamp, and executing the second task event using the corresponding function module.

[0131] In step S1101, the functional module in the chip system can also generate an event. In the disclosed embodiment, the event generated by the functional module is a second task event. In the disclosed embodiment, the task events are distinguished by "first" and "second", mainly to distinguish the events generated by different subjects, so that the process of explanation can be clearer. In addition, the second task event also carries a timestamp, and the second task event generated by the functional module can be executed according to the timestamp. Exemplarily, the timestamp of the second task event generated by a functional module is t0, so the second task event will be executed at time t0 later.

[0132] It is worth noting that the functional modules in the embodiments of the present disclosure may include a scalar unit, a vector unit, a copy engine, and a tensor core processing unit, etc., wherein the scalar unit is used to perform scalar operations, the vector unit is used to perform vector operations, the copy engine is used to perform copy operations, and the tensor core processing unit is used to perform matrix multiplication and accumulation operations. Exemplarily, the functional module in a secondary subsystem is a vector unit, and when the vector unit needs to perform vector operations, a second task event can be generated.

[0133] In step S1102, the second task events generated by the functional modules of the chip system are stored in the main event queue of the chip system, and then the corresponding second task events can be read from the main event queue of the chip system according to the timestamp carried by the second task events, in preparation for subsequent event processing.

[0134] In step S1103, in the process of processing the second task event generated by the functional module of the chip system, when the time corresponding to the timestamp arrives, the corresponding second task event will be read from the main event queue of the chip system, and the corresponding functional module will be used to execute the second task event. Exemplarily, the functional module is a scalar unit, and the second task event will be generated in the process of the scalar unit needing to perform scalar operations, and the timestamp carried by the second task event is t1, and the second task event is stored in the main event queue of the chip system; when the time t1 arrives, the second task event can be read from the main event queue, and the scalar unit is used to execute the second task event.

[0135] In step S1101 to step S1103, in the process of processing the second task event generated by the functional module, first obtain the second task event of the functional module, wherein the second task event carries a timestamp; then store the second task event in the main event queue of the chip system; finally read the corresponding second task event from the main event queue according to the timestamp carried by the second task event, and use the corresponding functional module to execute the second task event to process the event generated by the functional module. Exemplarily, the chip system includes two subsystems, namely a first subsystem and a second subsystem, the first subsystem includes a first secondary subsystem and a second secondary subsystem, the second subsystem includes a third secondary subsystem and a fourth secondary subsystem, the first secondary subsystem includes a first event processing cluster and a vector unit, the second secondary subsystem includes a second event processing cluster and a scalar unit, the third secondary subsystem includes a third event processing cluster and a replication engine, and the fourth secondary subsystem includes a fourth event processing cluster and a tensor core processing unit; during the operation of the chip system, the replication engine needs to perform a replication operation to generate a second task event, and the timestamp of the generated second task event is t1; the scalar unit needs to perform scalar operations and generate another second task event, and the timestamp of the generated second task event is t2, and t1<t2; the second task event corresponding to the replication engine and the second task event corresponding to the scalar unit are both stored in the main event queue of the chip system; when the time t1 arrives, the second task event corresponding to the replication engine will be read from the main event queue first, and the replication engine will be used to execute the second task event; subsequently, when the time t2 arrives, the second task event corresponding to the scalar unit will be read from the main event queue first, and the scalar unit will be used to execute the second task event.

[0136] Description of the apparatus and device of the present disclosure

[0137] Reference Fig.15 The present disclosure provides an event processing device 1600, which is used to test a chip system. The chip system includes multiple event processing clusters, and the event processing clusters include multiple processing units. The event processing device includes:

[0138] An acquisition unit 1610 is used to acquire discrete events to be processed of each processing unit in the chip system, wherein each discrete event to be processed carries a timestamp;

[0139] The transfer unit 1620 is used to store the discrete events to be processed of different event processing clusters into the event queues of the corresponding event processing clusters, wherein one event processing cluster corresponds to one event queue;

[0140] The execution unit 1630 is used to process each event queue in parallel using different sub-threads, wherein the discrete events to be processed are read from the event queue to the sub-threads according to the timestamps, and the discrete events to be processed are executed by the sub-threads.

[0141] The event processing device 1600 disclosed in the present invention is used to execute the event processing method as in the above embodiment. The specific processing process is the same as the event processing method in the above embodiment, and will not be repeated here.

[0142] An embodiment of the present disclosure also provides an electronic device 1700, comprising: at least one processor, and a memory communicatively connected to the at least one processor; wherein the memory stores instructions, and the instructions are executed by the at least one processor so that when the at least one processor executes the instructions, a method as described in any one of the above embodiments of the present disclosure is implemented.

[0143] Combine the following Fig.16 The hardware structure of the electronic device is described in detail. The electronic device includes: a processor 1710 , a memory 1720 , an input / output interface 1730 , a communication interface 1740 and a bus 1750 .

[0144] The processor 1710 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present disclosure;

[0145] The memory 1720 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1720 can store an operating system and other application programs. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory 1720, and the processor 1710 calls and executes the event processing method of the embodiment of the present disclosure;

[0146] Input / output interface 1730, used to implement information input and output;

[0147] Communication interface 1740, used to realize communication interaction between the device and other devices, which can be realized through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.); and

[0148] The bus 1750 transmits information between the various components of the device (e.g., the processor 1710, the memory 1720, the input / output interface 1730, and the communication interface 1740);

[0149] The processor 1710 , the memory 1720 , the input / output interface 1730 , and the communication interface 1740 are connected to each other in communication within the device via a bus 1750 .

[0150] The embodiments of the present disclosure also provide a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the event processing method of the above embodiments, which will not be repeated here.

[0151] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0152] It should be understood that in the present disclosure, "at least one (item)" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple. It should be understood that in the description of the embodiments of the present disclosure, the meaning of multiple (or multiple) is more than two, greater than, less than, more than, etc. are understood to exclude the number, and above, below, within, etc. are understood to include the number.

[0153] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0154] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0156] It should also be understood that the various implementations provided in the embodiments of the present disclosure can be combined arbitrarily to achieve different technical effects.

[0157] The above is a specific description of the implementation methods of the present disclosure, but the present disclosure is not limited to the above implementation methods. Technical personnel familiar with the art can also make various equivalent modifications or substitutions without violating the spirit of the present disclosure. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.

Claims

1. An event processing method, characterized in that: For testing a chip system, the chip system includes a plurality of event processing clusters, the event processing clusters include a plurality of processing units, the method includes: Acquire discrete events to be processed of each of the processing units in the chip system, wherein each of the discrete events to be processed carries a timestamp; storing the to-be-processed discrete events of different event processing clusters into the event queues of the corresponding event processing clusters respectively, wherein one event processing cluster corresponds to one event queue; Different sub-threads are used to process each of the event queues in parallel, wherein the discrete events to be processed are read from the event queue to the sub-threads according to the timestamps, and the discrete events to be processed are executed by the sub-threads.

2. The event processing method according to claim 1, characterized in that: The storing the to-be-processed discrete events of different event processing clusters into the event queues of the corresponding event processing clusters respectively includes: Obtaining queue index information of the event processing cluster; According to the queue index information, the to-be-processed discrete events in the event processing cluster are stored in the event queue of the corresponding event processing cluster.

3. The event processing method according to claim 1, characterized in that: The step of reading the discrete event to be processed from the event queue to the sub-thread according to the timestamp, and executing the discrete event to be processed by using the sub-thread includes: Get the current running time; Matching the current running time with the timestamp of the discrete event to be processed; When the current running time matches the timestamp, reading the to-be-processed discrete event corresponding to the timestamp from the event queue to the sub-thread corresponding to the event queue; The discrete event to be processed is executed and processed by the sub-thread.

4. The event processing method according to claim 3, characterized in that: When there are multiple sub-threads corresponding to the event queue, executing the to-be-processed discrete event by the sub-threads includes: The discrete events to be processed are processed in parallel by using a plurality of the sub-threads.

5. The event processing method according to claim 3, characterized in that: The step of reading the to-be-processed discrete event corresponding to the timestamp from the event queue to the sub-thread corresponding to the event queue includes: Determining the number of the discrete events to be processed corresponding to the timestamp to obtain the number of events to be processed; The sub-thread is obtained by dividing the preset main thread according to the number of events to be processed; The discrete events to be processed are read into the sub-thread.

6. The event processing method according to claim 3, characterized in that: When there is one child thread corresponding to the event queue, executing the to-be-processed discrete event through the child thread includes: The corresponding discrete events to be processed are executed and processed respectively by the sub-threads.

7. The event processing method according to claim 1, characterized in that: The sub-thread is obtained by dividing the preset main thread, and after the discrete event to be processed is read from the event queue to the sub-thread according to the timestamp, and the discrete event to be processed is executed by the sub-thread, the method further includes: Obtaining the synchronization time node of the main thread; The main thread and the sub-thread are synchronized according to the synchronization time node.

8. The event processing method according to claim 1, characterized in that: Each of the discrete events to be processed also carries a priority. After the discrete events to be processed of different event processing clusters are respectively stored in the event queues of the corresponding event processing clusters, the method further includes: Comparing the priorities of the discrete events to be processed in the event queue to obtain priority sorting information; Determining the execution order of the discrete events to be processed according to the priority sorting information; The corresponding discrete events to be processed are read from the event queue according to the execution order to the sub-thread, and the discrete events to be processed are executed by using the sub-thread.

9. The event processing method according to claim 1, characterized in that: The chip system further includes a subsystem control module and a plurality of subsystems, wherein the plurality of subsystems are connected to the subsystem control module, each of the subsystems includes a control logic processing unit and a plurality of secondary subsystems, wherein the plurality of secondary subsystems are connected to the control logic processing unit, each of the secondary subsystems includes a function module and the event processing cluster, and the method further includes: Acquire a first task event of the chip system, wherein the first task event carries marking information and the timestamp; Allocating the first task event to the corresponding functional module or the event processing cluster according to the tag information; and storing the first task event in the main event queue of the chip system; The corresponding first task event is read from the main event queue according to the timestamp, and the first task event is executed and processed by using the corresponding functional module or the event processing cluster.

10. The event processing method according to claim 9, characterized in that: The method further comprises: Acquire a second task event of the functional module, wherein the second task event carries the timestamp; Storing the second task event in the main event queue of the chip system; The corresponding second task event is read from the main event queue according to the timestamp, and the corresponding functional module is used to execute and process the second task event.

11. An event processing device, characterized in that: The event processing device is used to test the chip system, the chip system includes multiple event processing clusters, the event processing clusters include multiple processing units, and the event processing device includes: An acquisition unit, used for acquiring discrete events to be processed of each of the processing units in the chip system, wherein each of the discrete events to be processed carries a timestamp; A transfer unit, used for storing the to-be-processed discrete events of different event processing clusters into the event queues of the corresponding event processing clusters, wherein one event processing cluster corresponds to one event queue; An execution unit is used to process each of the event queues in parallel using different sub-threads, wherein the discrete events to be processed are read from the event queues to the sub-threads according to the timestamps, and the discrete events to be processed are executed by using the sub-threads.

12. An electronic device, characterized in that: The electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory. When the program is executed by the processor, the event processing method described in any one of claims 1 to 10 is realized.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the event processing method according to any one of claims 1 to 10.

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