Interrupt method, interrupt device, CPU architecture, computer program and storage medium

Abstract

The present invention discloses an interrupt method, an interrupt device, a CPU architecture, a computer program and a storage medium, which solve the problem of reduced execution efficiency caused by CPU waiting for cache loading. By configuring an interrupt cache and loading an interrupt processing program or a specified program fragment, the CPU directly fetches instructions from the cache for execution when interrupted, thereby reducing waiting time. The device includes a configuration loading and interrupt execution unit, and optimizes data transmission by using a DMA controller and a cache address register. The CPU architecture is combined with a cache storage program to achieve efficient interrupt processing. The computer program and the storage medium also implement the method, thereby improving execution efficiency and reducing CPU power consumption. The method is particularly suitable for scenarios where interrupts are frequent or require rapid response.

Description

Technical Field

[0001] The present invention relates to the technical field of interrupt processing optimization, and in particular to an interrupt method, an interrupt device, a CPU architecture, a computer program and a storage medium. Background Art

[0002] When a computer CPU (central processing unit) with a cache executes instructions, it first loads instructions and data from the memory into the internal cache, then fetches instructions from the internal cache, decodes instructions, and reads instructions. This process can be performed synchronously, that is, after the first instruction is loaded, the first instruction is executed at the same time, and subsequent instructions and data are loaded during the execution of the first instruction. However, the speed of loading instructions and data from the memory to the cache is often lower than the speed of instruction execution. Therefore, the CPU needs to waste time waiting for the loading process to be completed (usually loading a group of data). After the loading is completed, the CPU will execute the instructions already in the cache with maximum efficiency, and the CPU performance will be maximized.

[0003] However, the cache size in the computer CPU is much smaller than the memory size. Therefore, when encountering jump, interrupt and other instructions during the execution of instructions, sometimes it jumps to the instruction and data area that is not in the cache. It is necessary to put the data and code in the cache back into the memory first, and then load the new instruction and data from the memory into the cache. In this way, the CPU will be idle because of placing instructions and data back to the memory and loading instructions and data from the memory to the cache, which greatly reduces the CPU execution efficiency.

[0004] There are peripherals in the computer. Peripherals are devices that exchange data with the outside world. When these peripherals receive data, they will send an interrupt signal to the computing CPU at any time. After receiving the interrupt signal, the computer CPU will pause from the current execution instruction and jump to the interrupt handler. If the interrupt handler and data are not in the cache at this time, the instructions and data in the cache need to be put back into the memory first, and then the instructions and data of the interrupt handler are loaded from the memory into the cache. Such frequent execution will reduce the CPU execution efficiency.

[0005] In addition to interrupt programs, long jumps in general programs, such as when the next instruction is not in the cache, also require the instructions and data in the cache to be put back into the memory, and then new instructions and data are loaded from the memory into the cache. This situation will also cause the CPU to wait for the cache to be loaded, resulting in reduced execution efficiency.

[0006] Therefore, there is an urgent need for an interrupt method, an interrupt device, a CPU architecture, a computer program and a storage medium. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present application provides an interrupt method, an interrupt device, a CPU architecture, a computer program and a storage medium to solve the technical problem that the CPU waits for the cache to be loaded, resulting in reduced execution efficiency.

[0008] The present invention can effectively improve the execution efficiency when the CPU encounters an interrupt or a long jump to certain frequently called program fragments; the cache loading function is started, and by executing the start cache loading instruction in the program, the program instructions and data that may be executed next by the program being executed can be preloaded into the cache, thereby improving the execution efficiency.

[0009] In one aspect, the present invention provides an interruption method, comprising the following steps: A configuration loading step, configuring an interrupt cache and loading an interrupt handler into the cache, or configuring the interrupt cache to load a specified program fragment, wherein when it is detected that the interrupt frequency exceeds a preset threshold, the system controller enables the interrupt cache function; Interrupt execution step: when the CPU is interrupted, it directly fetches instructions from the interrupt cache, decodes instructions, executes instructions and generates the address of the next instruction. During the interrupt execution process, the cache load instruction is called to load the specified program or data fragment into the cache.

[0010] Furthermore, the configuration loading step also includes configuring the interrupt cache for loading the interrupt handler's size, addressing range, and determining whether to use the interrupt cache function.

[0011] Furthermore, before the configuration loading step, it also includes a step of starting an interrupt cache loading instruction, which is used to start loading the instruction slice and data slice of the specified address into the interrupt cache.

[0012] Furthermore, the interrupt execution step also includes an interrupt instruction address judgment sub-step. When the interrupt handler is not in the interrupt cache, the automatic loading mechanism is triggered according to the interrupt priority, the interrupt handler is loaded into the interrupt cache, and it is judged whether to jump to the interrupt instruction address.

[0013] Furthermore, in the interrupt handling program, a designated program or data may be loaded into the cache by calling a cache loading instruction, and the process of loading the program or data into the cache is performed concurrently with the execution of the interrupt handling program.

[0014] In another aspect, the present invention provides an interruption device, comprising: The configuration loading unit includes a cache address register, a DMA controller, and a bus interface circuit, and is used to configure the parameters of the interrupt cache through the bus protocol. The cache address register is used to store the address information of the interrupt cache, the DMA controller is used to control the transmission of data between the memory and the interrupt cache, and the bus interface circuit is used to realize the communication and data transmission between the configuration loading unit and the CPU or other external devices.

[0015] The interrupt execution unit includes an instruction decoder, an execution unit, and a multi-level cache architecture (such as L1 cache, L2 cache, etc.), which is used to fetch instructions directly from the interrupt cache, decode instructions, execute instructions, and generate the address of the next instruction when the CPU is interrupted. Among them, the multi-level cache architecture is used to store instructions and data to reduce the time the CPU spends accessing memory and improve the efficiency of interrupt processing. The instruction decoder is used to decode the instructions taken from the interrupt cache, and the execution unit is used to execute the decoded instructions.

[0017] Furthermore, the configuration loading unit also includes a logic circuit for configuring the interrupt cache for loading the interrupt handler, the size, addressing range and judging whether to use the interrupt cache function; and a start interrupt cache loading instruction unit, which loads the instruction slice and data slice of the specified address into the interrupt cache through the DMA controller and the cache address register; and also includes an interrupt instruction address judgment subunit, which is used to automatically load the interrupt handler into the interrupt cache through the DMA controller when the interrupt handler is not in the interrupt cache and judges whether to jump to the interrupt instruction address.

[0018] In another aspect, the present invention provides a CPU architecture, comprising: a CPU and a cache, wherein: The cache stores computer programs; The CPU implements the interrupt method by running the computer program stored in the cache.

[0019] In yet another aspect, the present invention provides a computer program, which implements the interruption method when the computer program is executed.

[0020] On the other hand, the present invention provides a storage medium, which is a readable storage medium and stores instructions, and the instructions are used to execute the interruption method.

[0021] In summary, the present application provides an interruption method, an interruption device, a CPU architecture, a computer program, and a storage medium, which have the following beneficial effects: 1. The interrupt method, interrupt device, CPU architecture, computer program and storage medium are used for the situation of frequent interrupts. Since the interrupt handler can place the interrupt handler instructions and data into the interrupt cache when the computer is turned on by loading the interrupt cache instruction, the CPU can directly execute the interrupt handler without waiting for the interaction time between the cache and the memory, thereby improving the execution efficiency. 2. The interrupt method, interrupt device, CPU architecture, computer program and storage medium can pre-load program instructions and data that may be executed in the next step after the interrupt occurs into the cache by executing the startup cache loading instruction in the interrupt program. After the interrupt processing function is executed, there is no need to wait for the interaction between the cache and the memory or reduce the waiting time, thereby improving the execution efficiency and reducing the CPU power consumption; some program fragment instructions and data that are often jumped to can also be stored in the interrupt cache to improve the execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is the overall framework diagram of the present invention.

[0023] Figure 2 Start the driver initialization flowchart for the system.

[0024] Figure 3 This is the instruction execution flow chart of the CPU when using the interrupt cache.

[0025] Figure 4 The interrupt handler loads the application execution flow chart related to the interrupt. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] See also Figure 1 The present invention provides an interruption method, comprising the following steps: Configure the loading step, and flexibly configure the size, location and other parameters of the interrupt cache according to system requirements and hardware resources. These parameters can be dynamically adjusted according to the actual operation situation to ensure the efficient use of the interrupt cache. After the interrupt cache is configured, the system will load the interrupt handler into the interrupt cache. This process includes reading the interrupt handler code from the storage medium and storing it in the specified location of the interrupt cache. By directly storing the interrupt handler in the cache, the delay during interrupt processing can be significantly reduced and the system response speed can be improved. In addition to loading the interrupt handler, the present invention also allows the user to configure the interrupt cache as needed to load the specified program fragment, which can be achieved by setting the cache address, size and other parameters, including: ‌Specific steps for configuring interrupt cache‌: By presetting the interrupt cache address range, a dedicated memory area in the system is designated as the interrupt cache; ‌Cache allocation method‌: Use static allocation or dynamic allocation to allocate appropriate memory space for the interrupt cache according to the size of the interrupt handler and the real-time requirements of the system; ‌Loading mechanism‌: Direct memory access (DMA) is used to quickly and efficiently load interrupt handlers from the storage medium into the interrupt cache, so that the interrupt handler can be responded to and executed quickly when an interrupt occurs.

[0028] When these program fragments need to be executed, the system can read them directly from the interrupt cache without having to load them from the storage medium again, thereby improving execution efficiency. During system operation, the system will dynamically adjust the configuration of the interrupt cache according to the actual operation situation. For example, when it is found that a certain interrupt handler or program fragment is frequently accessed, the system can automatically increase its cache size or optimize its storage location to improve access speed; Interrupt execution step: When the CPU is interrupted by an interrupt, it will immediately respond to the interrupt and prepare to execute the interrupt service program. In the interrupt service program, the CPU directly fetches instructions from the interrupt cache for execution. The interrupt cache is a cache area specifically used to store the instructions required during the interrupt processing process, which can significantly improve the access speed of instructions. The CPU decodes and executes the instructions according to the predetermined process and generates the address of the next instruction. During the interrupt execution process, if the specified program or data fragment needs to be loaded into the cache, the CPU will call the cache load instruction. This instruction will instruct the cache controller to read the required data or program code from the memory and load it into the cache. Since the access speed of the cache is much faster than that of the memory, this step can significantly improve the access speed of the data. When the interrupt service program is executed, the CPU will restore the execution state of the previously interrupted program and continue to execute the next instruction. By directly fetching and executing instructions from the interrupt cache, the delay in the interrupt processing process is reduced and the response speed of the CPU is improved. Calling the cache load instruction during the interrupt execution process can ensure that the required data or program code can be quickly loaded into the cache, further improving the access speed of the data.

[0029] The application scenarios of this solution include: Memory and CPU (Central Processing Unit): Memory is also called internal memory and main memory. It is used to temporarily store calculation data in the CPU and exchange data with external memory such as hard disk.

[0030] The central processing unit (CPU) is one of the main devices of an electronic computer and the core component of a computer. Its main function is to interpret computer instructions and process data in computer software. The CPU is the core component of a computer that is responsible for reading instructions, decoding instructions and executing instructions. The central processing unit mainly consists of two parts, namely the controller and the arithmetic unit, which also includes the cache and the data and control bus that realizes the connection between them. The three core components of an electronic computer are the CPU, internal memory, and input / output devices. The functions of the central processing unit are mainly to process instructions, execute operations, control time, and process data.

[0031] When a computer CPU (central processing unit) with a cache executes instructions, it first loads instructions and data from the memory into the internal cache, and then fetches instructions, decodes instructions, and reads instructions from the internal cache. This process can be performed synchronously, that is, after the first instruction is loaded, the first instruction can be executed, and subsequent instructions and data are loaded during the execution of the first instruction. However, often because the speed of loading instructions and data from the memory to the cache is lower than the speed of instruction execution, the CPU needs to waste time waiting for the loading process to complete (often loading a set of data). After the loading is completed, the CPU will execute the instructions already in the cache with maximum efficiency, and the CPU performance will be maximized.

[0032] However, the cache size in the computer CPU is much smaller than the memory size. Therefore, when encountering jump, interrupt and other instructions during the execution of instructions, sometimes it jumps to the instruction and data area that is not in the cache. It is necessary to put the data and code in the cache back into the memory first, and then load the new instruction and data from the memory into the cache. In this way, the CPU will be idle because of placing instructions and data back to the memory and loading instructions and data from the memory to the cache, which greatly reduces the CPU execution efficiency.

[0033] Instruction fetch (IF) is the process of fetching an instruction from main memory to the instruction register. The value in the program counter is used to indicate the location of the current instruction in main memory. When an instruction is fetched, the value in the PC will automatically increase according to the instruction word length.

[0034] Decode instructions (ID, instructiondecode), take out the instructions to be executed, and the instruction decoder will perform detailed splitting and interpretation of the retrieved instructions according to the predetermined instruction format. This process includes identifying the various components of the instruction, such as the opcode, addressing mode, etc., and parsing the specific meaning and expected operation of the instruction. Based on the splitting and interpretation of the instruction, the instruction decoder can accurately identify and distinguish different instruction categories. These categories may include arithmetic instructions, logic instructions, control instructions, etc. By accurately identifying the instruction category, the instruction decoder can provide correct guidance for subsequent instruction execution. For each instruction, the instruction decoder also needs to determine the method of obtaining the operand. The operation data is the data required during the execution of the instruction, and its acquisition method may include direct addressing, indirect addressing, immediate addressing, and other methods. The instruction decoder will select the most appropriate operand acquisition method based on the specific requirements of the instruction and the actual configuration of the system. After completing the splitting, interpretation, category identification, and determination of the operand acquisition method of the instruction, the instruction decoder will prepare the corresponding execution environment, such as setting register values, allocating memory space, etc., to ensure that the instruction can be executed smoothly.

[0035] Execute instructions (EX) implement the functions of the instructions. Different parts of the CPU are connected to perform the required operations.

[0036] When a computer executes an instruction, it will process it according to the predetermined logic and write the result data back to the specified storage location. After the instruction is executed and the result data is written back, the computer will immediately perform an unexpected event detection. This includes but is not limited to result overflow, memory access error, etc. If an unexpected event is detected, the computer will handle it according to the preset strategy, such as interrupting the current execution process, recording error logs, etc. If no unexpected event occurs, the computer will obtain the address of the next instruction from the program counter. The program counter is a special register that stores the address of the currently executed instruction and the address of the next instruction to be executed. By reading the value of the program counter, the computer can accurately locate the next instruction. After obtaining the address of the next instruction, the computer will enter a new round of loops. It will fetch instructions, execute instructions, write back results, and perform unexpected event detection again according to the same process. This process will be repeated until the program is executed or a specific termination condition is encountered.

[0037] refer to Figure 2 , Figure 2 Start the driver initialization flowchart for the system.

[0038] The first is system power-on and system initialization. Through the pre-designed interrupt cache configuration, when the peripheral driver is initialized, the instruction data related to the interrupt in the driver is placed in the internal interrupt processing cache of the CPU by executing the cache loading instruction. The peripheral interrupt handler is resident in the interrupt cache. When an interrupt arrives, the currently executed instruction will be paused and jump to the interrupt handler. After the interrupt handler is executed, other drivers will be loaded and initialized. This process will no longer need to put the currently executed instruction and data cache back into the memory, nor does it need to load the interrupt processing instructions and data from the memory into the cache. It can directly jump to the interrupt handler for execution, saving CPU waiting time and improving CPU execution efficiency. This interrupt cache used to place interrupt handlers for a long time can be solidified in size when designing and producing processors, or it can be allocated on demand by placing general caches and designing corresponding CPU instructions.

[0039] refer to Figure 3 , Figure 3 This is the instruction execution flow chart of the CPU when using the interrupt cache.

[0040] start; Step 1: Prepare to fetch instructions; Step 2: Determine whether the instruction address is in the interrupt cache. If yes, proceed to step 3a; otherwise, proceed to step 3b. Step 3a, fetching instructions from the interrupt cache; Step 3b, fetching instructions from the general cache; Step 4: After step 3a and step 3b are completed, step 4 is entered to determine whether the instruction fetch is successful. If so, step 5a is entered; otherwise, step 5b is entered. Step 5a, decode the instruction, calculate the address (location) of the next instruction, and proceed to step 6a; Step 5b, determine whether the instruction address belongs to the instruction address range of the interrupt handler, if yes, proceed to step 6b, if not, proceed to step 6c; Step 6a, detect whether there is an interruption and obtain the interruption signal, if yes, go to step 7a, if no, go back to step 1; Step 6b, loading the interrupt handler instructions and data to which the instruction belongs into the interrupt cache, and proceeding to step 7b; Step 6c, first save the original cache instructions and data to the memory, then load the program instructions and data slices to which the instruction address belongs to into the general cache, and proceed to step 7b; Step 7a, using the interrupt number as an index, makes the next instruction address the first instruction address of the interrupt handler, and returns to step 1 after completion; Step 7b, wait for a predetermined number of instructions and data to be stored in the cache, and return to step 1.

[0041] refer to Figure 4 , Figure 4 The interrupt handler loads the application execution flow chart related to the interrupt.

[0042] The application's operating process: The application starts; Application initialization; After receiving this information, the driver will communicate with the peripherals efficiently to ensure that the peripherals can execute correctly according to the instructions of the application. At the same time, in this step, the application will be ready to load the interrupt program at any time so that it can respond quickly when the peripheral operation is completed or an exception occurs. In order to optimize the interrupt processing process, the present invention allows the application to pass instruction parameters, such as App_addr or Data_addr, when loading the interrupt program, so that the interrupt handler can more accurately understand the cause of the interrupt and take corresponding processing measures, optimize the peripheral calling process, significantly improve the interaction efficiency between the application and the peripheral, reduce delays and redundancy, allow the application to pass instruction parameters when loading the interrupt program, improve the accuracy and response speed of interrupt processing, and adopt concurrent processing technology, so that the application can continue to perform other tasks while waiting for the peripheral operation to complete, thereby improving the overall operation efficiency of the system; If no interrupts are loading, the application continues to run normally.

[0043] Interrupt program running process: Interrupt handler entry; Execute the boot cache load instruction and pass App_addr and Data_addr as instruction parameters to the processor; Interrupt other processing, that is, you can load and interrupt other processing at any time; Finish.

[0044] Among them, the startup cache loading instruction is executed, and App_addr and Data_addr are passed to the processor as instruction parameters. The specific process inside the CPU is: When the CPU is running normally, the instruction scheduler will detect whether it needs to execute a cache load instruction when the CPU executes a normal instruction. If necessary, the instruction scheduler will start the cache load process and pass two key parameters: App_addr (application address) and Data_addr (data address) to the cache controller. The cache controller loads data from the memory into the cache based on these two parameters.

[0045] During the process of loading the cache, the CPU will not stop executing other normal instructions, but continue to execute subsequent instructions. When the cache loading operation is completed, the CPU will seamlessly switch back to executing the normal instructions after the cache loading instruction without any additional waiting time. In addition, the system of the present invention also supports the concurrent processing of the cache loading operation and the execution of other instructions, that is, at the same time, the CPU can execute multiple instructions at the same time, including cache loading instructions and other normal instructions, thereby greatly improving the operating efficiency and response speed of the CPU. By concurrently processing the cache loading operation and other instruction executions, the idle waiting time of the CPU is significantly reduced, the utilization rate and operating efficiency of the CPU are improved, and the cache loading instruction is dynamically scheduled to ensure that data can be loaded from the memory into the cache in time, thereby improving the access speed of the data.

[0046] The present invention provides a CPU architecture, comprising: a CPU and a cache, wherein: The cache stores computer programs; When the CPU runs the computer program stored in the cache, Figure 2 , 3 , the interruption method shown in 4.

[0047] In one embodiment, the present invention provides a computer program that, when executed, implements Figure 2 , 3 , the interrupt method shown in 4.

[0048] In one embodiment, the present invention provides a storage medium, which is a readable storage medium and stores instructions for executing Figure 2 , 3 , the interruption method described in 4.

[0049] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0050] Although the embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. An interruption method, characterized in that Follow these steps: S1: configuration loading step; Configuring an interrupt cache and loading an interrupt handler into the cache, wherein the interrupt cache is configured to load a specified program fragment, wherein when it is detected that the interrupt frequency exceeds a preset threshold, the system controller enables the interrupt cache function; S2: interrupt execution step; When the CPU is interrupted by an interrupt, it directly fetches instructions from the interrupt cache, decodes the instructions, executes the instructions, generates the address of the next instruction, and calls the cache load instruction during the interrupt execution process to load the specified program or data fragment into the cache.

2. The interruption method according to claim 1, characterized in that: The step S1: configuration loading step includes configuring the interrupt cache and the size and addressing range for loading the interrupt processing program, and when the interrupt frequency is detected to exceed a preset threshold, the system controller determines whether to enable the interrupt cache.

3. The interruption method according to claim 1, characterized in that: The step S1: before the configuration loading step, includes starting the interrupt cache loading instruction step, loading the instruction slice and data slice of the specified address into the interrupt cache.

4. The interruption method according to claim 1, characterized in that: The step S2: interrupt execution step includes interrupt instruction and address judgment sub-steps. When the interrupt handler is not in the interrupt cache, the automatic loading mechanism is triggered according to the interrupt priority, the interrupt handler is loaded into the interrupt cache, and it is judged whether to jump to the interrupt instruction address.

5. The interruption method according to claim 1, characterized in that: The step S2: in the interrupt execution step, the specified program or data is loaded into the cache by calling the cache loading instruction in the interrupt processing program, and the process of loading the program or data into the cache is performed concurrently with the execution of the interrupt processing program.

6. An interruption device, comprising an interruption method as claimed in any one of claims 1 to 5, characterized in that: include: Configure the load unit and interrupt execution unit; A configuration loading unit, including a cache address register, a DMA controller and a bus interface circuit, is used to configure the parameters of the interrupt cache through a bus protocol. The cache address register is used to store the address information of the interrupt cache. The DMA controller is used to control the transmission of data between the memory and the interrupt cache. The bus interface circuit is used to realize the communication and data transmission between the configuration loading unit and the CPU. The interrupt execution unit includes an instruction decoder, an execution unit and a multi-level cache architecture, which is used to directly fetch instructions from the interrupt cache, decode instructions, execute instructions and generate the address of the next instruction when the CPU is interrupted. The multi-level cache architecture is used to store instructions and data. The instruction decoder is used to decode the instructions taken from the interrupt cache, and the execution unit is used to execute the decoded instructions.

7. The interruption device according to claim 6, characterized in that: The configuration loading unit also includes a logic circuit for configuring the interrupt cache for loading the interrupt processing program, an addressing range, and determining whether to use the interrupt cache function, and a startup interrupt cache loading instruction unit, wherein the startup interrupt cache loading instruction unit loads the instruction slice and the data slice of the specified address into the interrupt cache through the DMA controller and the cache address register; It also includes an interrupt instruction address judgment subunit, which is used for automatically loading the interrupt processing program into the interrupt cache through the DMA controller when the interrupt processing program is not in the interrupt cache and judging whether to jump to the interrupt instruction address.

8. CPU architecture, characterized in that, include: A CPU and a cache memory in which a computer program is stored; The CPU implements the interrupt method according to any one of claims 1 to 5 by running the computer program stored in the cache.

9. A computer program, characterized in that: When the computer program is executed, the interruption method according to any one of claims 1 to 5 is implemented.

10. A storage medium, characterized in that include: A storage medium, wherein the storage medium is a readable storage medium and stores instructions, wherein the instructions are used to execute the interruption method according to any one of claims 1 to 5.

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