Storage data reading method, device, system, equipment, medium and product

Abstract

According to the storage data reading method, device, system, equipment, medium and product provided by the invention, in the method, the test system can send the data reading instruction to the tested equipment through the preset interface of the tested equipment when the CPU of the tested equipment fails. And the tested equipment starts a data reading path according to the data reading instruction, and reads the cache data of the cache memory through the data reading path. And receiving cache data sent by the tested equipment, wherein the cache data comprises running data of the CPU before the fault. And sending the cache data to a test system through a preset interface. According to the technical scheme, the test system can perform fault analysis on the CPU of the tested equipment to obtain the fault analysis result, so that the problem that cache data cannot be obtained when the CPU fails is solved, and the fault removal efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, system, equipment, medium and product for reading stored data. Background Art

[0002] System on chip (SOC) is widely used in intelligent devices such as mobile communications. It integrates central processing unit (CPU), memory, input and output modules, etc. Among them, the memory includes cache and main memory. Cache is a small capacity memory, but the access speed is faster than the main memory. Cache can provide instructions and data to the CPU at a high speed, thereby speeding up the execution of the program.

[0003] When the CPU is running, a large amount of data will be stored in the cache. If the CPU fails during operation, the cache data cannot be read, making the debugging efficiency poor. Summary of the invention

[0004] The present application provides a method, device, system, equipment, medium and product for reading stored data, which are used to solve the problem of reading cache data when a CPU exception occurs and improve the efficiency of troubleshooting.

[0005] In a first aspect, the present application provides a method for reading stored data, which is applied to a test system, and the method comprises:

[0006] When a central processing unit (CPU) of the device under test fails, a data reading instruction is sent to the device under test through a preset interface of the device under test, wherein the data reading instruction is used to read the operation data of the CPU before the failure;

[0007] Receiving cache data sent by the tested device, wherein the cache data includes operation data of the CPU before the failure;

[0008] Performing fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result;

[0009] The fault analysis result is outputted.

[0010] In a possible implementation, the cache data is out-of-order data in terms of addresses;

[0011] Performing a fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result includes:

[0012] Parsing the cache data to obtain restored cache data, wherein the restored cache data is ordered data in terms of address;

[0013] According to the restored cache data, a fault analysis is performed on the CPU of the tested device to obtain a fault analysis result.

[0014] In a possible implementation, the cache data includes a plurality of byte data; the cache data is stored in a high-speed cache memory in the device under test, and a storage format of the high-speed cache memory includes a plurality of groups, each group includes a plurality of cache lines, and each cache line includes a plurality of bytes;

[0015] Parsing the cached data to obtain restored cached data includes:

[0016] Acquire a storage file, wherein the storage format of the storage file is the same as the storage format of the cache memory;

[0017] Acquire attribute information of the plurality of byte data, wherein the attribute information of any one byte data among the plurality of byte data includes an identifier of a target group where the byte data is located, an identifier of a target cache line in the target group, and an identifier of a target byte included in the target cache line;

[0018] According to the attribute information of the multiple byte data, the multiple byte data are written into the storage file to obtain the restored cache data.

[0019] In a possible implementation, the test system includes an electronic device and a debugger, and the debugger is connected to the preset interface and the electronic device respectively;

[0020] Sending a data reading instruction to the device under test through a preset interface of the device under test includes:

[0021] The data read instruction is sent to the device under test through the debugger, and the data read instruction is also used to instruct a memory built-in self-test MBIST unit or a non-application processor in the device under test to start a data read path.

[0022] In a possible implementation, the cache memory in the device under test includes a plurality of cache memories at different levels; the plurality of cache memories at different levels are respectively used to store different operation data of the CPU;

[0023] The cache data includes different operating data corresponding to the cache memories of different levels.

[0024] In a second aspect, the present application provides a method for reading stored data, which is applied to a device under test, wherein the device under test includes a system-on-chip (SOC), wherein a central processing unit (CPU) and a cache memory are integrated in the SOC, and wherein the cache memory is used to store operating data of the CPU during operation; the method includes:

[0025] Receiving a data reading instruction through a preset interface, wherein the data reading instruction is used to read the operation data of the CPU before the failure;

[0026] According to the data reading instruction, a data reading path is opened, wherein the data reading path is used to connect the cache memory and the preset interface;

[0027] Reading cache data of the cache memory through the data reading path, wherein the cache data includes operation data of the CPU before the failure;

[0028] The cache data is sent to the test system through the preset interface.

[0029] In a possible implementation, the SOC is further integrated with a memory built-in self-test MBIST unit, and the MBIST unit includes a built-in test controller, a core controller and a built-in test trigger;

[0030] Wherein, the built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface; the core controller is used to access the cache memory, and the built-in test trigger is used to turn on or off the built-in test controller;

[0031] According to the data reading instruction, opening a data reading path includes:

[0032] According to the data read instruction, the built-in test controller is controlled to be turned on through the built-in test trigger so that the data read path is turned on. The data read path is the cache memory, the core controller, the built-in test controller to the preset interface, and the turning-on function of the preset interface is a test function.

[0033] In a possible implementation, the device under test further includes a non-application processor and a temporary storage memory; the SOC further integrates a memory built-in self-test MBIST unit, and the MBIST unit includes a built-in test controller, a core controller and a built-in test trigger;

[0034] The built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface through the non-application processor; the core controller is used to access the cache memory, and the built-in test trigger is used to turn on or off the built-in test controller;

[0035] According to the data reading instruction, opening a data reading path includes:

[0036] Reading the data read instruction by the non-application processor;

[0037] Through the non-application processor, the built-in test trigger is controlled to turn on the built-in test controller so that the data reading path is turned on. The data reading path is the cache memory, the core controller, the built-in test controller, the temporary storage memory to the preset interface, and the activation function of the preset interface is a non-test function.

[0038] In a possible implementation, reading cache data of the cache memory through the data reading path includes:

[0039] Sending the data read instruction to the core controller through the built-in test controller;

[0040] The core controller reads the cache data in the cache memory according to the data read instruction.

[0041] In a possible implementation, the cache memory includes a plurality of cache memories at different levels; the plurality of cache memories at different levels are respectively used to store different operation data of the CPU;

[0042] The cache data includes different operating data corresponding to the cache memories of different levels.

[0043] In a third aspect, the present application provides a storage data reading device, which is applied to a test system, comprising:

[0044] A sending module, used for sending a data reading instruction to the tested device through a preset interface of the tested device when a central processing unit (CPU) of the tested device fails, wherein the data reading instruction is used for reading the operation data of the CPU before the failure;

[0045] A receiving module, used for receiving cache data sent by the tested device, wherein the cache data includes the operation data of the CPU before the failure;

[0046] An analysis module, used to perform fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result;

[0047] An output module is used to output the fault analysis result.

[0048] In a fourth aspect, the present application provides a storage data reading device, which is applied to a device under test, wherein the device under test includes a system-on-chip SOC, wherein a central processing unit CPU and a high-speed cache memory are integrated in the SOC, and the high-speed cache memory is used to store operation data of the CPU during operation; the device includes:

[0049] A receiving module, used for receiving a data reading instruction through a preset interface, wherein the data reading instruction is used for reading the operation data of the CPU before the failure;

[0050] A processing module, configured to open a data reading path according to the data reading instruction, wherein the data reading path is configured to connect the cache memory and the preset interface;

[0051] A reading module, used for reading cache data of the cache memory through the data reading path, wherein the cache data includes operation data of the CPU before the failure;

[0052] The sending module is used to send the cache data to the test system through the preset interface.

[0053] In a fifth aspect, the present application provides a test system, comprising an electronic device, the electronic device comprising a processor, and a memory communicatively connected to the processor;

[0054] The memory stores computer-executable instructions;

[0055] The processor executes the computer-executable instructions stored in the memory to implement the method according to the first aspect.

[0056] In a possible implementation, the test system further includes a debugger, which is connected to a preset interface of the device under test and the electronic device respectively;

[0057] The debugger is used to send a data read instruction to the device under test and transmit cache data, wherein the data read instruction reads the running data of the CPU of the device under test before the failure, and the cache data includes the running data.

[0058] In a sixth aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor;

[0059] The memory stores computer-executable instructions;

[0060] The processor executes the computer-executable instructions stored in the memory to implement the method described in the second aspect.

[0061] In a possible implementation, the processor includes a system-on-chip (SOC), in which a central processing unit (CPU), a high-speed cache memory, and a memory built-in self-test (MBIST) unit connected to the high-speed cache memory are integrated;

[0062] The high-speed cache memory is used to store the operation data of the CPU when it is running;

[0063] The MBIST unit is used to read the cache data in the cache memory.

[0064] In a seventh aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by a computer, are used to implement the method of the first aspect or the second aspect.

[0065] In an eighth aspect, the present application provides a computer program product, comprising a computer program, which is used to implement the method of the first aspect or the second aspect when executed by a computer.

[0066] The present application provides a method, device, system, equipment, medium and product for reading stored data. In this method, when the CPU of the tested device fails, the test system can send a data reading instruction to the tested device through the preset interface of the tested device. According to the data reading instruction, the tested device opens the data reading path and reads the cache data of the cache memory through the data reading path. The cache data sent by the tested device is received, and the cache data includes the operating data of the CPU before the failure. Then, the cache data is sent to the test system through the preset interface. The test system can perform a fault analysis on the CPU of the tested device and obtain a fault analysis result, thereby solving the problem that the cache data cannot be obtained when the CPU fails, and improving the efficiency of troubleshooting. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0068] Figure 1 A schematic diagram of an application scenario applicable to the present application;

[0069] Figure 2 A schematic diagram of a flow chart of a method for reading stored data provided in an embodiment of the present application;

[0070] Figure 3 A schematic diagram of a modulator of a test system exemplified in this application accessing MBIST via a JTAG interface;

[0071] Figure 4 A schematic diagram of a modulator of a test system exemplified in this application accessing a non-application processor through a JTAG interface;

[0072] Figure 5 A schematic diagram of a flow chart of another method for reading stored data provided in an embodiment of the present application;

[0073] Figure 6 A schematic diagram of a cache storage format for an example of this application;

[0074] Figure 7 A schematic diagram of a flow chart of another method for reading stored data provided in an embodiment of the present application;

[0075] Figure 8 A schematic diagram of the structure of a device under test as an example of this application;

[0076] Fig. 9 A schematic diagram of the structure of another device under test as an example of this application;

[0077] Fig.10 A schematic diagram of a flow chart of another method for reading stored data provided in an embodiment of the present application;

[0078] Fig.11 A schematic diagram of the structure of a storage data reading device provided in an embodiment of the present application;

[0079] Fig.12 A schematic diagram of the structure of a storage data reading device provided in an embodiment of the present application;

[0080] Fig.13 A schematic diagram of the structure of a test system provided in an embodiment of the present application;

[0081] Fig.14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0082] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0083] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0084] In SOC, a cache is set between the CPU and the main memory. When the CPU reads or writes the address it needs to find, it first searches in the cache. If the address is found in the cache, the data in the cache is read without accessing the main memory. By effectively utilizing the cache, the number of accesses to the main memory can be significantly reduced, thereby improving overall performance. The cache architectures in SOC mainly include the Big.Little architecture and the DynamIQ architecture. Regardless of the architecture, a large amount of data generated by the CPU operation is stored in the cache. When the CPU fails, such as "running away" or "hanging", the data in the cache cannot be read through the CPU, making the troubleshooting (debugging) efficiency poor.

[0085] Among them, "runaway" means that the CPU cannot execute the program in a normal state after being affected by the interference signal, resulting in program chaos. This situation usually occurs when the interference signal acts on the CPU itself, and the CPU cannot execute instructions normally, causing the program to "runaway". "Hanging" means that the CPU suddenly stops responding during operation, causing the entire system to crash.

[0086] Therefore, the present application provides a method for reading stored data. When the CPU of the device under test fails, the test system can send a data reading instruction to the device under test through a preset interface of the device under test. The device under test can open a data reading path according to the data reading instruction, and read the CPU's running data before the failure in the cache based on the path, and then send it to the test system through a preset interface to implement fault analysis, thereby solving the problem of being unable to obtain cache data when the CPU fails, and improving the efficiency of troubleshooting.

[0087] For ease of understanding, the following Figure 1 The examples are used to illustrate the application scenarios to which the embodiments of the present application are applicable.

[0088] Figure 1 For a schematic diagram of an application scenario applicable to this application, please see Figure 1 , including: a device under test 101 and a test system 102.

[0089] In one possible implementation, when the CPU of the tested device 101 fails, maintenance personnel can connect to the test system 102 through the preset interface of the tested device 101, and read the cache data of the cache in the tested device 101 through the test system 102, so as to read the operating data of the CPU before the failure for fault analysis.

[0090] In a possible implementation, during the development process of the device under test 101, for example, during the testing phase, a fault may be intentionally introduced to cause the CPU to fail. Then, the device under test 101 may be connected to the test system 102 through its preset interface, and the test system 102 may read the cache data in the cache of the device under test 101, so that the running data of the CPU before the failure may be read to perform fault analysis, thereby testing the efficiency of troubleshooting when the CPU of the device under test 101 fails, thereby shortening the development cycle.

[0091] In a possible implementation, the test system 102 may include an electronic device 1021 and a debugger 1022, and the debugger 1022 is respectively connected to the preset interface and the electronic device 1021. It can be understood that the "connection" here refers to electrical connection, which can be achieved through a dedicated connection line.

[0092] In a possible implementation, a memory built-in self test (MBIST) circuit is integrated in the SOC of the device under test 101, and the debugger 1022 may be an emulator Trace32, which may interact with the MBIST through a test function of a preset interface.

[0093] Among them, memory built-in self test (MBIST) is a built-in self test (BIST) circuit, which is a test circuit for embedded chip memory and can realize read and write control of memory cache. The core idea of ​​MBIST is to use the logic circuit inside the memory to perform the test. By integrating the MBIST unit in the SOC, it can be realized to test whether the memory is working normally.

[0094] It can be understood that there may be multiple devices under test 101 and test systems 102, which are not shown in the figure.

[0095] In the embodiment of the present application, the electronic device 1022 may be a server or other device, which may be used for fault analysis.

[0096] In an embodiment of the present application, the device under test 101 may be a terminal device with a cache integrated in a SOC, etc. The terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent or user device.

[0097] The terminal device may be a device that provides voice / data connectivity to the user, for example, a handheld device with wireless connection function, a vehicle-mounted device, etc. At present, some examples of terminals may be: mobile phones, tablet computers (pad), computers with wireless transceiver functions (such as laptops, PDAs, etc.), mobile Internet devices (mobile internet devices, MIDs), virtual reality (virtual reality, VR) devices, augmented reality (augmented reality, AR) devices, extended reality (extended reality, XR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (session initiation protocol, SIP) phones, wireless local loop (wireless local loop, WLL) stations, personal digital assistants (personal The invention relates to a mobile phone or a digital assistant (PDA), a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a 5G network, or a terminal device in a public land mobile communication network (PLMN) to be evolved in the future, etc.

[0098] Among them, wearable devices can also be called wearable smart devices, which are a general term for the intelligent design and development of wearable devices for daily wear using wearable technology, such as glasses, gloves, watches, clothing and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also realize powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include full-featured, large-sized, and independent of smartphones to achieve complete or partial functions, such as smart watches or smart glasses, as well as those that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0099] In addition, the terminal device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection. IoT technology can achieve massive connections, deep coverage, and power saving through narrowband (NB) technology, for example.

[0100] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments may exist independently or in combination with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0101] Figure 2 A flowchart of a method for reading stored data provided in an embodiment of the present application, which can be executed by a test system, is shown in FIG. Figure 2 , the method comprises the following steps:

[0102] S201. When a CPU of a tested device fails, a data reading instruction is sent to the tested device through a preset interface of the tested device, where the data reading instruction is used to read the running data of the CPU before the failure.

[0103] When the CPU of the device under test fails, the maintenance personnel can connect the test system to the preset interface of the device under test to achieve connection with the device under test, and the test system can send data reading instructions to the device under test through the preset interface.

[0104] S202: Receive cache data sent by the tested device, where the cache data includes CPU operation data before the failure.

[0105] The test system can receive the cache data sent by the tested device, and the cache data includes the operation data of the CPU before the failure.

[0106] Exemplarily, the operation data may include instruction data, data used when the program is running, etc., wherein instruction data is when the CPU executes the program, and multiple instructions are usually loaded into the cache, which helps to understand what operations the CPU was performing before the failure occurred. The data used when the program is running may include, for example, variable values, calculation results, and temporary data, etc., which can help analyze the status and data flow of the program.

[0107] S203: Perform fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result.

[0108] After the test system obtains the cache data, it can perform fault analysis on the CPU of the device under test based on the cache data.

[0109] In one possible implementation, the cache data is composed of a string of unnecessary binary numbers, which are in disorder in address, that is, the running data in the cache data is not output according to the cache storage format. The test system can parse and restore the cache data, and then perform fault analysis on the CPU of the tested device based on the restored data to obtain the fault analysis results.

[0110] S204. Output the fault analysis result.

[0111] The test system can output the fault analysis results. For example, the fault analysis results may include the CPU fault type, fault cause, etc. Among them, the fault type may include hang, performance degradation, data corruption, etc. The fault cause can be used to identify the root cause of the fault, for example, it may include hardware failure, software error (such as program error, operating system error, etc.) and external interference (such as electromagnetic interference, power supply problem, etc.).

[0112] Maintenance personnel can perform fault repair on the CPU of the device under test based on the fault analysis result.

[0113] In this embodiment, when the CPU of the tested device fails, the test system can send a data reading instruction to the tested device through a preset interface of the tested device. Receive cache data sent by the tested device, the cache data including the running data of the CPU before the failure. Perform fault analysis on the CPU of the tested device according to the cache data to obtain a fault analysis result. Then output the fault analysis result, thereby solving the problem that the cache data cannot be obtained when the CPU fails, and improving the efficiency of troubleshooting.

[0114] Next, how the test system sends a data read instruction to the device under test is described.

[0115] In one possible implementation, Figure 1 As shown, the test system may include an electronic device and a debugger. The SOC in the tested device is integrated with an MBIST unit. The test system can send a data read instruction to the tested device through the debugger. The data read instruction is also used to instruct the MBIST unit or non-application processor in the tested device to start a data read path.

[0116] Wherein, after the modulator is connected to the preset interface of the device under test, the test function of the preset interface can be started. Exemplarily, the preset interface can be the type-c interface of the device under test, in which a JTAG interface (joint test action group, joint test working group) is integrated, and when the modulator is connected to the preset interface, the JTAG interface can be triggered to work, thereby realizing communication with the MBIST unit or non-application processor in the device under test.

[0117] For example, Figure 3 The schematic diagram of the modulator of the test system of this application example accessing MBIST through the JTAG interface is as follows: Figure 3 As shown, after the MBIST in the device under test detects the data read instruction, the MBIST can access the cache and start the data read path. The data read path is as follows Figure 3 As shown by the fancy arrows in Figure 3 It can be seen that if the data reading path is opened through MBIST, the cached data can be transmitted to the electronic equipment of the test system through the debugger.

[0118] Understandably, Figure 3 In the manner shown, the test function bit of the preset interface triggers the corresponding function of the JTAG behind the JTAG interface.

[0119] In a possible implementation, the device under test further includes a non-application processor and a temporary storage memory. Figure 4 The schematic diagram of the modulator of the test system of the present application example accessing the non-application processor through the JTAG interface is as follows: Figure 4 As shown, after the MBIST in the device under test detects the data read instruction, the MBIST can access the cache and start the data read path. The data read path is as follows Figure 4 As shown by the fancy arrows in Figure 4It can be seen that if the data reading path is opened through the non-application processor, the acquired cache data can be stored in the temporary storage memory, and the electronic equipment in the test system can read the cache data in the temporary storage memory through the non-test function of the preset interface of the device under test.

[0120] It should be noted that in Figure 4 In the manner shown, the non-test function of the preset interface can be a conventional USB function, and the electronic device can be connected to the preset interface via a connection line compatible with the USB function, thereby realizing the transmission of cached data. In this case, the maintenance personnel can first disconnect the debugger from the preset interface of the device under test, so that the preset interface can be connected to the connection line compatible with the USB function, thereby realizing the direct connection of the device under test with the electronic device in the test system.

[0121] Understandably, Figure 3 and Figure 4 The corresponding cache data transmission method is transmitted through the preset interface. Figure 3 and Figure 4 The preset interface is not shown.

[0122] Next, how the test system performs fault analysis based on cache data is described.

[0123] Figure 5 A flow chart of another method for reading stored data provided in an embodiment of the present application, the method can be executed by a test system, specifically, the method can be applied to an electronic device in the test system, refer to Figure 5 , the method comprises the following steps:

[0124] S501, parsing the cache data to obtain restored cache data, where the restored cache data is ordered data in terms of address.

[0125] After the test system obtains the cache data, the cache data is out of order data in terms of address, which can be understood as a string of disordered binary numbers.

[0126] In a possible implementation, the cache data includes a plurality of byte data, that is, a plurality of byte data exist in an unordered binary number, and each byte data includes, for example, 8 binary numbers.

[0127] Since the cache data is stored in a high-speed cache memory (ie, cache) in the device under test, the storage format of the cache includes multiple sets, each set includes multiple cache lines (ways), and each cache line includes multiple bytes. For example, Figure 6 A schematic diagram of a cache storage format of an example of the present application, wherein each cache line includes multiple bytes ( Figure 6(not shown), for example 64 bytes, each byte can store 8 binary numbers.

[0128] The test system can obtain a storage file, and the storage format of the storage file is the same as the storage format of the cache memory. It can be understood that the storage file is an empty file and is used to write cache data.

[0129] The test system can obtain attribute information of multiple byte data in the cache data, and the attribute information of any byte data in the multiple byte data includes an identifier of a target group where the byte data is located, an identifier of a target cache line in the target group, and an identifier of a target byte included in the target cache line. The test system can write the multiple byte data into a storage file according to the attribute information of the multiple byte data to obtain the restored cache data.

[0130] That is to say, the test system can determine which byte in which cache line in which group the byte belongs to based on the attribute information of each byte data, and write it to the corresponding position in the storage file, thereby realizing the parsing and restoration of the cache data. The test system can parse the cache data and obtain the restored cache data, which helps the test system to correctly parse the cache data in the cache storage format, better understand the execution path and state of the CPU before the failure occurs, and improve the accuracy of fault analysis.

[0131] S502: Perform fault analysis on the CPU of the tested device according to the restored cache data to obtain a fault analysis result.

[0132] The test system can perform fault analysis on the CPU of the tested device according to the restored cache data to obtain a fault analysis result.

[0133] In this embodiment, the test system can parse the cache data to obtain the restored cache data, which is ordered data in terms of address, and perform fault analysis on the CPU of the tested device based on the restored cache data to obtain the fault analysis result. The test system performs fault analysis based on the restored cache data, which helps the test system to correctly parse the cache data in the cache storage format, and can better understand the execution path and state of the CPU before the fault occurs, thereby improving the accuracy of the fault analysis.

[0134] In one possible implementation, the cache includes multiple cache memories of different levels, such as L1 cache, L2 cache, and L3 cache. Among them, L1 cache is the cache with the fastest access speed, which is directly connected to the CPU core and is used to store the data and instructions currently being processed. The access speed of L2 cache is lower than that of L1 cache. It is used to store data and instructions that are not hit in L1 cache, and it provides a larger data storage area for L1 cache. L3 cache is a shared cache that serves all cores of the CPU in the device under test. Its capacity is larger than that of L2 cache. L3 cache is used to store data that is not hit in L2 cache. The CPU can effectively manage and store cache memories of different levels to optimize data access speed.

[0135] The cache data acquired by the test system may include different operating data corresponding to cache memories at multiple different levels, so checking the data of cache memories at all levels can help identify the root cause of the fault.

[0136] Next, how the device under test reads cache data is described.

[0137] Figure 7 A flowchart of another method for reading stored data provided in an embodiment of the present application, which method can be executed by the device under test, is shown in FIG. Figure 7 , the method comprises the following steps:

[0138] S701. Receive a data read instruction through a preset interface, where the data read instruction is used to read the operation data of the CPU before the failure.

[0139] When the CPU of the device under test fails, the maintenance personnel can connect the test system to the preset interface of the device under test, thereby achieving connection with the device under test, so that the device under test can receive the data reading instruction sent by the test system through the preset interface.

[0140] S702: According to the data reading instruction, a data reading path is opened, where the data reading path is used to connect the cache and the preset interface.

[0141] After the device under test obtains the data read instruction, it can start the data read path according to the data read instruction. Figure 3 and Figure 4 With reference to the above embodiments, details will not be described again here.

[0142] It should be noted that after receiving the data read instruction, the device under test can open the data read path through MBIST or through a non-application processor.

[0143] S703: Read cache data from the cache through the data reading path, where the cache data includes the CPU's operating data before the failure.

[0144] The device under test can read cache data of the cache through the data reading path. For the description of the CPU operation data before the failure included in the cache data, reference can be made to the above embodiment, which will not be repeated here.

[0145] S704: Send the cached data to the test system through a preset interface.

[0146] The method of transmitting cache data from the device under test to the test system through the preset interface can be combined with Figure 3 and Figure 4 With reference to the above embodiments, details will not be described again here.

[0147] In this embodiment, when the CPU of the device under test fails, a data reading instruction sent by the test system is received through a preset interface. According to the data reading instruction, a data reading path is opened, and the data reading path is used to connect the cache and the preset interface. The cache data of the cache memory is read through the data reading path, and the cache data includes the running data of the CPU before the failure. According to the cache data, the cache data is then sent to the test system through the preset interface. This allows the test system to perform a fault analysis on the CPU of the device under test and obtain a fault analysis result, thereby solving the problem of being unable to obtain cache data when the CPU fails, and improving the efficiency of troubleshooting.

[0148] Next, how to enable the data reading path of the device under test is described.

[0149] In a possible implementation, the device under test can enable the data reading path through MBIST, which can be implemented in the following way:

[0150] Figure 8 This is a schematic diagram of the structure of a device under test as an example of the present application. The MBIST unit in the device under test includes a built-in test controller (IST controller), a core controller (BIST controller) and a built-in test trigger (IST Trigger).

[0151] Among them, the built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface; the core controller is used to access the cache, and the built-in test trigger is used to turn on or off the built-in test controller.

[0152] The device under test can control the built-in test controller to start up through the built-in test trigger according to the data reading instruction, so that the data reading path is turned on. The data reading path is cache, core controller, built-in test controller to the preset interface. The opening function of the preset interface is the test function, that is, the preset interface triggers the JTAG interface to work, and the test function is the function corresponding to the JTAG interface. The data reading path can be referred to Figure 8 Fancy arrows shown.

[0153] In a possible implementation, the built-in test controller sends a data read instruction to the core controller, and the core controller reads the cache data in the cache according to the data read instruction. That is, after the built-in test controller is turned on, the core controller can be controlled to access the cache according to the data read instruction from the preset interface (JTAG), forming a Figure 8 The solid arrows correspond to the control paths.

[0154] After receiving the data read instruction, the preset interface may transmit the data read instruction to the built-in test trigger, so that the built-in test trigger controls the built-in test controller to start, so that the data read path is turned on.

[0155] In a possible implementation, the device under test can enable a data reading path through a non-application processor, which can be implemented in the following manner:

[0156] Fig. 9 This is a schematic diagram of the structure of another device under test as an example of the present application. The composition of the MBIST unit in the device under test refers to the above embodiment and will not be repeated here.

[0157] The difference is that the built-in test trigger is connected to the preset interface through a non-application processor.

[0158] The device under test can read data through non-application processor read instructions.

[0159] Through the non-application processor, the built-in test trigger is controlled to start the built-in test controller to open the data reading path. The data reading path is the cache memory, the core controller, the built-in test controller, the temporary storage memory to the preset interface. The opening function of the preset interface is a non-test function.

[0160] In a possible implementation, the built-in test controller sends a data read instruction to the core controller, and the core controller reads the cached data in the cache according to the data read instruction. That is, after the non-application processor obtains the data read instruction, it can control the built-in test controller to start through the built-in trigger, and then control the core controller to access the cache, forming a Fig. 9The solid arrows correspond to the control paths.

[0161] After the preset interface receives the data read instruction, it can transmit the data read instruction to the non-application processor. The non-application processor controls the built-in test controller to start through the built-in test trigger, so that the data read path is turned on. Fig. 9 Fancy arrows shown.

[0162] Next, through Fig.10 The corresponding embodiments illustrate the interaction between the test system and the device under test.

[0163] Fig.10 A flowchart of another method for reading stored data provided in an embodiment of the present application is shown in FIG. Fig.10 , the method comprises the following steps:

[0164] S1001. When a CPU of a tested device fails, a test system sends a data reading instruction to the tested device through a preset interface of the tested device, where the data reading instruction is used to read the running data of the CPU before the failure.

[0165] S1002: The device under test opens a data reading path according to a data reading instruction, where the data reading path is used to connect a cache and a preset interface.

[0166] S1003: The tested device reads cache data from the cache through a data reading path, where the cache data includes CPU operation data before the failure.

[0167] S1004: The device under test sends cache data to the test system through a preset interface.

[0168] S1005: The test system performs a fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result.

[0169] S1006. The test system outputs the fault analysis result.

[0170] For the specific implementation and beneficial effects of the above steps, please refer to the above embodiments, which will not be described again here.

[0171] In the embodiment of the present application, the cache memory and the cache can be replaced with each other.

[0172] Fig.11 The structure diagram of a storage data reading device provided in an embodiment of the present application. The device 110 is applied to a test system, and the device 110 includes: a sending module 1101, a receiving module 1102, an analyzing module 1103 and an output module 1104. Among them,

[0173] The sending module 1101 is used to send a data reading instruction to the device under test through a preset interface of the device under test when a CPU of the device under test fails. The data reading instruction is used to read the running data of the CPU before the failure.

[0174] The receiving module 1102 is used to receive the cache data sent by the tested device, where the cache data includes the operation data of the CPU before the failure.

[0175] The analysis module 1103 is used to perform fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result.

[0176] The output module 1104 is used to output the fault analysis result.

[0177] In a possible implementation, the cache data is out of order data in terms of address. The analysis module 1103 is specifically used for:

[0178] The cache data is parsed to obtain restored cache data, and the restored cache data is ordered data in terms of address.

[0179] According to the restored cache data, a fault analysis is performed on the CPU of the tested device to obtain a fault analysis result.

[0180] In a possible implementation, the cache data includes multiple bytes of data; the cache data is stored in a high-speed cache memory in the device under test, and the storage format of the high-speed cache memory includes multiple groups, each group includes multiple cache lines, and each cache line includes multiple bytes. The analysis module 1103 is specifically used to:

[0181] Get a storage file, the storage format of the storage file is the same as the storage format of the cache memory.

[0182] Attribute information of a plurality of byte data is obtained, wherein the attribute information of any byte data of the plurality of byte data includes an identifier of a target group where the byte data is located, an identifier of a target cache line in the target group, and an identifier of a target byte included in the target cache line.

[0183] According to the attribute information of the plurality of byte data, the plurality of byte data are written into the storage file to obtain the restored cache data.

[0184] In a possible implementation, the test system includes an electronic device and a debugger, and the debugger is connected to a preset interface and the electronic device respectively. The sending module 1101 is specifically used for:

[0185] A data read instruction is sent to the device under test through the debugger. The data read instruction is also used to instruct a memory built-in self-test MBIST unit or a non-application processor in the device under test to start a data read path.

[0186] In a possible implementation, the cache memory includes a plurality of cache memories at different levels; the plurality of cache memories at different levels are respectively used to store different operating data of the CPU.

[0187] The cache data includes different operating data corresponding to cache memories of different levels.

[0188] The device of this embodiment can be used to execute the technical solution corresponding to the test system in the above embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0189] Fig.12 A schematic diagram of a data storage reading device provided in an embodiment of the present application. The device 120 is applied to a device under test, and the device under test includes a SOC, in which a central processing unit CPU and a high-speed cache memory are integrated, and the high-speed cache memory is used to store the operation data of the CPU during operation. The device 120 includes: a receiving module 1201, a processing module 1202, a reading module 1203 and a sending module 1204. Among them,

[0190] The receiving module 1201 is used to receive a data reading instruction through a preset interface, where the data reading instruction is used to read the operation data of the CPU before the failure.

[0191] The processing module 1202 is used to open a data reading path according to the data reading instruction, where the data reading path is used to connect the cache memory and the preset interface.

[0192] The reading module 1203 is used to read the cache data of the cache memory through the data reading path, and the cache data includes the operation data of the CPU before the failure.

[0193] The sending module 1204 is used to send the cache data to the test system through a preset interface.

[0194] In a possible implementation, the SOC is further integrated with an MBIST unit, which includes a built-in test controller, a core controller, and a built-in test trigger.

[0195] Among them, the built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface; the core controller is used to access the cache memory, and the built-in test trigger is used to turn on or off the built-in test controller.

[0196] The processing module 1202 is specifically used for:

[0197] According to the data read instruction, the built-in test controller is controlled to start through the built-in test trigger to open the data read path. The data read path is the cache memory, the core controller, the built-in test controller to the preset interface. The start function of the preset interface is the test function.

[0198] In a possible implementation, the device under test further includes a non-application processor and a temporary storage memory; the SOC further integrates an MBIST unit, and the MBIST unit includes a built-in test controller, a core controller, and a built-in test trigger.

[0199] Among them, the built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface through the non-application processor; the core controller is used to access the cache memory, and the built-in test trigger is used to turn on or off the built-in test controller.

[0200] The processing module 1202 is specifically used for:

[0201] Read data via a non-application processor Read instruction.

[0202] Through the non-application processor, the built-in test trigger is controlled to start the built-in test controller to open the data reading path. The data reading path is the cache memory, the core controller, the built-in test controller, the temporary storage memory to the preset interface. The opening function of the preset interface is a non-test function.

[0203] In a possible implementation, the reading module 1203 is specifically configured to:

[0204] Send data read instructions to the core controller through the built-in test controller.

[0205] The core controller reads the cache data in the cache memory according to the data read instruction.

[0206] In a possible implementation, the cache memory in the device under test includes a plurality of cache memories at different levels; the cache memories at different levels are respectively used to store different operating data of the CPU.

[0207] The cache data includes different operating data corresponding to cache memories of different levels.

[0208] The device of this embodiment can be used to execute the technical solution corresponding to the device under test in the above embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0209] Fig.13 A schematic diagram of the structure of a test system provided in an embodiment of the present application is shown in FIG. Fig.13As shown, the test system 130 includes an electronic device 131 , and the electronic device 131 may include: at least one processor 1301 and a memory 1302 .

[0210] The memory 1302 is used to store programs. Specifically, the programs may include program codes, and the program codes include computer-executable instructions.

[0211] The memory 1302 may include a random access memory (RAM), and may also include a non-volatile memory (Non-volatile Memory), such as at least one disk memory.

[0212] The processor 1301 is used to execute the computer-executable instructions stored in the memory 1302 to implement the method described in the aforementioned method embodiment. The processor 1301 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0213] Optionally, the electronic device 131 may further include: a communication interface 1303. In a specific implementation, if the communication interface 1303, the memory 1302 and the processor 1301 are implemented independently, the communication interface 1303, the memory 1302 and the processor 1301 may be interconnected through a bus and communicate with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc., but it does not mean that there is only one bus or one type of bus.

[0214] Optionally, in a specific implementation, if the communication interface 1303, the memory 1302 and the processor 1301 are integrated on a chip, the communication interface 1303, the memory 1302 and the processor 1301 can communicate through an internal interface.

[0215] The electronic device 131 may be a server, a personal computer (PC), or the like.

[0216] In a possible implementation, the test system 130 further includes a debugger 132 , which is connected to the electronic device 131 and is used to connect to a preset interface of the device under test.

[0217] The debugger 132 is used to send a data read instruction to the device under test and transmit cache data. The data read instruction reads the running data of the CPU of the device under test before the failure. The cache data includes the running data.

[0218] The test system 131 of this embodiment can be used to execute the technical solution corresponding to the test system in the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0219] Fig.14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig.14 As shown, the electronic device 141 may include: at least one processor 1401 and a memory 1402 .

[0220] The memory 1402 is used to store programs. Specifically, the programs may include program codes, and the program codes include computer-executable instructions.

[0221] The memory 1402 may include a random access memory (RAM), and may also include a non-volatile memory (Non-volatile Memory), such as at least one disk memory.

[0222] The processor 1401 is used to execute the computer-executable instructions stored in the memory 1402 to implement the method described in the aforementioned method embodiment. The processor 1401 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0223] Optionally, the electronic device 140 may further include: a communication interface 1403. In a specific implementation, if the communication interface 1403, the memory 1402 and the processor 1401 are implemented independently, the communication interface 1403, the memory 1402 and the processor 1401 may be interconnected through a bus and communicate with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc., but it does not mean that there is only one bus or one type of bus.

[0224] Optionally, in a specific implementation, if the communication interface 1403, the memory 1402 and the processor 1401 are integrated on a chip, the communication interface 1403, the memory 1402 and the processor 1401 can communicate through an internal interface.

[0225] The electronic device 140 may be a device under test, and the device under test may be a terminal device, etc.

[0226] In a possible implementation, the processor 1401 includes a SOC, in which a CPU, a cache memory, and an MBIST unit connected to the cache memory are integrated.

[0227] The cache memory is used to store the running data of the CPU during its running.

[0228] MBIST unit, used to read cached data in the cache memory.

[0229] The electronic device of this embodiment can be used to execute the technical solution corresponding to the device under test in the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0230] The embodiment of the present application provides a computer-readable storage medium, which may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a RAM, a disk or an optical disk, and other media that can store computer-executable instructions. Specifically, the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a computer, the technical solution shown in the above method embodiment is executed. The specific implementation method and technical effect are similar and will not be repeated here.

[0231] An embodiment of the present application provides a computer program product, including a computer program. When the computer program is executed by a computer, the technical solution shown in the above method embodiment is executed. The specific implementation method and technical effect are similar and will not be repeated here.

[0232] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0233] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

[0234] In this application, "and / or" is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0235] "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b and c, where each of a, b, c can be an element itself or a set containing one or more elements.

[0236] In this application, "at least one" means one or more. "Multiple" means two or more. The first, second, etc. descriptions that appear in the embodiments of this application are only used for illustration and distinction of the described objects. There is no order, nor does it represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not represent the difference in size, priority or importance of the two thresholds.

[0237] In this application, "exemplary", "in some embodiments", "in other embodiments", etc. are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0238] In this application, "of", "corresponding, relevant", "corresponding", and "associated" can sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, the meanings they express are consistent. In the embodiments of this application, communication and transmission can sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, the meanings they express are consistent. For example, transmission can include sending and / or receiving, which can be a noun or a verb.

Claims

1. A method for reading stored data, characterized in that: Applied to test systems, including: When a central processing unit (CPU) of the device under test fails, a data reading instruction is sent to the device under test through a preset interface of the device under test, wherein the data reading instruction is used to read the operation data of the CPU before the failure; Receiving cache data sent by the tested device, wherein the cache data includes operation data of the CPU before the failure; Performing fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result; The fault analysis result is outputted.

2. The method according to claim 1, characterized in that: The cache data is out-of-order data in terms of address; Performing a fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result includes: Parsing the cache data to obtain restored cache data, wherein the restored cache data is ordered data in terms of address; According to the restored cache data, a fault analysis is performed on the CPU of the tested device to obtain a fault analysis result.

3. The method according to claim 2, characterized in that The cache data includes a plurality of byte data; the cache data is stored in a high-speed cache memory in the device under test, and the storage format of the high-speed cache memory includes a plurality of groups, each group includes a plurality of cache lines, and each cache line includes a plurality of bytes; Parsing the cached data to obtain restored cached data includes: Acquire a storage file, wherein the storage format of the storage file is the same as the storage format of the cache memory; Acquire attribute information of the plurality of byte data, wherein the attribute information of any one byte data among the plurality of byte data includes an identifier of a target group where the byte data is located, an identifier of a target cache line in the target group, and an identifier of a target byte included in the target cache line; According to the attribute information of the multiple byte data, the multiple byte data are written into the storage file to obtain the restored cache data.

4. The method according to any one of claims 1 to 3, characterized in that: The test system comprises an electronic device and a debugger, wherein the debugger is connected to the preset interface and the electronic device respectively; Sending a data reading instruction to the device under test through a preset interface of the device under test includes: The data read instruction is sent to the device under test through the debugger, and the data read instruction is also used to instruct a memory built-in self-test MBIST unit or a non-application processor in the device under test to start a data read path.

5. The method according to any one of claims 1 to 4, characterized in that: The cache memory in the device under test includes a plurality of cache memories at different levels; the plurality of cache memories at different levels are respectively used to store different operation data of the CPU; The cache data includes different operating data corresponding to the cache memories of different levels.

6. A method for reading stored data, characterized in that: The method is applied to a device under test, wherein the device under test includes a system-on-chip (SOC), wherein a central processing unit (CPU) and a high-speed cache memory are integrated in the SOC, and wherein the high-speed cache memory is used to store operation data of the CPU during operation; the method includes: Receiving a data reading instruction through a preset interface, wherein the data reading instruction is used to read the operation data of the CPU before the failure; According to the data reading instruction, a data reading path is opened, wherein the data reading path is used to connect the cache memory and the preset interface; Reading cache data of the cache memory through the data reading path, wherein the cache data includes operation data of the CPU before the failure; The cache data is sent to the test system through the preset interface.

7. The method according to claim 6, characterized in that The SOC is also integrated with a memory built-in self-test MBIST unit, wherein the MBIST unit includes a built-in test controller, a core controller and a built-in test trigger; Wherein, the built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface; the core controller is used to access the cache memory, and the built-in test trigger is used to turn on or off the built-in test controller; According to the data reading instruction, opening a data reading path includes: According to the data read instruction, the built-in test controller is controlled to be turned on through the built-in test trigger so that the data read path is turned on. The data read path is the cache memory, the core controller, the built-in test controller to the preset interface, and the turning-on function of the preset interface is a test function.

8. The method according to claim 6, characterized in that The device under test also includes a non-application processor and a temporary storage memory; the SOC also integrates a memory built-in self-test MBIST unit, and the MBIST unit includes a built-in test controller, a core controller and a built-in test trigger; The built-in test controller is connected to the built-in test trigger, the preset interface and the core controller respectively; the built-in test trigger is connected to the preset interface through the non-application processor; the core controller is used to access the cache memory, and the built-in test trigger is used to turn on or off the built-in test controller; According to the data reading instruction, opening a data reading path includes: Reading the data read instruction by the non-application processor; Through the non-application processor, the built-in test trigger is controlled to turn on the built-in test controller so that the data reading path is turned on. The data reading path is the cache memory, the core controller, the built-in test controller, the temporary storage memory to the preset interface, and the activation function of the preset interface is a non-test function.

9. The method according to claim 7 or 8, characterized in that: Reading cache data of the cache memory through the data reading path includes: Sending the data read instruction to the core controller through the built-in test controller; The core controller reads the cache data in the cache memory according to the data read instruction.

10. The method according to any one of claims 6 to 9, characterized in that: The cache memory includes a plurality of different levels of cache memories; the plurality of different levels of cache memories are respectively used to store different operation data of the CPU; The cache data includes different operating data corresponding to the cache memories of different levels.

11. A device for reading stored data, characterized in that: Applied to test systems, including: A sending module, used for sending a data reading instruction to the tested device through a preset interface of the tested device when a central processing unit (CPU) of the tested device fails, wherein the data reading instruction is used for reading the operation data of the CPU before the failure; A receiving module, used for receiving cache data sent by the tested device, wherein the cache data includes the operation data of the CPU before the failure; An analysis module, used to perform fault analysis on the CPU of the device under test according to the cache data to obtain a fault analysis result; An output module is used to output the fault analysis result.

12. A device for reading stored data, characterized in that: Applied to a device under test, the device under test includes a system-on-chip (SOC), the SOC integrates a central processing unit (CPU) and a high-speed cache memory, and the high-speed cache memory is used to store operating data of the CPU during operation; the device includes: A receiving module, used for receiving a data reading instruction through a preset interface, wherein the data reading instruction is used for reading the operation data of the CPU before the failure; A processing module, configured to open a data reading path according to the data reading instruction, wherein the data reading path is configured to connect the cache memory and the preset interface; A reading module, used for reading cache data of the cache memory through the data reading path, wherein the cache data includes operation data of the CPU before the failure; The sending module is used to send the cache data to the test system through the preset interface.

13. A testing system, characterized in that: include: Electronic equipment; The electronic device comprises a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 5.

14. The test system according to claim 13, characterized in that: The test system further comprises a debugger, which is connected to a preset interface of the device under test and the electronic device respectively; The debugger is used to send a data read instruction to the device under test and transmit cache data, wherein the data read instruction reads the running data of the CPU of the device under test before the failure, and the cache data includes the running data.

15. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 6 to 10.

16. The electronic device according to claim 15, characterized in that: The processor comprises a system-on-chip (SOC), wherein the SOC is integrated with a central processing unit (CPU), a high-speed cache memory and a memory built-in self-test (MBIST) unit connected to the high-speed cache memory; The high-speed cache memory is used to store the operation data of the CPU when it is running; The MBIST unit is used to read the cache data in the cache memory.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method according to any one of claims 1 to 5, or any one of claims 6 to 10.

18. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 5, or the method according to any one of claims 6 to 10.

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