Hardware testing method, apparatus, device, and storage medium

Abstract

The application provides a hardware test method, device, equipment and storage medium. The method comprises the following steps: dividing a test graph into at least two sub test graphs, wherein each sub test graph comprises a×b regions, a and b are both integers equal to or greater than 2; generating a sub graph state array, wherein the sub graph state array is used for recording the test state of the regions in the sub test graph; performing the following processing on one or more sub test graphs in the at least two sub test graphs respectively to obtain a test result graph corresponding to the hardware to be tested: determining a target region from the sub test graph according to the sub graph state array; testing the hardware to be tested according to the test parameters corresponding to the target region, obtaining a test result, and updating the sub graph state array; performing filling processing on the target region of the test graph according to the test result; and initializing the sub graph state array after completing the test on each target region in the sub test graph. The method reduces the memory requirement during the test by reusing the sub graph state array.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of hardware testing, and particularly relate to a hardware testing method, device, apparatus and storage medium. BACKGROUND

[0002] Chip testing refers to a series of physical and electrical tests performed after chip manufacturing is completed to ensure that the functions and performance of the chip meet the design specifications and to identify and eliminate any potential defects or problems.

[0003] When testing the performance of a chip, a Shmoo chart can be used to display the performance of the chip under different conditions, helping engineers to quickly locate and debug problems. The Shmoo chart displays the scanning results in a two-dimensional coordinate system by scanning two key performance indicators, such as reference voltage (Vref) and timing (Timing), and intuitively shows the relationship between these two variables. By taking Vref and Timing as test variables, the chip is tested for whether it has errors or the number of errors, and all working points (Vref, Timing) are scanned to obtain a two-dimensional eye diagram on the Shmoo chart, which can be referred to as a Shmoo eye diagram.

[0004] For Shmoo eye diagram testing, a flood fill algorithm can be used to implement it, but regardless of whether a recursive or non-recursive method is used to execute the flood fill algorithm, a large amount of memory is required. SUMMARY

[0005] In view of this, embodiments of the present application provide a hardware testing method, device, apparatus and storage medium to at least solve or alleviate the above problems.

[0006] According to a first aspect of embodiments of the present application, a hardware testing method is provided, the method comprising: dividing a test chart into at least two sub-test charts, the sub-test chart comprising a×b regions, a and b are both integers equal to or greater than 2; generating a sub-chart state array, wherein the sub-chart state array is used to record the test state of the regions in the sub-test chart; for one or more of the at least two sub-test charts, the following processing is performed respectively to obtain a test result chart corresponding to the hardware to be tested: determining a target region from the sub-test chart according to the sub-chart state array; testing the hardware to be tested according to the test parameters corresponding to the target region to obtain a test result, and updating the sub-chart state array; performing filling processing in the target region of the test chart according to the test result; after completing the test of each target region in the sub-test chart, initializing the sub-chart state array.

[0007] According to a second aspect of the embodiments of the present application, a hardware testing device is provided, the device comprising: a division module configured to divide a test graph into at least two sub test graphs, the sub test graphs comprising a×b regions, a and b being integers equal to or greater than 2; a generation module configured to generate a sub graph state array, wherein the sub graph state array is configured to record test states of the regions in the sub test graphs; and a processing module configured to perform the following processing for one or more of the at least two sub test graphs respectively, to obtain a test result graph corresponding to a hardware to be tested: determining a target region from the sub test graph according to the sub graph state array; testing the hardware to be tested according to a test parameter corresponding to the target region, to obtain a test result, and updating the sub graph state array; performing filling processing on the target region of the test graph according to the test result; and initializing the sub graph state array after completing the testing of each target region in the sub test graph.

[0008] According to a third aspect of the embodiments of the present application, an electronic device is provided, comprising: a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface performing communication with each other through the communication bus; the memory is configured to store at least one executable instruction, the executable instruction causing the processor to perform operations corresponding to the hardware testing method provided in the first aspect.

[0009] According to a fourth aspect of the embodiments of the present application, a computer storage medium is provided, the computer storage medium storing a computer program, the program being executed by a processor to implement the hardware testing method described in the first aspect.

[0010] According to a fifth aspect of the embodiments of the present application, a computer program product is provided, comprising computer instructions, the computer instructions instructing a computing device to execute the hardware testing method described in the first aspect.

[0011] According to the hardware testing scheme provided by the embodiments of the present application, the original test graph is divided into a plurality of sub test graphs, each sub test graph comprising a×b regions, and a sub graph state array is generated to record test states of the regions in the sub test graphs. By reusing the sub graph state array, the testing of the hardware to be tested is performed for each of one or a part of the plurality of sub test graphs. Compared with recording test states of the entire test graph, the memory required for recording test states of the sub test graphs is significantly reduced, and the memory requirement during hardware testing is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0013] Figure 1 is a schematic diagram of an exemplary system to which an embodiment of the present application is applied;

[0014] Figure 2 is a flowchart of a hardware testing method of an embodiment of the present application;

[0015] Figure 3 is a flowchart of a hardware testing method of an embodiment of the present application;

[0016] Figure 4 is a schematic diagram of subprogram 1 of an embodiment of the present application;

[0017] Figure 5 is a schematic diagram of subprogram 2 of an embodiment of the present application;

[0018] Figure 6 is a schematic diagram of updating of a state array of an embodiment of the present application;

[0019] Figure 7 is a schematic diagram of respective subtests running tests of an embodiment of the present application;

[0020] Figure 8 is a schematic diagram of a hardware testing device of an embodiment of the present application;

[0021] Figure 9 is a schematic diagram of an electronic device of an embodiment of the present application. DETAILED DESCRIPTION

[0022] The present application will be described below based on the embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can also be fully understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, the well-known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms appearing in the description of the embodiments of the present application are applicable to the following explanations.

[0024] The Shmoo eye diagram is a two-dimensional chart used to show the performance of a chip under different conditions. The working principle is to scan two key performance indicators through an automatic test equipment (ATE), an automated test system (ATS), or a traditional test platform, and display the test results in a two-dimensional coordinate system. The test results will show the shape of an "eye". This chart can intuitively show the working conditions of the chip under different conditions.

[0025] Taking Vref and Timing as examples of key performance indicators, given a working point (Vref, Timing), the transmit (Tx) side of the input / output (I / O) channel transmits a known pattern, and the receive (Rx) side receives and compares the pattern. Scan all working points (Vref, Timing), record whether there is an error or the number of errors at each (Vref, Timing), and draw a two-dimensional eye diagram corresponding to the test results of whether there is an error or the number of errors. Obtain the Shmoo eye diagram. The Shmoo eye diagram can be used as an important basis for evaluating I / O electrical performance and can also be used as basic data for signal integrity signoff.

[0026] Exemplary system

[0027] Figure 1 An exemplary system suitable for the hardware test method of the embodiments of the present application is shown. As shown in Figure 1 , the system includes a basic input output system (BIOS), a first chip, and a second chip.

[0028] The physical layer 110 of the first chip includes a built-in self test (BIST) unit 11, an input / output (I / O) unit 12, a comparing unit 13, and a result storing unit 14. The built-in self test unit 11 includes a parameter sweep control unit and a pattern generating unit. The parameter sweep control unit can set the scan range of multiple test parameters, for example, the scan range of each test parameter can include a scan starting point, a scan ending point, and a scan offset point. The pattern generating unit can generate a test pattern according to the test needs.

[0029] The physical layer 120 of the second chip includes an input / output unit 21. A transmission connection is established between the input / output unit 12 of the first chip and the input / output unit 21 of the second chip. The first chip transmits a test signal to the second chip according to the test pattern generated by the pattern generator through the transmission connection between the input / output unit 12 and the input / output unit 21; the second chip receives and stores the test signal; the first chip reads the stored test signal from the memory of the second chip again through the input / output unit 12 and the input / output unit 21 to obtain a feedback signal of the second chip; the input / output unit 12 sends the read feedback signal to the comparator 13, and the comparator 13 compares the test signal and the feedback signal to generate a test result, which is sent to the result register 14 for storage.

[0030] In other embodiments, the physical layer 120 of the second chip includes a comparator 22. After receiving the test signal, the second chip can also input the test signal to the comparator 22 through the input / output unit 21; the comparator 22 judges whether the received test signal is consistent with the expected one, generates a test result, and sends the test result to the result register 14 for storage.

[0031] In other embodiments, the physical layer 120 of the second chip can also include a result register 23, and the comparator 22 judges whether the received test signal is consistent with the expected one, and outputs the result to the result register 23.

[0032] In other embodiments, the physical layer 120 of the second chip can also include a built-in self-test unit 24, which includes a parameter scan controller and a pattern generator. The control signal sent by the basic input / output system can be sent to the second chip by the first chip, and the built-in self-test unit 24 of the second chip is used to perform parameter scanning and test pattern generation; then, a test signal is transmitted to the first chip according to the test pattern; after the input / output unit 12 of the first chip receives the test signal, it is input to the comparator 13, which judges whether the received test signal is consistent with the expected one, generates a test result, and sends the test result to the result register 14 for storage.

[0033] It should be noted that the built-in self-test unit can be arranged in the physical layer of the chip or in the controller of the chip, and in this embodiment, the built-in self-test unit is arranged in the physical layer of the chip.

[0034] The test algorithm provided by the embodiment of the application is used to implement the hardware test method provided by the embodiment of the application, wherein the hardware to be tested is the physical layer of the first chip or the second chip. The test algorithm can run in the BIOS, or in the internal part of the chip controller, or in the internal part of the physical layer, or in the internal part of the BIST, or in the processor (Processor), and then test the hardware to be tested.

[0035] Hardware testing method

[0036] Based on the above system, the embodiment of the application provides a hardware test method, which can be executed by the ATS in the above system embodiment. The hardware test method is described in detail through multiple embodiments.

[0037] Figure 2 is a flowchart of the hardware test method of one embodiment of the application. As shown in Figure 2 , the hardware test method comprises the following steps:

[0038] Step 210, dividing the test graph into at least two sub-test graphs.

[0039] Among them, the sub-test graph includes a×b regions, and a and b are both integers equal to or greater than 2.

[0040] The total size of the test graph and the partition size for dividing the sub-test graph are set in the computer in advance, such as the partition size of a rows and b columns; the test graph is divided into at least two sub-test graphs according to the partition size, so that each sub-test graph includes a×b regions. If the total size of the test graph is (a×m)×(b×n), then m×n sub-test graphs are obtained by dividing the test graph, wherein m and n are both integers greater than 1. For example, the total size of the test graph set in the computer in advance is 128×64, and the partition size is 32×32. According to the partition size, the test graph can be divided into 4×2 sub-test graphs, each of which includes 32×32 regions.

[0041] The total size of the test graph is set according to the number of combinations of two test variables, such as taking different values of two test variables to get (c×m)×(d×n) combinations, that is, (c×m)×(d×n) test working points, and the total size of the test graph is set as (a×m)×(b×n), wherein c and d are both integers greater than 2, a is c times e, b is d times f, and e and f are positive integers.

[0042] The above-mentioned region refers to a pixel region, and each pixel region can be composed of e×f pixel points.

[0043] Step 220, generating a sub-graph state array.

[0044] The subgraph state array is used to record the test states of the regions in the subtest graph. The subgraph state array includes two arrays, a first array and a second array. The first array is used to record the tested states of the regions in the subtest graph, and the second array is used to record the untested states of the regions in the subtest graph. Optionally, the subgraph state array can be in the form of a matrix, such as a Boolean matrix.

[0045] The computer can generate the subgraph state array according to the size of the subtest graph, or according to the number of regions included in the subtest graph. Optionally, each array in the subgraph state array contains the same number of elements as the number of regions included in the subtest graph, and each element indicates the test state of a region. For example, if the subtest graph includes a x b regions, the subgraph state array includes 2 x a x b elements. If the subgraph state array is a Boolean matrix, the size of the Boolean matrix corresponding to each array is also the same as the size of the subtest graph, and the size of both is a x b. Alternatively, each array contains a number of elements greater than the number of regions included in the subtest graph and less than twice the number of regions included in the subtest graph. For example, if the subtest graph includes a x b regions, the subgraph state array includes 2 x (a+1) x (b+1) elements.

[0046] In step 230, the following processes are performed for one or more of the at least two subtest graphs to obtain a test result graph corresponding to the hardware to be tested: determining a target region from the subtest graph according to the subgraph state array; testing the hardware to be tested according to the test parameters corresponding to the target region, obtaining a test result, and updating the subgraph state array; filling the target region of the test graph according to the test result; and initializing the subgraph state array after completing the testing of each target region in the subtest graph.

[0047] The computer performs the following processes for each of the one or more subtest graphs:

[0048] According to the test state marked by the subgraph state array, a target region with an untested state is determined from the subtest graph; the hardware to be tested is tested according to the test parameters corresponding to the target region, a test result is obtained, and the subgraph state array is updated; and the target region of the test graph is filled according to the test result;

[0049] If it is determined that the subgraph state array still includes untested state information, the step of determining the target region is returned, and the testing of the hardware to be tested in the subtest graph is continued;

[0050] If it is determined that the subgraph state array does not include the state information to be tested, the subgraph state array is initialized, and the next sub-test graph is determined, and the above processing is performed for the next sub-test graph until the hardware test for one or more sub-test graphs is completed.

[0051] In the test process, the target region determined each time can be one or more. If there are multiple target regions, the following processing can be performed on each target region in turn: testing the hardware to be tested according to the test parameters corresponding to the target region, obtaining the test result, and updating the subgraph state array; and filling the target region in the test graph according to the test result.

[0052] The test result obtained includes the number of error codes. After testing the hardware to be tested according to the test parameters corresponding to the target region, the test state of the target region in the subgraph state array is updated to be tested, and if the number of error codes indicated by the test result is within the value range, the test state of the untested region adjacent to the target region is also marked as to be tested, and the update of the subgraph state array is completed.

[0053] Regarding the update of the test state of the target region, the value in the first array representing the test state of the target region is updated from the first value to the second value, and the value in the second array representing the test state of the target region is updated from the third value to the fourth value, which indicates that the target region is updated to be tested. Regarding the update of the test state of the untested region adjacent to the target region, the value in the second array representing the test state of the untested region is updated from the fourth value to the third value, where the untested region is the untested region adjacent to the target region in the test graph. For example, the first array and the second array are both Boolean matrices, if the test state of a region is tested, the value representing the test state of the region in the first array is 1, and the value representing the test state of the region in the second array is 0; if the test state of a region is to be tested, the value representing the test state of the region in the first array is 0, and the value representing the test state of the region in the second array is 1; if the test state of a region is untested, the value representing the test state of the region in the first array is 0, and the value representing the test state of the region in the second array is 0, where the test state of the untested region is a test state other than tested and to be tested. After testing, the test state of the target region is updated, the value representing the test state of the target region in the first array is updated from 0 to 1, and the value representing the test state of the target region in the second array is updated from 1 to 0; the test state of the to-be-tested region is updated, the value representing the test state of the to-be-tested region in the second array is updated from 0 to 1, and the value representing the test state of the to-be-tested region in the first array remains unchanged, still being 0.

[0054] In the second array, the value of the test state is the fourth value, which indicates that there is no region to be tested in the sub-test graph, and the test for the sub-test graph is ended. The next sub-test graph is determined, and the test for the next sub-test graph is continued.

[0055] In the second array, the value of the test state is the fourth value, which indicates that there is no region to be tested in the sub-test graph, and the test for the sub-test graph is ended. The next sub-test graph is determined, and the test for the next sub-test graph is continued.

[0056] Regarding the determination of the region to be tested, the test result needs to be executed. In the computer, the value range is set in advance. If the error code number indicated by the test result is within the value range, the test state of the untested region adjacent to the target region is marked as to be tested. If the error code number indicated by the test result is outside the value range, the state update of the region to be tested is not performed. Alternatively, the value range is (0, 255), that is, greater than 0 and less than 255. If the error code number indicated by the test result is within (0, 255), the test state of the untested region adjacent to the target region is marked as to be tested. If the error code number indicated by the test result is 0 or 255, the state update of the region to be tested is not performed.

[0057] Alternatively, the test result graph is an eye diagram. For example, the test graph is a Shmoo eye diagram. In a possible implementation, the test result is filled in the target region of the test graph, and the filling process can be numerical filling or color filling. If numerical filling is used, the error code number indicated by the test result is filled into the target region of the test graph. If color filling is used, if the error code number indicated by the test result is within the value range, the color corresponding to the value range is filled into the target region of the test graph; wherein the value range includes at least three, and different value ranges correspond to different filling colors. For example, if the error code number is within (0, 255), the target region is filled with yellow; if the error code number is 0, the target region is filled with green; and if the error code number is 255, the target region is filled with red.

[0058] Wherein, "a plurality of" refers to two or more.

[0059] In summary, the hardware testing method provided by the embodiments of the present application divides the original test graph into a plurality of sub-test graphs, each of which includes a x b regions, and generates a sub-graph state array to record the test state of the regions in the sub-test graph. By multiplexing the sub-graph state array, the test processing of the hardware to be tested is performed for each of one or a part of the plurality of sub-test graphs. Compared with recording the test state of the entire test graph, the memory required for recording the test state of the sub-test graph is significantly reduced, greatly reducing the memory requirement during hardware testing.

[0060] In a possible implementation, the computer generates the sub-test graph state array based on the test graph. Figure 2 As shown in the embodiments, the edge state array is also used to record the test state of the edge regions in the plurality of sub-test graphs. After the test of one sub-test graph is completed, the next sub-test graph to be tested is determined based on the edge state array. The edge state array is described below in three parts.

[0061] Generation of the edge state array

[0062] The computer also generates an edge state array, which is used to record the test state of the edge regions in the at least two sub-test graphs. The edge state array includes two arrays, i.e., a third array and a fourth array. The third array is used to record the tested state of the edge regions in the at least two sub-test graphs, and the fourth array is used to record the to-be-tested state of the edge regions in the at least two sub-test graphs. Optionally, the edge state array can be in the form of a matrix, for example, a Boolean matrix.

[0063] The computer can generate the edge state array according to the size of the sub-test graph, or according to the number of edge regions included in the sub-test graph. Optionally, the number of elements contained in each array of the edge state array is the same as the total number of edge regions in the at least two sub-test graphs. For example, if the sub-test graph includes a x b regions, the sub-test graph corresponds to the use of (2a+2b-4) x 2 elements in the edge state array. If the sub-test graph includes m x n, the edge state array includes (2a+2b-4) x 2 x m x n elements. Alternatively, the number of elements used in each array by each sub-test graph is 4 more than the number of edge regions in the sub-test graph. For example, if the sub-test graph includes a x b regions, the sub-test graph corresponds to the use of (2a+2b) x 2 elements in the edge state array. If the sub-test graph includes m x n, the edge state array includes (2a+2b) x 2 x m x n elements.

[0064] Optionally, the above edge state array can be in the form of a matrix, for example, the edge state array can be a Boolean matrix. For example, each array in the edge state array can be a Boolean matrix with a size of m x n x (2a+2b).

[0065] The edge state array can be used to record the test state of the edge region of all sub-test patterns. In the embodiments provided in the present application, the edge state array is used to record the test state of the edge region of one or part of the sub-test patterns.

[0066] The sub-pattern state array and the edge state array can be generated in sequence or simultaneously, and the generation sequence of the two is not limited.

[0067] · Update of the edge state array

[0068] After the target region is tested according to the test parameter corresponding to the target region, it is determined that the target region is located at the edge of the sub-test pattern, and the test state of the target region in the edge state array is updated to be measured.

[0069] That is, in the update process of the test state, it is also necessary to determine whether the target region is located at the edge of the sub-test pattern, and if the target region is located at the edge of the sub-test pattern, the test state of the target region in the edge state array is updated. If the target region does not belong to the edge of the sub-test pattern, the test state of the target region in the edge state array is not updated.

[0070] In the update of the edge state array, if the test state of the target region is updated to be measured, the value representing the test state of the target region in the third array is updated from the fifth value to the sixth value, and the value representing the test state of the target region in the fourth array is updated from the seventh value to the eighth value.

[0071] Regarding the update of the test state of the edge region, if the test state of an edge region is measured, the value representing the test state of the edge region in the third array is 1, and the value representing the test state of the edge region in the fourth array is 0; if the test state of an edge region is to be measured, the value representing the test state of the edge region in the third array is 0, and the value representing the test state of the edge region in the fourth array is 1; if the test state of an edge region is not measured, the value representing the test state of the edge region in the third array is 0, and the value representing the test state of the edge region in the fourth array is 0.

[0072] After the test, the test state of the target region is updated, and if the target region is an edge region of the sub-test pattern, the value representing the test state of the target region in the third array is updated from 0 to 1, and the value representing the test state of the target region in the fourth array is updated from 1 to 0.

[0073] Optionally, the computer further updates the test state of the to-be-tested region in the edge state array after determining that the to-be-tested region is located at the edge of any sub-test figure, i.e., if the to-be-tested region is located at the edge of any sub-test figure in at least two sub-test figures, the test state of the to-be-tested region in the edge state array is marked as to-be-tested, wherein the to-be-tested region is an untested region adjacent to the target region in the test figure.

[0074] The to-be-tested region can be located at the edge of the sub-test figure under test, or can also be located at the edge of another sub-test figure adjacent to the sub-test figure. If the to-be-tested region is located at the edge of the sub-test figure under test, the test state of the to-be-tested region in the sub-figure state array and the edge state array needs to be updated to to-be-tested; if the to-be-tested region is located at the edge of another sub-test figure adjacent to the sub-test figure, the test state of the to-be-tested region in the edge state array needs to be updated to to-be-tested. If the to-be-tested region does not belong to the edge of any sub-test figure, the test state update of the to-be-tested region in the edge state array is not performed.

[0075] If the test state of the to-be-tested region is updated to to-be-tested, the value representing the test state of the to-be-tested region in the fourth array is updated from the eighth value to the seventh value, such as updating the value representing the test state of the edge region in the fourth array from 0 to 1.

[0076] If there is an update of the edge state array, it can be performed simultaneously or sequentially with the update of the sub-figure state array, and the execution order of the two is not limited.

[0077] • determining the sub-test figure for the next test based on the edge state array

[0078] After completing the test on each target region in the sub-test figure, the sub-test figure for the next test is determined according to the edge region with a to-be-tested test state in the edge state array; the test state of the edge region of the sub-test figure for the next test is updated from the edge state array to the initialized sub-figure state array, and the test on each target region in the sub-test figure for the next test is performed.

[0079] For example, in the case where the seventh value exists in the fourth array, the sub-test figure in which the region with the seventh value of the test state is located is determined as the sub-test figure for the next test; the value of the test state of the edge region of the sub-test figure for the next test is copied from the fourth array to the initialized second array.

[0080] If the subgraph state array indicates that there is no region to be tested in the sub-test graph, the testing of each target region in the sub-test graph is completed, and then the sub-test graph with the edge region to be tested is determined as the next testing sub-test graph according to the edge state array, the testing state of the edge region of the next testing sub-test graph is updated from the edge state array to the corresponding position in the initialized subgraph state array, and then the step 330 is returned to execute, and the next testing sub-test graph is determined again based on the edge state array, until the edge state array indicates that there is no sub-test graph to be tested, and the hardware testing corresponding to one or more sub-test graphs is completed.

[0081] In summary, the hardware testing method provided by the embodiment of the present application divides the original test graph into a plurality of sub-test graphs, each of which includes a×b regions, and generates a subgraph state array to record the testing state of the regions in the sub-test graph. After the testing of one sub-test graph is completed, the subgraph state array is initialized, and the initialized subgraph state array is used to continue participating in the testing of the next sub-test graph. Through the reuse of the subgraph state array, the testing of one or more sub-test graphs is completed. Compared with recording the testing state of the entire test graph, the memory required for recording the testing state of the sub-test graph is significantly reduced. Therefore, the generation and reuse of the subgraph state array can greatly reduce the memory requirement during the hardware testing.

[0082] In the method, an edge state array is also generated to record the testing state of the edge regions of the plurality of sub-test graphs. In the process of selecting the region to be tested, the region to be tested may be selected in the edge region of another sub-test graph adjacent to the sub-test graph. The testing state of the region to be tested is updated in the edge state array. After the testing of the sub-test graph is completed, the next testing sub-test graph can be accurately positioned through the testing state existing in the edge state array. The sub-test graph without the target region does not need to be tested, thereby reducing the workload of the hardware testing and improving the rate of the hardware testing.

[0083] Figure 3 is a flowchart of the hardware testing method of one embodiment of the present application. As shown in Figure 3 , one of the hardware testing methods provided by the above-mentioned embodiments is exemplarily described, and the steps are as follows:

[0084] Step 301, start.

[0085] Step 302, partition size: (a×b); total size of the test graph: (a×m)×(b×n); number of sub-test graphs: (m×n).

[0086] The preset partition size is (a x b) and the total size of the test graph is (a x m) x (b x n), and the computer divides the test graph with the total size of (a x m) x (b x n) into (m x n) sub test graphs according to the partition size (a x b). The partition size refers to the size for dividing the sub test graphs.

[0087] Wherein, (a x b) represents a row x b column; (m x n) represents m row x n column; (a x m) x (b x n) represents (a x m) row x (b x n) column.

[0088] Step 303, initialize the following Boolean arrays to be all false: visited; to_visit; edge_visited; edge_to_visit.

[0089] The numerical value 0 is used to represent false in the Boolean array, and the numerical value 1 is used to represent true. The following Boolean arrays are generated and initialized: visited; to_visit; edge_visited; edge_to_visit; wherein, visited refers to the first array; to_visit refers to the second array; edge_visited refers to the third array; edge_to_visit refers to the fourth array.

[0090] The Boolean array is generated according to the size of the sub test graph, and visited and to_visit are Boolean matrices with the size of (a x b), and edge_visited and edge_to_visit are Boolean matrices with the size of m x n x (2a+2b).

[0091] Step 304, get the center point (V0, T0) of the test graph through I / O training.

[0092] The computer determines the center point (V0, T0) from the test graph through the way of input / output (Input / Output, I / O) training (Training).

[0093] In this embodiment, test variables Vref and Timing are taken as examples. One area in the test graph is represented by one cell, and in the test graph set according to the test variables, each cell corresponds to a working point, and a working point corresponds to a set of test parameters (Vref, Timing). The center point refers to the working point located at the center position of the test graph.

[0094] Step 305, start from (V0, T0) and move in one direction, and run a test for each test parameter corresponding to each cell every time the cell is moved, until the test result is within the range of interest, and the last test working point (V, T) is taken as the initial working point.

[0095] The range of interest is the value range. Starting from (V0, T0), move in one direction, which can be any of up, down, left or right. For example, starting from (V0, T0), move down. For each step down, run a test for the corresponding test parameter until the test result is within (0, 255). Take the last test working point (V, T) as the initial working point.

[0096] Step 306, calculate the sub-test graph where the initial working point is located.

[0097] The test graph is divided into m rows x n columns of sub-test graphs. Determine the position (ri, rj) of the initial working point in the above m x n sub-test graph array. Use the floor function to calculate (ri, rj):

[0098] ri = floor(V / a);

[0099] rj = floor(T / b);

[0100] Where i and j are positive integers.

[0101] Step 307, set visited to all False; set to_visit to all False.

[0102] Before starting the test of each sub-test graph, initialize visited and to_visit, and set both visited and to_visit to all False.

[0103] Step 308, copy 2(a+b) values in edge_to_visit[ri, rj] to the upper and lower edges of to_visit.

[0104] Where edge_to_visit[ri, rj] represents the address of edge_to_visit recording the test state of the edge area of sub-test graph (ri, rj). The relationship of copying 2(a+b) values from edge_to_visit[ri, rj] to to_visit is as follows:

[0105] Upper edge: to_visit[0, :] = edge_to_visit[ri, rj, 2a:2a+b];

[0106] Lower edge: to_visit[a-1, :] = edge_to_visit[ri, rj, 2a+b:2a+2b];

[0107] Left edge: to_visit[:,0] = edge_to_visit[ri,rj,:a];

[0108] Right edge: to_visit[:,b-1] = edge_to_visit[ri,rj,a:2a];

[0109] where to_visit is a 2-dimensional boolean matrix of a x b, to_visit[0,:] represents the b positions of the upper edge with starting position 0 in to_visit, to_visit[a-1,:] represents the b positions of the lower edge with starting position (a-1) in to_visit, to_visit[:,0] represents the a positions of the left edge with ending position 0 in to_visit, to_visit[:,b-1] represents the a positions of the right edge with ending position (b-1) in to_visit; edge_to_visit is a 3-dimensional boolean matrix of m x n x 2(a+b), edge_to_visit[ri,rj,:a] represents the positions 0 to (a-1) of the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit, edge_to_visit[ri,rj,a:2a] represents the positions a to (2a-1) of the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit, edge_to_visit[ri,rj,2a:2a+b] represents the positions (2a-1) to (2a+b-1) of the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit, edge_to_visit[ri,rj,2a+b:2a+2b] represents the positions (2a+b) to (2a+2b-1) of the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit.

[0110] Step 309, calculate the position (ci,cj) of the working point (V,T) in the sub-test graph.

[0111] The sub-test graph is a x b, determine the position (ci,cj) of the working point (V,T) in the above a x b sub-test graph.

[0112] The remainder (mod) function is used to calculate (ci,cj):

[0113] ci = V mod a;

[0114] cj = T mod b.

[0115] Step 310, configure the I / O working point as (V,T), run the test and record the results.

[0116] The computer configures the test parameters of the I / O operation as V and T, runs the test, and records the results of the test on the hardware to be tested, such as the number of error codes.

[0117] Step 311, update visited and to_visit.

[0118] Update the values at the position (ci, cj) in to_visit and visited:

[0119] to_visit[ci,cj] = False;

[0120] visited[ci,cj] = True.

[0121] Step 312, execute Subroutine 1: update edge_to_visit[ci,cj] and edge_visited[ci,cj].

[0122] Execute Subroutine 1 to determine the position of the working point (V, T) in the sub-test graph. If the working point (V, T) is located on the edge of the sub-test graph, update edge_to_visit and edge_visited. As Figure 4 shown, the update process of Subroutine 1 is as follows:

[0123] Judge the value of ci;

[0124] If ci = 0, it means that the working point (V, T) is at the upper edge of the sub-test graph, and update edge_to_visit and edge_visited:

[0125] edge_to_visit[ri,rj,2a+cj] = False; edge_visited[ri,rj,2a+cj] = Ture;

[0126] If ci = a - 1, it means that the working point (V, T) is at the lower edge of the sub-test graph, and update edge_to_visit and edge_visited:

[0127] edge_to_visit[ri,rj,2a+b+cj] = False; edge_visited[ri,rj,该文本中“Ture”应改为“True”,修改后的翻译为:edge_visited[ri,rj,2a+b+cj] = True;

[0128] If 0 < ci < a - 1, then judge the value of cj;

[0129] If cj = 0, it indicates the left edge of the sub-test graph at the working point (V, T), and update edge_to_visit and edge_visited:

[0130] edge_to_visit[ri, rj, ci] = False; edge_visited[ri, rj, ci] = True;

[0131] If cj = b - 1, it indicates the right edge of the sub-test graph at the working point (V, T), and update edge_to_visit and edge_visited:

[0132] edge_to_visit[ri, rj, a + ci] = False; edge_visited[ri, rj, a + ci] = True;

[0133] If 0 < cj < b - 1, it indicates that the working point (V, T) is not located at the edge of the sub-test graph.

[0134] Step 313, determine whether the test result is within the range of interest.

[0135] If the test result is within the range of interest, execute Step 314; if not, that is, the test result is not within the range of interest, execute Step 315. For example, determine whether the number of error codes is within (0, 255). If so, execute Step 314; if not, execute Step 315.

[0136]

[0137] Execute Subroutine 2 to determine whether there are still untested areas in the upper, lower, left, and right regions adjacent to (ci, cj). If there are still untested areas, mark them as to be tested. As Figure 5 shown, the update process of Subroutine 2 is as follows:

[0138] · Judge the value of ci.

[0139] 1) If ci = 0, it indicates that the working point (V, T) is located at the upper edge of the sub-test graph. Mark the area (ci + 1, cj) below (ci, cj) as to be tested, that is, update to_visit:

[0140] ​to_visit[ci+1,cj] = ~visited[ci+1,cj], wherein, "~" represents a NOT operation, for example, visited[ci+1,cj] = False, then ~visited[ci+1,cj] = True, then after updating, to_visit[ci+1,cj] = True, otherwise, visited[ci+1,cj] = True, then ~visited[ci+1,cj] = False, then after updating, to_visit[ci+1,cj] = False;

[0141] After updating to_visit, it is judged whether ri>0;

[0142] If ri>0, it indicates that there is a sub-test graph (ri-1, rj) above the sub-test graph (ri, rj) in the sub-test graph array, and the test state of the region adjacent to (ci, cj) and located above (ci, cj) in the sub-test graph (ri-1, rj) is updated in edge_to_visit:

[0143] edge_to_visit[ri-1,rj,k] = ~edge_visited[ri-1,rj,k], k = 2a+b+cj;

[0144] If ri>0, it indicates that the sub-test graph (ri, rj) is located at the upper edge of the sub-test graph array, and the step of "judging the value of cj" is executed.

[0145] 2) If ci=a-1, it indicates that the working point (V, T) is located at the lower edge of the sub-test graph, and the region (ci-1, cj) above (ci, cj) is marked as to be tested, that is, to_visit is updated as:

[0146] to_visit[ci-1,cj] = ~visited[ci-1,cj];

[0147] After updating to_visit, it is judged whether ri<m-1;

[0148] If ri<m-1, it indicates that there is a sub-test graph (ri+1, rj) below the sub-test graph (ri, rj) in the sub-test graph array, and the test state of the region adjacent to (ci, cj) and located below (ci, cj) in the sub-test graph (ri+1, rj) is updated in edge_to_visit:

[0149] edge_to_visit[ri+1,rj,k] = ~edge_visited[ri+1,rj,k], k = 2a+cj;

[0150] If not ri < m - 1, it means that the sub-test graph (ri, rj) is located at the lower edge in the sub-test graph array, the step of "judging the value of cj" is executed.

[0151] 3) If 0 < ci < a - 1, it means that the working point (V, T) is not located at the upper and lower edge positions of the sub-test graph, the region (ci - 1, cj) above (ci, cj) and the region (ci + 1, cj) below (ci, cj) are marked as to be tested, that is, to_visit is updated as follows:

[0152] to_visit[ci - 1, cj] = ~visited[ci - 1, cj]; to_visit[ci + 1, cj] = ~visited[ci + 1, cj];

[0153] After updating to_visit, the step of "judging the value of cj" is executed.

[0154] The value of cj is judged.

[0155] 1) If cj = 0, it means that the working point (V, T) is located at the left edge of the sub-test graph, the region (ci, cj + 1) to the right of (ci, cj) is marked as to be tested, that is, to_visit is updated as follows:

[0156] to_visit[ci, cj + 1] = ~visited[ci, cj + 1];

[0157] After updating to_visit, it is judged whether rj > 0;

[0158] If rj > 0, it means that there is a sub-test graph (ri, rj - 1) to the left of the sub-test graph (ri, rj) in the sub-test graph array, the test state of the region adjacent to (ci, cj) and located to the left of (ci, cj) in the sub-test graph (ri, rj - 1) is updated in edge_to_visit as follows:

[0159] edge_to_visit[ri, rj - 1, k] = ~edge_visited[ri, rj - 1, k], k = a + ci;

[0160] If not ri > 0, it means that the sub-test graph (ri, rj) is located at the left edge in the sub-test graph array, step 315 is executed.

[0161] 2) If cj = b - 1, it means that the working point (V, T) is located at the right edge of the sub-test graph, the region (ci, cj - 1) to the left of (ci, cj) is marked as to be tested, that is, to_visit is updated as follows:

[0162] to_visit[ci,cj-1] = ~visited[ci,cj-1];

[0163] Update to_visit and determine whether rj < n-1.

[0164] If rj < n-1, it means that there is a sub-test pattern (ri, rj+1) to the right of the sub-test pattern (ri, rj) in the sub-test pattern array. Update the test state of the regions adjacent to (ci, cj) and located to the right of (ci, cj) in the sub-test pattern (ri, rj+1) in edge_to_visit as follows:

[0165] edge_to_visit[ri,rj+1,k] = ~edge_visited[ri,rj+1,k], k = ci;

[0166] If ri < n-1, it means that the sub-test pattern (ri, rj) is located at the right edge of the sub-test pattern array. Perform step 315.

[0167] 3) If 0 < cj < b-1, it means that the operating point (V, T) is not located at the left or right edge of the sub-test pattern. Mark the regions to the left (ci, cj-1) and right (ci, cj+1) of (ci, cj) as to-be-tested, i.e., update to_visit as follows:

[0168] to_visit[ci,cj-1] = ~visited[ci,cj-1]; to_visit[ci,cj+1] = ~visited[ci,cj+1];

[0169] After updating to_visit, perform step 315.

[0170] Step 315: Determine whether to_visit is all False.

[0171] After completing the test of the operating point (V, T), determine whether to_visit is all False, i.e., determine whether there are still regions to be tested in the sub-test pattern. If yes, perform step 318; if no, perform step 316.

[0172] Step 316: Find a new set of (ci, cj) such that to_visit[ci,cj] = True and visited[ci,cj] = False.

[0173] Redetermine a (ci, cj) in the sub-test pattern, where to_visit[ci,cj] = True and visited[ci,cj] = False, i.e., it is a region to be tested.

[0174] Step 317, calculate the working point corresponding to the new (ci, cj).

[0175] According to the working point corresponding to the re-determined (ci, cj) in the test graph, the calculation method is as follows:

[0176] v = ri x a + ci;

[0177] t = rj x b + cj.

[0178] After step 317 is executed, return to step 310.

[0179] Step 318, judge whether edge_to_visit is all False.

[0180] Judge whether edge_to_visit is all False, that is, judge whether there is a sub-test graph to be tested. If edge_to_visit is all False, it indicates that there is no sub-test graph to be tested, and step 320 is executed. If not, that is, edge_to_visit is not all False, it indicates that there is still a sub-test graph to be tested, and step 319 is executed.

[0181] Step 319, find a new set of (ri, rj) such that edge_to_visit[ri, rj] is not all False.

[0182] In the sub-test graph, a sub-test graph (ri, rj) is re-determined. In this re-determined sub-test graph (ri, rj), edge_to_visit[ri, rj] is not all False, that is, it is a sub-test graph to be tested.

[0183] For example Figure 6As shown, the test run is exemplified. First, the hardware to be tested is tested for the sub-test graph (ri, rj) on the right side of the boundary line. The test is run at the working point 601, the error number (errcnt) is recorded as 64, and the state of the working point 601 is marked as the region measured, 0 < errcnt = 64 < the maximum error number (err_max), so the working points on the lower three sides of the working point 601 are marked as the region to be tested; move one step to the left, run the test at the working point 602, record the error number as 133, and mark the state of the working point 602 as the region measured, 0 < errcnt = 133 < err_max, mark the working points on the lower two sides of the working point 602 as the region to be tested; continue to move one step to the left, run the test at the working point 603, record the error number as 169, and mark the state of the working point 603 as the region measured, 0 < errcnt = 169 < err_max, the working point 603 is located at the left edge of the sub-test graph (ri, rj), mark the working points on the upper and lower sides of the working point 603 as the region to be tested, and mark the working points on the left side of the working point 603 as the edge to be tested; move one step down, run the test at the working point 604, record the error number as 194, and mark the state of the working point 604 as the region measured, 0 < errcnt = 194 < err_max, the working point 604 is located at the left edge of the sub-test graph (ri, rj), mark the working points on the lower side of the working point 604 as the region to be tested, and mark the working points on the left side of the working point 604 as the edge to be tested; …… until the measurement of the sub-test graph (ri, rj) is completed, the measurement of the next sub-test graph (ri, rj-1) is started according to the marking of the edge to be tested, the test is run at the working point 605, the error number is recorded as 209, the state of the working point 605 is marked as the region measured, 0 < errcnt = 209 < err_max, the working point 605 is located at the right edge of the sub-test graph (ri, rj-1), the working points on the upper, lower and left three sides of the working point 605 are marked as the region to be tested, …… until the measurement of the sub-test graph (ri, rj-1) is completed, the measurement of the next sub-test is started again according to the marking of the edge to be tested, and so on. As shown in FIG. 7, the measurement of the sub-test graph 701 is completed, the measurement of the sub-test graph 702 is started according to the marking of the edge to be tested, and then the measurement of the sub-test graph 703, the sub-test graph 704, the sub-test graph 705 and the sub-test graph 706 is completed in turn, until the measurement of the test graph is completed. Among them, marking the region measured and the region to be tested is marking the test state in the sub-graph state array; marking the edge to be tested is marking the test state in the edge state array. Figure 7 , after the measurement of the sub-test graph 701 is completed, the measurement of the sub-test graph 702 is started according to the marking of the edge to be tested, and then the measurement of the sub-test graph 703, the sub-test graph 704, the sub-test graph 705 and the sub-test graph 706 is completed in turn, until the measurement of the test graph is completed. Among them, marking the region measured and the region to be tested is marking the test state in the sub-graph state array; marking the edge to be tested is marking the test state in the edge state array.

[0184] Step 320, end.

[0185] The test result graph in the embodiment is an eye diagram. If an (a x m) x (b x n) eye diagram is to be generated, the sub test graphs are divided according to the size of a x b, and the memory requirements are as follows: visited requires a x b / 8 (Bytes), to_visit requires a x b / 8 (Bytes), edge_to_visit requires m x n x (2 x a + 2 x b) / 8 (Bytes), edge_visited requires m x n x (2 x a + 2 x b) / 8 (Bytes). Table 1 shows the memory requirements for testing hardware in combination of different eye diagram sizes and different partition sizes. If the eye diagram size is 128 x 128 and the partition size is 32 x 32, the total memory required for testing is 0.75 kB (kilobyte). Bytes is a byte, and 1 kB = 1024 Bytes. As shown in Table 1, if the partition size is 32 x 32, the Shmoo measurement of 128 x 128 or below can be satisfied by 1 kB of memory.

[0186] Table 1

[0187]

[0188] The hardware testing method provided in the embodiments reduces the memory requirements for hardware testing, and can solve the problem that the Basic Input / Output System (BIOS) resource is limited, the memory usage needs to be limited within 1 kB, and 34 kB of memory is required for Shmoo measurement in a recursive manner for a 128 x 128 eye diagram, and 4 kB of memory is required for Shmoo measurement in a non-recursive manner, which cannot meet the memory requirement.

[0189] Hardware testing apparatus

[0190] Corresponding to the method embodiment, Figure 8 A schematic diagram of a hardware testing device is shown. As Figure 8 shown, the hardware testing device includes:

[0191] The dividing module 801 is configured to divide a test graph into at least two sub test graphs, and each sub test graph includes a x b regions, where a and b are integers greater than 2.

[0192] The generating module 802 is configured to generate a sub graph state array, where the sub graph state array is used to record the test state of each region in the sub test graph.

[0193] The processing module 803 is configured to perform the following processing on one or more of the at least two sub-test graphs respectively, to obtain a test result graph corresponding to the hardware to be tested: determining a target region from the sub-test graph according to a subgraph state array; testing the hardware to be tested according to a test parameter corresponding to the target region, to obtain a test result, and updating the subgraph state array; performing filling processing on the target region of the test graph according to the test result; and initializing the subgraph state array after completing the testing on each target region in the sub-test graph.

[0194] In a possible implementation, the processing module 803 updates the subgraph state array, including: updating, in the subgraph state array, a test state of the target region to a tested state; and marking a test state of an untested region adjacent to the target region as a to-be-tested state, if a number of error codes indicated by the test result is within a value range, wherein the target region is determined from a region marked as the to-be-tested state in the sub-test graph.

[0195] In a possible implementation, the subgraph state array includes a first array and a second array.

[0196] The processing module 803 updates, in the subgraph state array, the test state of the target region to the tested state, including: updating a value representing the test state of the target region in the first array from a first value to a second value, and updating a value representing the test state of the target region in the second array from a third value to a fourth value.

[0197] The processing module 803 marks the test state of the untested region adjacent to the target region as the to-be-tested state, including: updating a value representing the test state of the to-be-tested region in the second array from the fourth value to the third value, wherein the to-be-tested region is an untested region adjacent to the target region in the test graph.

[0198] In a possible implementation, the processing module 803 determines the target region from the sub-test graph according to the subgraph state array, including: determining, according to the second array, a region in the sub-test graph with a value representing a test state of the region being the third value as the target region.

[0199] In a possible implementation, the generation module 802 is further configured to generate an edge state array, wherein the edge state array is used to record test states of edge regions in the at least two sub-test graphs.

[0200] The processing module 803 is further configured to, after testing the hardware to be tested according to the test parameter corresponding to the target region, determine that the target region is located at an edge of the sub-test graph, and update a test state of the target region in the edge state array to a tested state.

[0201] In a possible implementation, the edge state array includes a third array and a fourth array.

[0202] The processing module 803 updates the to-be-tested state of the target region in the edge state array to a tested state, including: updating the value representing the test state of the target region in the third array from the fifth value to a sixth value, and updating the value representing the test state of the target region in the fourth array from a seventh value to an eighth value.

[0203] In a possible implementation, the processing module 803 is further configured to mark the test state of the to-be-tested region in the edge state array as to be tested, if the to-be-tested region is located at an edge of any of the at least two sub test maps, where the to-be-tested region is an untested region adjacent to the target region in the test map.

[0204] In a possible implementation, the processing module 803 marks the test state of the to-be-tested region in the edge state array as to be tested, including: updating the value representing the test state of the to-be-tested region in the fourth array from the eighth value to the seventh value.

[0205] In a possible implementation, the processing module 803 is further configured to, after completing the test on each target region in the sub test map, determine a next test sub test map according to an edge region with a test state marked as to be tested in the edge state array, update the test state of the edge region of the next test sub test map to the initialized sub map state array from the edge state array, and perform the test on each target region in the next test sub test map.

[0206] In a possible implementation, the test result map is an eye diagram.

[0207] In a possible implementation, the processing module 803 performs a filling process on the target region of the test map according to the test result, including: filling the number of error codes indicated by the test result to the target region of the test map; or if the number of error codes indicated by the test result is located in a value range, filling a color corresponding to the value range to the target region of the test map, where the value range includes at least three, and different value ranges correspond to different filling colors.

[0208] It should be noted that the hardware test device in this embodiment is used to implement the corresponding hardware test method in the foregoing method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described herein again.

[0209] Electronic device

[0210] Figure 9 is a schematic block diagram of an electronic device provided by an embodiment of the present application, and embodiments of the present application do not limit the specific implementation of the electronic device. For example, Figure 9As shown, the electronic device can include a processor 902, a communications interface 904, a memory 906, and a communications bus 908. Among them:

[0211] The processor 902, the communications interface 904, and the memory 906 complete the communication with each other through the communications bus 908.

[0212] The communications interface 904 is configured to communicate with other electronic devices or servers.

[0213] The processor 902 is configured to execute the program 910, and specifically can execute the related steps in any of the preceding hardware test method embodiments.

[0214] Specifically, the program 910 can include program code, which includes computer operation instructions.

[0215] The processor 902 can be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement one or more embodiments of the present application. The one or more processors included in the smart device can be the same type of processor, such as one or more CPUs; or can be different types of processors, such as one or more CPUs and one or more ASICs.

[0216] RISC-V is an open-source instruction set architecture based on the principle of reduced instruction set (RISC), which can be applied to various aspects such as single-chip microcomputers and FPGA chips. Specifically, it can be applied in the fields of Internet of Things security, industrial control, mobile phones, personal computers, etc. And because it takes into account the realities of small, fast, and low power consumption when designing, it is particularly suitable for modern computing devices such as warehouse-scale computers, high-end mobile phones, and small embedded systems. With the rise of artificial intelligence Internet of Things (AIoT), the RISC-V instruction set architecture has also received more and more attention and support, and is expected to become the next generation of widely used CPU architecture.

[0217] The computer operation instructions in the embodiments of the present application can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 902 can be designed based on the RISC-V instruction set. Specifically, the chip of the processor in the electronic device provided by the embodiments of the present application can be a chip designed based on the RISC-V instruction set. The chip can execute executable code based on the configured instructions, and thus implement the hardware test method in the above embodiments.

[0218] The memory 906 stores a program 910. The memory 906 can include a high-speed RAM memory and can also include a non-volatile memory such as at least one disk memory.

[0219] The program 910 can specifically be used to cause the processor 902 to perform the hardware testing method in any of the preceding embodiments.

[0220] The specific implementation of each step in the program 910 can refer to the corresponding description in the corresponding steps and units in any of the preceding hardware testing method embodiments, and will not be described here. It can be clearly understood by those skilled in the art that, for the convenience and brevity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the preceding method embodiments, which will not be described here.

[0221] Computer storage medium

[0222] The present application also provides a computer-readable storage medium storing instructions for causing a machine to perform the hardware testing method as described herein. Specifically, a system or device equipped with a storage medium can be provided, and the storage medium stores software program code for implementing the functions of any of the above-described embodiments, and causes the computer (or CPU or MPU) of the system or device to read and execute the program code stored in the storage medium.

[0223] In this case, the program code read from the storage medium itself can implement the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present application.

[0224] The storage medium for providing the program code includes a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as a CD-ROM, a CD-R, a CD-RW, a DVD-ROM, a DVD-RAM, a DVD-RW, a DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0225] Computer program product

[0226] The embodiments of the present application also provide a computer program product including computer instructions instructing a computing device to perform any corresponding operation in the above-described method embodiments.

[0227] It should be noted that, according to the needs of implementation, each component / step described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or part of the operations of the components / steps can be combined into a new component / step, to achieve the purpose of the embodiments of the present application.

[0228] The methods according to the embodiments of the present application described above can be implemented in hardware, firmware, or software, or be implemented as software or computer code that can be stored in a recording medium such as CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or be implemented by computer code stored in a remote recording medium or non-transitory machine-readable medium originally downloaded through a network and stored in a local recording medium, so that the methods described herein can be processed by such software using a general purpose computer, a special purpose processor, or programmable or dedicated hardware such as ASIC or FPGA. It can be understood that the computer, processor, microprocessor controller, or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor, or hardware, the methods described herein are implemented. Furthermore, when a general purpose computer accesses the code for implementing the methods shown herein, the execution of the code will convert the general purpose computer into a special purpose computer for executing the methods shown herein.

[0229] Those skilled in the art can realize that the units and method steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, or in combination of computer software and electronic hardware. Whether the functions are realized in hardware or software manner depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0230] The above embodiments are only used to illustrate the present application, and not to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore all equivalent technical solutions also belong to the scope of the present application, the patent protection scope of the present application should be defined by the claims.

Claims

1. A hardware testing method, the method comprising: dividing a test graph into at least two sub-test graphs, the sub-test graphs comprising a×b regions, a and b being integers equal to or greater than 2; generating a sub-graph state array, wherein the sub-graph state array is used to record test states of regions in the sub-test graphs; respectively performing the following processes for one or more of the at least two sub-test graphs to obtain a test result graph corresponding to a hardware to be tested: determining a target region from the sub-test graph according to the sub-graph state array; testing the hardware to be tested according to test parameters corresponding to the target region, obtaining a test result, and updating the sub-graph state array; performing a filling process on the target region of the test graph according to the test result; and initializing the sub-graph state array after completing testing of each target region in the sub-test graph; wherein the updating of the sub-graph state array comprises: updating a test state of the target region to tested in the sub-graph state array; and if a number of error codes indicated by the test result is within a value range, marking a test state of an untested region adjacent to the target region as to be tested, wherein the target region is determined from regions marked as to be tested in the sub-test graph; in a case where the sub-graph state array comprises a first array and a second array, the updating of the test state of the target region in the sub-graph state array comprises: updating a value representing the test state of the target region in the first array from a first value to a second value, and updating a value representing the test state of the target region in the second array from a third value to a fourth value; and the marking of the test state of the untested region adjacent to the target region as to be tested comprises: updating a value representing the test state of the to-be-tested region in the second array from the fourth value to the third value, wherein the to-be-tested region is an untested region adjacent to the target region in the test graph.

2. The method of claim 1, wherein, the determining of the target region from the sub-test graph according to the sub-graph state array comprises: determining regions in the sub-test graph for which values of test states are the third value in the second array as the target regions, respectively.

3. The method of claim 1 or 2, wherein, the method further comprises: generating an edge state array, wherein the edge state array is used to record test states of edge regions in the at least two sub-test graphs; after testing the hardware to be tested according to the test parameters corresponding to the target region, determining that the target region is located at an edge of the sub-test graph, and updating a test state of the target region in the edge state array to tested.

4. The method of claim 3, wherein, the edge state array comprises a third array and a fourth array; the updating of the test state of the target region in the edge state array to tested comprises: updating a value representing the test state of the target region in the third array from a fifth value to a sixth value, and updating a value representing the test state of the target region in the fourth array from a seventh value to an eighth value.

5. The method of claim 4, wherein, the method further comprises: If the to-be-tested region is located at an edge of any of the at least two sub-test maps, mark the test state of the to-be-tested region in the edge state array as to-be-tested.

6. The method of claim 5, wherein, The marking of the test state of the to-be-tested region in the edge state array as to-be-tested comprises: updating a value representing the test state of the to-be-tested region in the fourth array from the eighth value to the seventh value.

7. The method of claim 3, wherein, The method further comprises: after completing the test on each target region in the sub-test map, determining a next test sub-test map according to an edge region with a corresponding test state of to-be-tested in the edge state array; updating the test state of the edge region of the next test sub-test map from the edge state array to the initialized sub-map state array, and performing the test on each target region in the next test sub-test map.

8. The method of claim 1 or 2, wherein, The filling processing on the target region of the test map according to the test result comprises: filling the number of error codes indicated by the test result to the target region of the test map; or if the number of error codes indicated by the test result is within a value range, filling a color corresponding to the value range to the target region of the test map, wherein the value range comprises at least three, and different value ranges correspond to different filling colors.

9. A hardware testing device, the device comprising: a division module configured to divide a test map into at least two sub-test maps, the sub-test maps comprising a×b regions, a and b are both integers equal to or greater than 2; a generation module configured to generate a sub-map state array, wherein the sub-map state array is used to record the test state of a region in the sub-test map; a processing module configured to perform the following processing on one or more of the at least two sub-test maps respectively to obtain a test result map corresponding to a to-be-tested hardware: determining a target region from the sub-test map according to the sub-map state array; testing the to-be-tested hardware according to a test parameter corresponding to the target region to obtain a test result, and updating the sub-map state array; performing filling processing on the target region of the test map according to the test result; and initializing the sub-map state array after completing the test on each target region in the sub-test map. The updating of the sub-map state array by the processing module comprises: updating the test state of the target region in the sub-map state array as tested; if the number of error codes indicated by the test result is within a value range, marking the test state of an untested region adjacent to the target region as to-be-tested; wherein the target region is determined from the regions marked as to-be-tested in the sub-test map. In a case where the subgraph state array includes a first array and a second array, the processing module updates the test state of the target region in the subgraph state array as tested, including: updating a value representing the test state of the target region in the first array from a first value to a second value, and updating a value representing the test state of the target region in the second array from a third value to a fourth value; and the processing module marks the test state of an untested region adjacent to the target region as to-be-tested, including: updating a value representing the test state of the to-be-tested region in the second array from the fourth value to the third value, wherein the to-be-tested region is an untested region adjacent to the target region in the test graph.

10. An electronic device comprising: The processor, the memory, and the communication interface are in communication with each other through the communication bus; The memory is configured to store at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the hardware testing method in any one of claims 1-8. 11.A computer storage medium having a computer program stored thereon, the program being executed by a processor to implement the hardware testing method in any one of claims 1-8. 12.A computer program product comprising computer instructions, the computer instructions instructing a computing device to perform the hardware testing method in any one of claims 1-8.

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