UVM verification platform supporting single-port and double-port pcie SSD

Abstract

The invention relates to the field of chip verification, in particular to a UVM verification platform supporting a single-port and double-port pcie SSD. Comprising a UVM component, an adapter, a global configuration manager and a top layer interface, the UVM component inherits from UVMenv and comprises hosteenv, ambaenv and lcpuenv, the adapter comprises a clock generation module and a connector, the global configuration manager is used for controlling a single-dual port mode, channel overturning and polarity reversal, and the top layer interface comprises a root complex phy, an axi bus interface, an apb bus interface and an ahb bus interface. According to the invention, a single-port and double-port environment does not need to be maintained through macro management, and multiplexing and flexible configuration of the single-port and double-port component are realized through the global configuration manager. Compared with a macro management verification environment, recompiling is not needed when a single-port and double-port PCIe test function is tested, the port mode can be switched by controlling simulation parameters, one-time compiling and multi-time simulation are achieved, and verification efficiency is improved.

Description

Technical Field

[0001] The invention relates to the field of chip verification, in particular to a UVM verification platform supporting single-port and dual-port PCIE SSDs. Background Art

[0002] With the continuous development of solid-state drive (SSD) technology, especially PCIe interface SSD, it is becoming more and more popular in the consumer and enterprise markets due to its high performance and reliability. Single-port PCIe SSD is widely used by various high-end users with its unified specifications and excellent transmission bandwidth. However, dual-port PCIe SSD is gradually gaining favor in the field of all-flash storage due to its higher reliability. The dual-port design can realize redundant backup, improve data security, and meet the high availability requirements of enterprises for storage systems.

[0003] For single-port and dual-port PCIe SSD chip verification platform work, macros are usually used to switch between different modes. Due to the different configurations of single and dual ports, dual verification environments need to be managed, resulting in reduced verification efficiency. Therefore, it is crucial to develop a simple and efficient switching mechanism and a stable and reliable verification environment. This platform helps reduce verification complexity, improve verification efficiency, provide reliable support for single-port and dual-port PCIe SSD chip verification work, and promote progress in the field of technology. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a UVM verification platform supporting single- and dual-port PCIe SSDs, which does not require macro management to maintain the single- and dual-port environments, and realizes the reuse and flexible configuration of single- and dual-port components through a global configuration manager.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a UVM verification platform supporting single and dual port PCIE SSD, including UVM components, adapters, global configuration managers and top-level interfaces; UVM components include Host_env, amba_env, and lcpu_env; Host_env inherits from uvm_env and is used to encapsulate the host, root complex, and components related to the root complex and host adapter to facilitate environment management, including host agent, root complex agent, and host2rc adapter. The host agent is a component used to implement simulated host behavior, including a driver, monitor, and sequencer; the root complex agent is a component used to implement simulated RC behavior, including a root complex driver, monitor, and sequencer. The host2rc adapter is used to adapt to compatibility issues between different hosts and root complexes. When single-port mode is selected, Host_env is instantiated only once; when dual-port mode is selected, Host_env is instantiated twice and runs concurrently; amba_env inherits from uvm_env and is used to encapsulate various protocol environments in amba to facilitate environment management, including axi_env, apb_env and ahb_env. axi_env, apb_env and ahb_env are used to verify whether the AXI, APB and AHB interfaces in the design comply with relevant protocol specifications to ensure that data transmission, control signals and response mechanisms are correct. axi_env, apb_env and ahb_env all contain corresponding bus agents, which include drivers, monitors and sequencers. For the common bus in dual-port mode, the corresponding agent is instantiated only once in single-port and dual-port modes, and for the independent bus in dual-port mode, the corresponding agent is instantiated twice; lcpu_env inherits from uvm_env and is used to configure relevant registers and interrupt processing during the power-on process; The global configuration manager is connected to the UVM component to control the single and dual port modes; The top-level interfaces include the root complex interface, axi bus interface, apb bus interface, and ahb bus interface; The adapter is used for adapting the interconnection between the root complex and the endpoint device serial interface in different port modes and generating a reference clock that matches it. Host_env is connected to the device under test through the root complex interface and the adapter, and amba_env is connected to the device under test through the axi bus interface, apb bus interface, and ahb bus interface. In single-port mode, the verification platform forms a 4-channel link with the device under test through the root complex interface and the adapter. In dual-port mode, the verification platform forms two independent 2-channel links with the device under test through the root complex interface and the adapter.

[0006] Furthermore, the adapter includes a clock generation module and a connector, the connector is connected to the root complex and the device under test, the clock generation module is used to generate a clock signal and send it to the device under test, and the connector and the clock generation module are connected with a dual-port enable signal and other control signals; in single-port mode, there is only one host and root complex, the host is responsible for initializing the PCIe bus and allocating resources to all devices connected to the bus, such as memory addresses, interrupts, etc., in this patent, host_env is used to simulate the host behavior, the root complex acts as a bridge between the host and the PCIe bus, and is responsible for mapping the host's memory and I / O address space to the PCIe bus; the connector connects the device under test tx0 / tx1 / tx2 / tx3 to the four lanes of the root complex RC0 respectively. Connect, the clock generation module generates the corresponding clock as required; in dual-port mode, 2 hosts and root complexes are required, the connector connects tx0 / rx0, tx1 / rx1 of the root complex RC0 with tx0 / rx0, tx1 / rx1 of the device under test, and connects tx0 / rx0, tx1 / rx1 of the root complex RC1 with tx2 / rx2, tx3 / rx3 of the device under test, and the clock generation module generates the corresponding clock as required.

[0007] Furthermore, the clock generation module generates a normal clock and an unstable clock according to requirements.

[0008] Furthermore, other control signals include channel flipping. After channel flipping is enabled, in single-port mode, the adapter reversely connects the four channels of the root complex RC0 with the four channels of the device under test to realize the verification of the single-port channel flipping function point. In dual-port mode, the adapter reversely connects the two channels of the root complex RC0 and RC1 with the corresponding channels of the device under test to realize the verification of the dual-port channel flipping function point.

[0009] Furthermore, other control signals include polarity inversion. When polarity inversion is enabled, the adapter will reverse the polarity of the differential signals of tx and rx in each channel regardless of single-port or dual-port mode.

[0010] Furthermore, the global manager is a class, which is instantiated in the uvm_test component in UVM, and broadcasts the handle to the UVM component through the uvm_config_db mechanism. The UVM component instantiates the components required for the single and dual ports and configures the corresponding registers according to the requirements of the global configuration manager.

[0011] Furthermore, the top level of the verification platform is a module, which is used to instantiate the top-level interface and adapter, and realize the connection between the verification platform and the device under test; at the same time, according to different port modes, the corresponding virtual interface is sent to the specified UVM component.

[0012] Furthermore, the apb agent is a dual-port common configuration interface, and the axi agent and ahb agent are independent buses in dual-port mode.

[0013] The beneficial effects of the present invention are as follows: a strategy for building a single / dual-port PCIe verification platform is provided, and the single / dual-port environment does not need to be maintained through macro management. The single / dual-port components can be reused and flexibly configured through a global configuration manager. For example, the global configuration manager contains a configuration signal for selecting a single / dual-port mode. By modifying the port mode in the build_phase in the uvm environment, the uvm_test component in the uvm can obtain the configuration information and instantiate one or two host_env, amba_env, and lcpu_env according to the configuration information.

[0014] Compared with the macro management verification environment, there is no need to recompile when testing single-port and dual-port PCIe test functions. The port mode can be switched by controlling the simulation parameters, achieving one-time compilation and multiple simulations, thus improving verification efficiency. Provided is an adapter for both single-port and dual-port PCIe, which can realize automatic connection of single and dual ports and automatic generation of reference clocks, and facilitate fast switching of port modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a principle block diagram of the present invention; Figure 2 This is the functional block diagram of amba_env; Figure 3 This is the principle block diagram of the adapter. DETAILED DESCRIPTION

[0016] The present invention will be further described below in conjunction with the accompanying drawings and specific implementations.

[0017] Example 1 This embodiment discloses a UVM verification platform supporting single and dual port PCIE SSD. The present invention is a verification platform built based on UVM (Universal Verification Methodology). Figure 1As shown, it includes UVM components, adapters, global configuration managers and top-level interfaces. The top level of the verification platform is a module, which is used to instantiate top-level interfaces and adapters. The top-level interfaces include root complex (RC) phy, axi bus interface, apb bus interface, ahb bus interface, etc., and realize the connection between the verification platform and the device under test; at the same time, according to different port modes, the uvm_config_db mechanism in UVM is used to send the corresponding virtual interface to the specified UVM component. In this embodiment, the axi and ahb bus interfaces are two independent groups of interfaces in port 0 and port 1, and the apb bus interface is an interface shared by port 0 and port 1. Instantiate the adapter to automatically complete the connection between the verification platform TB and the device under test. The global configuration manager is connected to the UVM component to control the single-port and dual-port modes, channel flipping, polarity inversion, etc. The global manager is a class that is instantiated in the uvm_test component in UVM, and the handle is broadcast to the above-mentioned UVM components through the uvm_config_db mechanism. Each component instantiates the components required for single and dual ports and configures the corresponding registers according to the requirements of the global configuration manager. As mentioned above, when the global configuration manager selects the single-port mode, it instantiates 1 group of axi, ahb, apb bus interfaces and corresponding axi, ahb, apb env, 1 group of root complex (RC) phy and corresponding host_env. When the global configuration manager is configured for dual-port mode, it instantiates 2 groups of axi, ahb bus interfaces and corresponding axi, ahb env, 1 group of apb bus interfaces and corresponding apb env, 2 groups of root complex (RC) phy and corresponding host_env.

[0018] UVM components include Host_env, amba_env, and lcpu_env; when the single-port mode is selected, these three envs are only instantiated once, and when the dual-port mode is selected, these three envs are instantiated twice to achieve environment multiplexing and independent configuration in dual-port mode. Host_env inherits from uvm_env and is used to encapsulate the host, root complex, and components related to the root complex and host adapter to facilitate environmental management. It includes host agent, root complex agent, and host2rc adapter. The host agent is a component used to implement simulated host-related behaviors, including drivers, monitors, and sequencers; the root complex agent is a component used to implement simulated RC behaviors, including root complex drivers, monitors, and sequencers. The host2rc adapter is to adapt to compatibility issues between different hosts and root complexes. When the single-port mode is selected, Host_env is only instantiated once; when the dual-port mode is selected, Host_env is instantiated twice and runs concurrently without interfering with each other. amba_env inherits from uvm_env and is used to encapsulate various protocol environments in amba to facilitate environmental management, such as Figure 2 As shown, it includes axi_env, apb_env and ahb_env. axi_env, apb_env and ahb_env are used to verify whether the AXI, APB and AHB interfaces in the design comply with the relevant protocol specifications to ensure that data transmission, control signals and response mechanisms are correct. axi_env, apb_env and ahb_env all contain corresponding bus agents, which include drivers, monitors and sequencers. For the common bus in dual-port mode, the corresponding agent is only instantiated once in both single-port and dual-port modes. For the independent bus in dual-port mode, the corresponding agent is instantiated twice; and they are executed concurrently. Among them, apb agent is a dual-port common configuration interface, and axi agent and ahb agent are independent buses in dual-port mode.

[0019] lcpu_env inherits from uvm_env and is used for configuration of related registers and interrupt processing during the power-on process.

[0020] The adapter is used to adapt the interconnection between the root complex and the endpoint device serial interface in different port modes and generate a matching reference clock. Host_env is connected to the device under test through the root complex interface and the adapter, and amba_env is connected to the device under test through the axi bus interface, apb bus interface, and ahb bus interface. In single-port mode, the verification platform forms a 4-channel link with the device under test through the root complex interface and the adapter. In dual-port mode, the verification platform forms two independent 2-channel links with the device under test through the root complex interface and the adapter.

[0021] like Figure 3 As shown, the adapter includes a clock generation module and a connector, the connector is connected to the root complex and the device under test gradually, the clock generation module is used to generate a clock signal and send it to the device under test, and the connector and the clock generation module are connected with a dual-port enable signal and other control signals; in the single-port mode, there is only one host and a root complex, the connector connects the device under test tx0 / tx1 / tx2 / tx3 to the four lanes of the root complex RC0 respectively, and the clock generation module generates the corresponding clock according to the requirements; in the dual-port mode, two hosts and root complexes are required, the connector connects the tx0 / rx0, tx1 / rx1 of the root complex RC0 to the tx0 / rx0, tx1 / rx1 of the device under test, and the tx0 / rx0, tx1 / rx1 of the root complex RC1 is connected to the tx2 / rx2, tx3 / rx3 of the device under test, and the clock generation module generates the corresponding clock according to the requirements.

[0022] The clock generation module generates normal clock and unstable clock according to the requirements. Normal clock is like turning on pma0_refclk0 and turning off pma0_refclk1 / pma1_refclk0 / pma1_refclk1. The unstable clock is used to simulate the actual usage scenario.

[0023] Other control signals include channel flipping. After channel flipping is enabled, in single-port mode, the adapter reverses the four channels of the root complex RC0 with the four channels of the device under test to verify the single-port channel flipping function point. In dual-port mode, the adapter reverses the two channels of the root complex RC0 and RC1 with the corresponding channels of the device under test to verify the dual-port channel flipping function point.

[0024] Other control signals include polarity inversion. When polarity inversion is enabled, the adapter will reverse the polarity of the differential signals of TX and RX in each channel, regardless of single-port or dual-port mode.

[0025] The present invention provides a strategy for building a single / dual port PCIe verification platform, which does not require macro management to maintain a single / dual port environment, and implements the reuse and flexible configuration of single / dual port components through a global configuration manager. Compared with the macro management verification environment, when testing the single / dual port PCIe test function, there is no need to recompile, and the port mode can be switched by controlling simulation parameters, so that multiple simulations can be achieved through one compilation, thereby improving verification efficiency. An adapter for single / dual port PCIe is provided, which can realize automatic connection of single / dual ports and automatic generation of reference clocks, and facilitates rapid switching of port modes.

[0026] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A UVM verification platform supporting single and dual port PCIE SSD, characterized in that: Includes UVM components, adapters, global configuration manager, and top-level interfaces; UVM components include Host_env, amba_env, and lcpu_env; Host_env is inherited from uvm_env and is used for encapsulation of host, root complex, and root complex and host adapter components, including host agent, root complex agent, and host2rc adapter. Host agent is a component used to implement simulated host behavior, including driver, monitor, and sequencer; root complex agent is a component used to implement simulated RC behavior, including root complex driver, monitor, and sequencer. Host2rc adapter is used to achieve compatibility between different hosts and root complexes; host agent includes driver, monitor, and sequencer; root complex agent includes root complex driver, monitor, and sequencer. When single-port mode is selected, Host_env is instantiated only once; when dual-port mode is selected, Host_env is instantiated twice and runs concurrently; amba_ env is inherited from uvm_env and is used for encapsulation of various protocol environments in amba, including axi_env, apb_env and ahb_env. axi_env, apb_env and ahb_env all contain corresponding bus agents, which include drivers, monitors and sequencers. For the common bus in dual-port mode, the corresponding agent is only instantiated once in both single-port and dual-port modes. For the independent bus in dual-port mode, the corresponding agent is instantiated twice; lcpu_env is inherited from uvm_env and is used for configuration of relevant registers and interrupt processing during the power-on process; The global configuration manager is connected to the UVM component to control the single and dual port modes; The top-level interfaces include the root complex interface, axi bus interface, apb bus interface, and ahb bus interface; The adapter is used for adapting the interconnection between the root complex and the endpoint device serial interface in different port modes and generating a reference clock that matches it. Host_env is connected to the device under test through the root complex interface and the adapter, and amba_env is connected to the device under test through the axi bus interface, apb bus interface, and ahb bus interface. In single-port mode, the verification platform forms a 4-channel link with the device under test through the root complex interface and the adapter. In dual-port mode, the verification platform forms two independent 2-channel links with the device under test through the root complex interface and the adapter.

2. The UVM verification platform supporting single and dual port PCIE SSD according to claim 1, characterized in that: The adapter includes a clock generation module and a connector. The connector is connected to the root complex and the device under test. The clock generation module is used to generate a clock signal and send it to the device under test. The connector and the clock generation module are connected with a dual-port enable signal and other control signals. In single-port mode, there is only one host and a root complex. The host is responsible for initializing the PCIe bus and allocating resources to all devices connected to the bus. host_env is used to simulate the host behavior. The root complex serves as a bridge between the host and the PCIe bus and is responsible for mapping the host's memory and I / O address space to the PCIe bus. The connector connects the device under test tx0 / tx1 / tx2 / tx3 to the four lanes of the root complex RC0 respectively, and the clock generation module generates the corresponding clock as required; in dual-port mode, two hosts and root complexes are required, the connector connects the root complex RC0's tx0 / rx0, tx1 / rx1 to the device under test's tx0 / rx0, tx1 / rx1, and the root complex RC1's tx0 / rx0, tx1 / rx1 to the device under test's tx2 / rx2, tx3 / rx3, and the clock generation module generates the corresponding clock as required.

3. The UVM verification platform supporting single and dual port PCIE SSD according to claim 2, characterized in that: The clock generation module generates normal clock and unstable clock according to requirements.

4. The UVM verification platform supporting single and dual port PCIE SSD according to claim 2, characterized in that: Other control signals include channel flipping. After channel flipping is enabled, in single-port mode, the adapter reverses the four channels of the root complex RC0 with the four channels of the device under test to verify the single-port channel flipping function point. In dual-port mode, the adapter reverses the two channels of the root complex RC0 and RC1 with the corresponding channels of the device under test to verify the dual-port channel flipping function point.

5. The UVM verification platform supporting single and dual port PCIE SSD according to claim 2, characterized in that: Other control signals include polarity inversion. When polarity inversion is enabled, the adapter will reverse the polarity of the differential signals of TX and RX in each channel, regardless of single-port or dual-port mode.

6. The UVM verification platform supporting single and dual port PCIE SSD according to claim 1, characterized in that: The global manager is a class that is instantiated in the uvm_test component in UVM and broadcasts the handle to the UVM component through the uvm_config_db mechanism. The UVM component instantiates the components required for single and dual ports and configures the corresponding registers according to the requirements of the global configuration manager.

7. The UVM verification platform supporting single and dual port PCIE SSD according to claim 1, characterized in that: The top level of the verification platform is a module, which is used to instantiate the top-level interface and adapter, and realize the connection between the verification platform and the device under test; at the same time, according to different port modes, the corresponding virtual interface is sent to the specified UVM component.

8. The UVM verification platform supporting single and dual port PCIE SSD according to claim 1, characterized in that: apbagent is a dual-port common configuration interface, axi agent and ahb agent are independent buses in dual-port mode.

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