Command generation method and device for NAND controller test and medium

Abstract

The invention relates to the field of NAND testing, in particular to a command generation method and device for NAND controller testing and a medium. The generation process of random commands is divided into two stages: in the pre-generation stage, the types and the number of the commands are firstly determined, a memory space is applied according to the total number of the commands, and then main difference information of the current command and other commands is written into a memory unit space; in the instant generation stage, firstly, a frame test command containing a common part of each command and other commands is generated, main difference information stored in the pre-generation stage is read, secondary difference information is generated, and the frame test command is filled with the main difference information and the secondary difference information. And generating a complete test command and transmitting the test command to the NAND controller. According to the invention, by balancing the memory and CPU resources of the test system, the command generation efficiency of the test software can be improved so as to meet the pressure test requirement of the NAND controller.

Description

Technical Field

[0001] The present invention relates to the field of NAND testing, and in particular to a command generation method, device and medium for NAND controller testing. Background Art

[0002] In traditional random testing methods, random commands are usually generated just before they are sent. Since each configuration information in the command needs to be randomized one by one, the interval between command transmissions will be significantly increased, resulting in the risk of insufficient test pressure. If the command is randomly generated at the beginning to ensure the test pressure, a large memory space is required to store these commands to be sent, which places high demands on the hardware environment of the test system. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a command generation method, device and medium for NAND controller testing, which can improve the command generation efficiency of the test software by balancing the memory and CPU resources of the test system to meet the stress testing requirements of the NAND controller.

[0004] In order to solve the technical problem, the technical solution adopted by the present invention is: a command generation method for NAND controller testing, the method divides the random command generation process into two stages: a pre-generation stage and an immediate generation stage; In the pre-generation phase, the command type and quantity are first determined according to the configuration information sent by the tester, and a space is applied in the memory according to the total number of commands. Then, the sending order of each command is determined. According to the sending order of the commands, the main difference information between the current command and other commands is written into the divided memory unit space in sequence; In the immediate generation stage, a framework test command is first generated according to the test command format required for the NAND controller test. The framework test command contains the common parts of each command with other commands and can be used repeatedly. Then the test program reads the main difference information stored in the pre-generation stage and generates the secondary difference information at the same time. The main difference information and the secondary difference information are filled into the framework test command to generate a complete test command and transmit it to the NAND controller. In this way, test commands are generated in sequence until the predetermined number of commands is reached. There is an adjustable proportional relationship between the main difference information and the secondary difference information.

[0005] Furthermore, the ratio of the primary difference information to the secondary difference information is adjusted according to the memory size and the CPU computing power.

[0006] Furthermore, for a test machine whose memory is greater than the set requirement but whose CPPU computing power is less than the set requirement, all difference information is written into the memory as primary difference information in the pre-generation stage, and there is no need to generate secondary difference information in the immediate generation stage.

[0007] Furthermore, for a test set whose memory is less than the set requirement but whose CPU computing power is greater than the set requirement, the amount of secondary difference information is greater than the amount of primary difference information.

[0008] Furthermore, the main difference information includes command type, whether the scrambling function is enabled, whether the additional data function is enabled, whether the data check code function is enabled, and the data unit length.

[0009] Furthermore, the secondary difference information includes the specific storage address of the user data in the DDR, the specific storage address of the additional data in the DDR, the specific storage address of the data in the NAND, the command ID number, and the scrambling sequence to be used.

[0010] Furthermore, the configuration information includes the test command type, the number of each type of test commands, and the NAND address operated by the test command.

[0011] Furthermore, the sending order of each command is randomly determined and the secondary difference information is generated through a random function.

[0012] The present invention also discloses a command generation device for NAND controller testing, comprising a processor and a memory storing program instructions, wherein the processor is configured to execute the command generation method for NAND controller testing as described above when running the program instructions.

[0013] A storage medium stores program instructions, which, when running, execute the command generation method for NAND controller testing as described above.

[0014] Beneficial effects of the present invention: The method provided by the present invention is simple to operate, can adapt to a variety of hardware environments with different CPU computing power and memory space combinations, effectively reduces the command sending interval, and can simultaneously ensure test pressure and randomness, meeting the stable operation test requirements of the NAND controller under a large number of random command scenarios. Compared with traditional methods, under the premise of ensuring the same test capabilities, this method has stronger flexibility and environmental adaptability, and can give full play to the advantages and characteristics of different hardware platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of the present method; Figure 2 Schematic diagram of the device described in Example 2. DETAILED DESCRIPTION

[0016] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0017] Example 1 This embodiment discloses a command generation method for NAND controller testing, such as Figure 1 As shown, this method divides command generation into two stages: pre-generation and immediate generation.

[0018] Pre-generation phase: The main task of the test program is to randomly sort the commands sent according to the configuration information and write the main difference information of each command into the memory The main difference information includes: command type, whether the scrambling function is enabled, whether the additional data (Meta data) function is enabled, whether the data check code function is enabled, data unit length and other basic control information Instant generation phase: The main task of the test program is to read the primary difference information in the memory, combine it with the secondary difference information and framework commands generated in real time into a test command, and issue it Secondary difference information includes: the specific storage address of user data in DDR, the specific storage address of additional data (Meta data) in DDR, the specific storage address of data in NAND, command ID number, scrambling sequence to be used, and other detailed operation information required by the current command Specifically, this method is completed by the following steps: 1. The test program obtains the basic information configured by the tester through the interactive interface, including the test command type, the number of each type, the NAND address operated by the test command, and other control information; 2. The test program enters the test command pre-generation stage, applies for a sufficiently large memory space according to the total number of commands M, and divides it into M unit spaces of the same size; 3. Call the random function to randomly sort the commands, determine the sending order of each command, and write the main differences between the current command and other commands into the divided memory unit space in sequence according to the sending order; 4. The test program enters the command instant generation stage and generates a framework test command according to the command format required for NAND controller testing. The framework test command contains the common parts of each command with other commands and can be used repeatedly; 5. The test program reads the main difference information prepared in the memory and fills it into the framework test command; 6. The test program generates secondary difference information instantly through random functions, fills it into the framework test command, and then combines it into a complete test command and transmits it to the NAND controller; 7. Repeat steps 5 and 6 until the number of test commands sent reaches the predetermined number and the process ends.

[0019] In the above steps, the ratio of primary difference information to secondary difference information can be adjusted according to the memory size and CPU computing power to adapt to a variety of hardware environments including different CPU computing power and memory space sizes. For example, for a test machine whose memory is greater than the set requirement but whose CPU computing power is less than the set requirement, all difference information is written into the memory as primary difference information in the pre-generation stage, and there is no need to generate secondary difference information in the real-time generation stage, which minimizes the time interval for the test program to issue commands and ensures the test pressure. For a test set whose memory is less than the set requirement but whose CPU computing power is greater than the set requirement, the amount of secondary difference information is greater than the amount of primary difference information, and more difference information is generated in the real-time generation stage to reduce the memory usage in the pre-generation stage.

[0020] Example 2 The embodiment of the present disclosure provides a command generation device 300 for NAND controller testing, such as Figure 2 As shown, the device includes a processor 304 and a memory 301. Optionally, the device may also include a communication interface 302 and a bus 303. The processor 304, the communication interface 302, and the memory 301 may communicate with each other through the bus 303. The communication interface 302 may be used for information transmission. The processor 304 may call the logic instructions in the memory 301 to execute the command generation device method for NAND controller testing of the above embodiment.

[0021] In addition, the logic instructions in the memory 301 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0022] The memory 301 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes the function application and data processing by running the program instructions / modules stored in the memory 301, that is, the command generation device method for NAND controller testing in the above embodiment is implemented.

[0023] The memory 301 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 301 may include a high-speed random access memory and may also include a non-volatile memory.

[0024] Example 3 This embodiment provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the command generation method for NAND controller testing.

[0025] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0026] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0027] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0028] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

Claims

1. A command generation method for NAND controller testing, characterized in that: This method divides the random command generation process into two stages: pre-generation stage and immediate generation stage; In the pre-generation phase, the command type and quantity are first determined according to the configuration information sent by the tester, and a space is applied in the memory according to the total number of commands. Then, the sending order of each command is determined. According to the sending order of the commands, the main difference information between the current command and other commands is written into the divided memory unit space in sequence; In the immediate generation phase, a framework test command is first generated according to the test command format required for the NAND controller test. The framework test command contains the common parts of each command with other commands and can be used repeatedly. Then the test program reads the main difference information stored in the pre-generation phase, generates the secondary difference information at the same time, fills the main difference information and the secondary difference information into the framework test command, thereby generating a complete test command and transmitting it to the NAND controller. In this way, the test commands are generated in sequence until the predetermined number of commands is reached. There is an adjustable proportional relationship between the primary difference information and the secondary difference information.

2. The command generation method for NAND controller testing according to claim 1, characterized in that: Adjust the ratio of primary difference information to secondary difference information based on memory size and CPU computing power.

3. The command generation method for NAND controller testing according to claim 2, characterized in that: For a test machine whose memory is greater than the set requirement but whose CPPU computing power is less than the set requirement, all difference information is written into the memory as primary difference information in the pre-generation stage, and there is no need to generate secondary difference information in the immediate generation stage.

4. The command generation method for NAND controller testing according to claim 2, characterized in that: For the test set with less memory than the set requirement but more CPU power than the set requirement, the number of secondary difference information is greater than the number of primary difference information.

5. The command generation method for NAND controller testing according to claim 1, characterized in that: The main difference information includes command type, whether the scrambling function is enabled, whether the additional data function is enabled, whether the data check code function is enabled, and the data unit length.

6. The command generation method for NAND controller testing according to claim 1, characterized in that: The secondary difference information includes the specific storage address of the user data in DDR, the specific storage address of the additional data in DDR, the specific storage address of the data in NAND, the command ID number, and the scrambling sequence to be used.

7. The command generation method for NAND controller testing according to claim 1, characterized in that: The configuration information includes the test command type, the number of each type of test command, and the NAND address operated by the test command.

8. The command generation method for NAND controller testing according to claim 1, characterized in that: The sending order of each command and the generation of secondary difference information are randomly determined through a random function.

9. A command generation device for NAND controller testing, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the command generation method for NAND controller testing according to any one of claims 1 to 8 when running the program instructions.

10. A storage medium storing program instructions, characterized in that: When the program instructions are executed, the command generation method for NAND controller testing according to any one of claims 1 to 8 is executed.

Images