A memory access method and device, computer equipment and storage medium

Abstract

This application relates to a memory access method, apparatus, computer device, and storage medium. The method includes: identifying multiple non-consistent memory access nodes and allocating resources to the non-consistent memory access nodes; dividing storage objects in the storage system into multiple data segments; sequentially binding the multiple data segments to the multiple non-consistent memory access nodes; and in response to receiving a data access request, obtaining the logical block address of the data access request and determining the target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment. This method avoids cross-node memory access and solves the problems of insufficient utilization of computing and memory resources or the bottleneck effect in storage system performance in existing solutions.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a memory access method, apparatus, computer device, and storage medium. Background Technology

[0002] As the number of cores increases, processors evolve from SMP (Symmetric Multi-Processor) architecture to NUMA (Non-Uniform Memory Access) architecture. However, in NUMA architecture, when a processor core of a NUMA node accesses the memory of another node, it needs to access the memory through the QPI bus between nodes. This can lead to significant performance differences when the processor accesses the memory of its own node and other nodes.

[0003] To address the challenges of I / O processing in storage systems and reduce memory usage across NUMA access control blocks, existing technologies employ the following solutions: 1. Binding NUMA nodes to storage objects. However, if a user configures only one storage object, the computational and memory resources of only one NUMA node will be used during I / O access, leading to resource waste on other nodes. 2. Binding NUMA nodes to modules. However, the functions of different modules in the I / O stack vary, as do their computational load and memory access frequency. This results in significant differences in processor activity and memory access volume among NUMA nodes. If the CPU and memory resources of a NUMA node reach a bottleneck, the "weakest link" effect will occur. Summary of the Invention

[0004] Therefore, it is necessary to provide a memory access method, apparatus, computer device, and storage medium that can solve the performance problems caused by cross-node memory access, in response to the above-mentioned technical problems.

[0005] On the one hand, a memory access method is provided, the method comprising:

[0006] Identify multiple inconsistent memory access nodes and allocate resources to the inconsistent memory access nodes;

[0007] The storage objects in the storage system are divided into multiple data segments;

[0008] The multiple data segments are sequentially bound to the multiple non-consistent memory access nodes;

[0009] In response to receiving a data access request, the logical block address of the data access request is obtained, and the target data segment corresponding to the data access request is determined based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0010] In one embodiment, determining a plurality of inconsistent memory access nodes and allocating resources to each of the inconsistent memory access nodes includes:

[0011] The number of non-consistent memory access nodes is determined based on the hardware configuration;

[0012] Create a corresponding number of thread pools and memory pools based on the number of non-consistent memory access nodes, and bind the threads in the thread pools and the memory in the memory pools to the processor cores of the corresponding non-consistent memory access nodes, respectively.

[0013] In one embodiment, the partitioning of storage objects in the storage system to obtain multiple data segments includes:

[0014] Obtain the storage object in the storage system and the storage space of the storage object, wherein the storage space of the storage object is addressed according to linear space addressing;

[0015] Set the spatial granularity and segment the storage space of the storage object according to the spatial granularity to obtain multiple data segments;

[0016] The multiple data segments are sequentially linearly numbered to obtain the segment number of each data segment.

[0017] In one embodiment, before binding the plurality of data segments sequentially to the plurality of inconsistent memory access nodes, the method further includes:

[0018] The memory device information of the inconsistent memory access node is obtained respectively, and the validity of the inconsistent memory access node is determined based on the memory device information.

[0019] Based on the judgment result, the available non-consistent memory access nodes are determined, and the node number of the available non-consistent memory access nodes is obtained.

[0020] In one embodiment, binding the plurality of data segments sequentially to the plurality of inconsistent memory access nodes includes:

[0021] The data segments and the available non-consistent memory access nodes are sorted according to the segment number and node number, respectively, to form a data segment sequence and a node sequence;

[0022] Based on the data segment sequence and the node sequence, establish a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node;

[0023] According to the mapping relationship, the multiple data segments are sequentially and cyclically bound to the available non-consistent memory access nodes.

[0024] In one embodiment, the step of responding to receiving a data access request, obtaining the logical block address of the data access request, and determining the target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment, includes:

[0025] Receive data access requests, including data write requests and data read requests;

[0026] Obtain the logical block address of the data access request, and divide the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request;

[0027] Based on the mapping relationship between the segment number and the node number, the target non-consistent memory access node corresponding to the data access request is determined;

[0028] In response to the data access request being a data read request, the target data fragment is accessed through the target non-consistent memory access node.

[0029] In response to the data access request being a data write request, the first data volume of the target non-consistent memory access node and the second data volume of the data to be written corresponding to the data write request are obtained, wherein the first data volume is the remaining data volume of the corresponding memory.

[0030] Compare the first data volume and the second data volume;

[0031] In response to the first data volume being greater than or equal to the second data volume, the data to be written is written into the memory corresponding to the target non-consistent memory access node.

[0032] In one embodiment, the step of accessing memory through the target inconsistency memory access node corresponding to the target data segment includes:

[0033] In response to the data access request being a data read request, computing resources and memory resources are obtained from the thread pool and memory pool corresponding to the target inconsistent memory access node, respectively.

[0034] The target data is accessed in segments based on the computing and memory resources.

[0035] On the other hand, a memory access device is provided, the device comprising:

[0036] An allocation module is used to identify multiple inconsistent memory access nodes and allocate resources to the inconsistent memory access nodes.

[0037] The partitioning module is used to divide the storage objects in the storage system into multiple data segments;

[0038] A binding module is used to bind the multiple data segments sequentially to the multiple non-consistent memory access nodes;

[0039] The access module is used to respond to a received data access request, obtain the logical block address of the data access request, and determine the target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0040] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0041] Identify multiple inconsistent memory access nodes and allocate resources to the inconsistent memory access nodes;

[0042] The storage objects in the storage system are divided into multiple data segments;

[0043] The multiple data segments are sequentially bound to the multiple non-consistent memory access nodes;

[0044] In response to receiving a data access request, the logical block address of the data access request is obtained, and the target data segment corresponding to the data access request is determined based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0045] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0046] Identify multiple inconsistent memory access nodes and allocate resources to the inconsistent memory access nodes;

[0047] The storage objects in the storage system are divided into multiple data segments;

[0048] The multiple data segments are sequentially bound to the multiple non-consistent memory access nodes;

[0049] In response to receiving a data access request, the logical block address of the data access request is obtained, and the target data segment corresponding to the data access request is determined based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0050] The aforementioned memory access method, apparatus, computer device, and storage medium configure NUMA nodes and allocate computing and memory resources. Then, the storage object is divided into multiple data segments according to the storage space and bound to different NUMA nodes. Thus, when a data access request is received, the target data segment to be accessed is calculated based on the logical block address, avoiding cross-NUMA node memory access. At the same time, it solves the problem of insufficient utilization of computing and memory resources or the bottleneck effect in storage system performance in existing solutions. Attached Figure Description

[0051] Figure 1 This is a block diagram of an inconsistent memory access architecture in the prior art;

[0052] Figure 2 This is a flowchart illustrating the storage system I / O stack in one embodiment;

[0053] Figure 3 This is a flowchart illustrating a memory access method in one embodiment;

[0054] Figure 4 This is a block diagram of a non-consistent memory access architecture in one embodiment;

[0055] Figure 5 This is a schematic diagram illustrating the partitioning of storage object space in one embodiment;

[0056] Figure 6 This is a schematic diagram illustrating the mapping relationship between data fragments and inconsistent memory access nodes in one embodiment;

[0057] Figure 7 This is a structural block diagram of a memory access device in one embodiment;

[0058] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0060] like Figure 1As shown, in traditional NUMA architectures, the processor core is divided into multiple NUMA nodes, each with its own independent memory access controller, memory space, and PCIe bus system. Each node accesses its own memory through its own memory access controller and bus system, without interfering with each other. This improves memory concurrency and solves the memory access bottleneck problem caused by all processor cores sharing a single bus in SMP architectures. However, in a NUMA architecture, when a processor core in one NUMA node accesses the memory of another node, it needs to access it through the inter-node QPI bus. This leads to significant performance differences when the processor accesses memory within its own node versus other nodes; for example, the latency for accessing memory within its own node is 60–100 ns, while the latency for cross-node memory access is 140–200 ns. Therefore, in a NUMA architecture, to improve system performance, the system and applications should utilize the memory of their own node as much as possible during runtime, minimizing cross-node memory access.

[0061] like Figure 2 As shown, the I / O stack of a storage system for handling I / O requests includes the following main modules: Front-end protocol, which interacts with the host through the storage protocol and parses the I / O requests submitted by the host according to the protocol content; Disaster recovery service, which mainly provides disaster recovery services such as snapshots, backups, remote replication, and dual-active operation; Cache, which caches hot data to reduce the latency of host I / O request access; Storage pool, which performs virtualization management of the storage space of the storage system; RAID (Redundant Array of Independent Disks), which performs array management of storage disks (including mechanical disks and SSD disks), providing redundancy protection and multi-disk concurrent processing capabilities; and Back-end protocol, which manages the storage disks and submits I / O requests to the disks through the storage protocol for data access.

[0062] An I / O request needs to be passed through various modules in the I / O stack. Each module needs to generate and save some control information during the I / O request processing; this collection of control information is called the I / O request control block. The control block information is stored in memory. Therefore, when an I / O request arrives at a module, it needs to allocate memory resources to store the control block information. This memory is accessed during I / O processing and released after I / O is completed. Therefore, the storage system involves a large number of processor memory accesses during I / O operations. If these memory accesses involve a large number of cross-node memory accesses, it will significantly impact performance.

[0063] In one embodiment, such as Figure 3-6 As shown, a memory access method is provided, including the following steps:

[0064] Step S1: Identify multiple non-consistent memory access nodes and allocate resources to them.

[0065] In an optional implementation, multiple non-consistent memory access nodes are identified, and resources are allocated to each non-consistent memory access node, including: determining the number of non-consistent memory access nodes based on hardware configuration; creating a corresponding number of thread pools and memory pools based on the number of non-consistent memory access nodes, and binding the threads in the thread pools and the memory in the memory pools to the processor cores of the corresponding non-consistent memory access nodes, respectively.

[0066] like Figure 4 As shown, the number of NUMA nodes in the current system is determined based on the system's hardware configuration during system initialization. Each NUMA node corresponds to a thread pool and a memory pool, enabling the storage system to organize and manage computing and memory resources at the granularity of NUMA nodes. This better solves the performance problems caused by accessing memory across NUMA nodes under the NUMA architecture.

[0067] Step S2: Divide the storage objects in the storage system to obtain multiple data segments.

[0068] In an optional implementation, the storage objects in the storage system are divided into multiple data segments, including: obtaining the storage objects in the storage system and the storage space of the storage objects, wherein the storage space of the storage objects is linearly spatially addressed; setting the spatial granularity and segmenting the storage space of the storage objects according to the spatial granularity to obtain multiple data segments; and sequentially linearly numbering the multiple data segments to obtain the segment number of each data segment.

[0069] The storage objects in the storage system include LUNs (Logical Units), RAID (Range Array of Independent Disks), and data disks (mechanical disks or SSDs), all of which are linearly addressable. For example... Figure 2 As shown, the objects of operation for the front-end protocol, disaster recovery service, cache, and storage pool in the storage I / O stack are LUNs (logical volumes); the objects of operation for the RAID module are RAID; and the objects of operation for the back-end protocol are data disks.

[0070] like Figure 5 As shown, the space granularity is set to 32MB, dividing these storage objects into multiple data segments with a granularity of 32MB. It is understood that the space granularity here can be set according to actual needs and is not specifically limited here.

[0071] By segmenting the storage space of the stored objects according to a fixed spatial granularity and binding each data segment to a different NUMA node, the data access path is optimized, avoiding the latency caused by cross-node communication. This improves the response speed and throughput of I / O operations and ensures more even resource usage among NUMA nodes. This not only reduces the probability of the "weakest link" effect but also improves the overall system resource utilization.

[0072] Step S3: Bind multiple data segments to multiple non-consistent memory access nodes in sequence.

[0073] In an optional implementation, before binding multiple data segments sequentially to multiple non-consistent memory access nodes, the method further includes: obtaining memory device information of the non-consistent memory access nodes respectively, and determining whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes based on the determination result, and obtaining the node number of the available non-consistent memory access nodes.

[0074] Specifically, by determining whether a NUMA node is valid, data segmentation and binding to invalid or faulty nodes can be avoided, greatly reducing the risk of data loss or system crashes due to hardware problems. When some NUMA nodes are detected to be unavailable, the system can dynamically adjust the binding strategy according to the actual situation and select other available nodes to continue working, enhancing the system's fault tolerance and stability.

[0075] In an optional implementation, multiple data segments are sequentially bound to multiple non-consistent memory access nodes, including: sorting the data segments and available non-consistent memory access nodes according to segment number and node number, respectively, to form a data segment sequence and a node sequence; establishing a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node based on the data segment sequence and the node sequence; and sequentially binding multiple data segments to the available non-consistent memory access nodes according to the mapping relationship.

[0076] like Figure 6 As shown, taking LUN as a storage object as an example, assuming there are 4 NUMA nodes in the storage system, LUN 0 is divided into multiple 32MB data segments. The 1st, 2nd, 3rd, and 4th data segments are bound to the thread pool and memory pool of NUMA nodes 1, 2, 3, and 4 respectively. The 5th data segment is bound to NUMA node 1 again, and so on. Each data segment is bound to the corresponding NUMA node in a cyclic manner according to the segment number to achieve uniform distribution.

[0077] Based on the above steps, a mapping relationship is established between the sorted segment numbers and node numbers. By using a cyclic binding method, it is ensured that each data segment can be evenly distributed to each NUMA node. This helps to achieve load balancing of each NUMA node during I / O access, avoids the situation where some nodes are overloaded while other nodes are idle, and thus improves the overall system resource utilization efficiency.

[0078] Step S4: In response to receiving a data access request, obtain the logical block address of the data access request, and determine the target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0079] In an optional implementation, in response to receiving a data access request, obtaining the logical block address of the data access request, and determining the target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment, includes: receiving a data access request, the data access request including a data write request and a data read request; obtaining the logical block address of the data access request, and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access on the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data volume of the target non-consistent memory access node, and a second data volume of the data to be written corresponding to the data write request, wherein the first data volume is the remaining data volume in the corresponding memory; comparing the first data volume with the second data volume; in response to the first data volume being greater than or equal to the second data volume, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0080] Specifically, the logical block address (LBA) of the data access request is first divided by a preset space granularity, such as 32MB in this case, to calculate the segment number of the data segment to be accessed. Then, the remainder is taken with respect to the number of NUMA nodes to calculate the NUMA node to which the data access request belongs. The computing and memory resources required to process the request are then requested from the thread pool and memory pool of the corresponding NUMA node.

[0081] This scheme allows the logical block address to determine which NUMA node to obtain the computing and memory resources needed to process data access requests, ensuring that each data access request is evenly distributed across the NUMA nodes, maximizing the utilization of existing resources and achieving a more uniform load distribution.

[0082] In an optional implementation, in response to a data access request being a data write request, a target non-consistent memory access node is designated as a first node, wherein the first node includes first memory; in response to a first data volume being less than a second data volume, the first memory is determined to be unavailable memory; the distance between the first node and other non-consistent memory access nodes is obtained, and the non-consistent memory access node with the smallest distance from the first node is designated as a second node, wherein the second node includes second memory; a third data volume in the second memory is compared with the second data volume, wherein the third data volume is the remaining data volume in the second memory; in response to a third data volume being greater than or equal to the second data volume, the second memory is determined to be available memory; the data write request is forwarded from the first node to the processor of the second node, and the data to be written is written into the second memory according to the processor of the second node.

[0083] In an optional implementation, memory access is performed through the target non-consistent memory access node corresponding to the target data segment, including: responding to the data access request as a data read request, obtaining computing resources and memory resources from the thread pool and memory pool corresponding to the target non-consistent memory access node respectively; and accessing the target data segment based on the computing resources and memory resources.

[0084] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, Figure 2 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0085] In one embodiment, such as Figure 7 As shown, a memory access device is provided, including: an allocation module, a partitioning module, a binding module, and an access module, wherein:

[0086] The allocation module is used to identify multiple inconsistent memory access nodes and allocate resources to them.

[0087] The partitioning module is used to divide the storage objects in the storage system into multiple data segments;

[0088] The binding module is used to bind multiple data segments sequentially to multiple non-consistent memory access nodes;

[0089] The access module is used to respond to a received data access request, obtain the logical block address of the data access request, and determine the target data segment corresponding to the data access request based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0090] In one embodiment, the allocation module is further configured to determine the number of non-consistent memory access nodes based on the hardware configuration; create a corresponding number of thread pools and memory pools based on the number of non-consistent memory access nodes; and bind the threads in the thread pools and the memory in the memory pools to the processor cores of the corresponding non-consistent memory access nodes, respectively.

[0091] In one embodiment, the partitioning module is further configured to obtain storage objects in the storage system and the storage space of the storage objects, wherein the storage space of the storage objects is addressed by linear space; set the space granularity and segment the storage space of the storage objects according to the space granularity to obtain multiple data segments; and sequentially linearly number the multiple data segments to obtain the segment number of each data segment.

[0092] In one embodiment, the system further includes a judgment module, which is used to obtain memory device information of non-consistent memory access nodes respectively, and judge whether the non-consistent memory access nodes are valid based on the memory device information; determine the available non-consistent memory access nodes according to the judgment result, and obtain the node number of the available non-consistent memory access nodes.

[0093] In one embodiment, the binding module is further configured to sort the data segments and available non-consistent memory access nodes according to the segment number and node number, respectively, to form a data segment sequence and a node sequence; based on the data segment sequence and node sequence, establish a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node; and bind multiple data segments to the available non-consistent memory access node in a cyclic manner according to the mapping relationship.

[0094] In one embodiment, the access module is further configured to receive data access requests, including data write requests and data read requests; obtain the logical block address of the data access request and divide the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determine the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, perform memory access on the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtain a first data volume of the target non-consistent memory access node and a second data volume of the data to be written corresponding to the data write request, wherein the first data volume is the remaining data volume in the corresponding memory; compare the first data volume with the second data volume; in response to the first data volume being greater than or equal to the second data volume, write the data to be written into the memory corresponding to the target non-consistent memory access node.

[0095] In one embodiment, the access module is further configured to respond to a data access request as a data read request, obtain computing resources and memory resources from the thread pool and memory pool corresponding to the target inconsistent memory access node, respectively; and access the target data in segments based on the computing resources and memory resources.

[0096] For specific limitations regarding memory access devices, please refer to the limitations on memory access methods above, which will not be repeated here. Each module in the aforementioned memory access device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0097] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 8 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores segmented data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a memory access method.

[0098] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0099] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0100] Identify multiple non-consistent memory access nodes and allocate resources to them;

[0101] The storage objects in the storage system are divided into multiple data segments;

[0102] Multiple data segments are sequentially bound to multiple non-consistent memory access nodes;

[0103] In response to receiving a data access request, the logical block address of the data access request is obtained, and the target data segment corresponding to the data access request is determined based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0104] In one embodiment, when the processor executes a computer program, it further performs the following steps: determining the number of non-consistent memory access nodes based on the hardware configuration; creating a corresponding number of thread pools and memory pools based on the number of non-consistent memory access nodes, and binding the threads in the thread pools and the memory in the memory pools to the processor cores of the corresponding non-consistent memory access nodes, respectively.

[0105] In one embodiment, when the processor executes the computer program, it further performs the following steps: obtaining a storage object in the storage system and the storage space of the storage object, wherein the storage space of the storage object is linearly space-addressed; setting the space granularity and segmenting the storage space of the storage object according to the space granularity to obtain multiple data segments; sequentially linearly numbering the multiple data segments to obtain the segment number of each data segment.

[0106] In one embodiment, when the processor executes the computer program, it further performs the following steps: obtaining memory device information of non-consistent memory access nodes respectively, and determining whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes based on the determination result, and obtaining the node number of the available non-consistent memory access nodes.

[0107] In one embodiment, when the processor executes the computer program, it further performs the following steps: sorting the data segments and available non-consistent memory access nodes according to the segment number and node number, respectively, to form a data segment sequence and a node sequence; establishing a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node based on the data segment sequence and the node sequence; and binding multiple data segments to the available non-consistent memory access node in a cyclic manner according to the mapping relationship.

[0108] In one embodiment, when the processor executes the computer program, it further performs the following steps: receiving a data access request, the data access request including a data write request and a data read request; obtaining the logical block address of the data access request and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request according to the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access on the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data volume of the target non-consistent memory access node and a second data volume of the data to be written corresponding to the data write request, wherein the first data volume is the remaining data volume in the corresponding memory; comparing the first data volume with the second data volume; in response to the first data volume being greater than or equal to the second data volume, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0109] In one embodiment, when the processor executes the computer program, it further performs the following steps: in response to a data access request as a data read request, it obtains computing resources and memory resources from the thread pool and memory pool corresponding to the target non-consistent memory access node, respectively; and accesses the target data in segments based on the computing resources and memory resources.

[0110] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0111] Identify multiple non-consistent memory access nodes and allocate resources to them;

[0112] The storage objects in the storage system are divided into multiple data segments;

[0113] Multiple data segments are sequentially bound to multiple non-consistent memory access nodes;

[0114] In response to receiving a data access request, the logical block address of the data access request is obtained, and the target data segment corresponding to the data access request is determined based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0115] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining a storage object in the storage system and the storage space of the storage object, wherein the storage space of the storage object is linearly space-addressed; setting the space granularity and segmenting the storage space of the storage object according to the space granularity to obtain multiple data segments; sequentially linearly numbering the multiple data segments to obtain the segment number of each data segment.

[0116] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining memory device information of non-consistent memory access nodes respectively, and determining whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes based on the determination result, and obtaining the node number of the available non-consistent memory access nodes.

[0117] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining memory device information of non-consistent memory access nodes respectively, and determining whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes based on the determination result, and obtaining the node number of the available non-consistent memory access nodes.

[0118] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: sorting the data segments and available non-consistent memory access nodes according to the segment number and node number, respectively, to form a data segment sequence and a node sequence; establishing a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node based on the data segment sequence and the node sequence; and binding multiple data segments to the available non-consistent memory access node in a cyclic manner according to the mapping relationship.

[0119] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: receiving a data access request, the data access request including a data write request and a data read request; obtaining the logical block address of the data access request and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request according to the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access on the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data volume of the target non-consistent memory access node and a second data volume of the data to be written corresponding to the data write request, wherein the first data volume is the remaining data volume in the corresponding memory; comparing the first data volume with the second data volume; in response to the first data volume being greater than or equal to the second data volume, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0120] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to a data access request as a data read request, it obtains computing resources and memory resources from the thread pool and memory pool corresponding to the target non-consistent memory access node, respectively; and accesses the target data in segments based on the computing resources and memory resources.

[0121] In one embodiment, a computer product is provided that stores a computer program, which, when executed by a processor, performs the following steps:

[0122] Identify multiple non-consistent memory access nodes and allocate resources to them;

[0123] The storage objects in the storage system are divided into multiple data segments;

[0124] Multiple data segments are sequentially bound to multiple non-consistent memory access nodes;

[0125] In response to receiving a data access request, the logical block address of the data access request is obtained, and the target data segment corresponding to the data access request is determined based on the logical block address, so as to perform memory access through the target non-consistent memory access node corresponding to the target data segment.

[0126] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining a storage object in the storage system and the storage space of the storage object, wherein the storage space of the storage object is linearly space-addressed; setting the space granularity and segmenting the storage space of the storage object according to the space granularity to obtain multiple data segments; sequentially linearly numbering the multiple data segments to obtain the segment number of each data segment.

[0127] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining memory device information of non-consistent memory access nodes respectively, and determining whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes based on the determination result, and obtaining the node number of the available non-consistent memory access nodes.

[0128] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: obtaining memory device information of non-consistent memory access nodes respectively, and determining whether the non-consistent memory access nodes are valid based on the memory device information; determining available non-consistent memory access nodes based on the determination result, and obtaining the node number of the available non-consistent memory access nodes.

[0129] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: sorting the data segments and available non-consistent memory access nodes according to the segment number and node number, respectively, to form a data segment sequence and a node sequence; establishing a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node based on the data segment sequence and the node sequence; and binding multiple data segments to the available non-consistent memory access node in a cyclic manner according to the mapping relationship.

[0130] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: receiving a data access request, the data access request including a data write request and a data read request; obtaining the logical block address of the data access request and dividing the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determining the target non-consistent memory access node corresponding to the data access request according to the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, performing memory access on the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtaining a first data volume of the target non-consistent memory access node and a second data volume of the data to be written corresponding to the data write request, wherein the first data volume is the remaining data volume in the corresponding memory; comparing the first data volume with the second data volume; in response to the first data volume being greater than or equal to the second data volume, writing the data to be written into the memory corresponding to the target non-consistent memory access node.

[0131] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to a data access request as a data read request, it obtains computing resources and memory resources from the thread pool and memory pool corresponding to the target non-consistent memory access node, respectively; and accesses the target data in segments based on the computing resources and memory resources.

[0132] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A memory access method, characterized by, include: Identify multiple inconsistent memory access nodes and allocate resources to the inconsistent memory access nodes; The storage objects in the storage system are divided into multiple data segments; The multiple data segments are sequentially bound to the multiple non-consistent memory access nodes; Receive data access requests, including data write requests and data read requests; Obtain the logical block address of the data access request, and divide the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; Based on the mapping relationship between the segment number and the node number, the target non-consistent memory access node corresponding to the data access request is determined; In response to the data access request being a data read request, the target data is segmented and accessed in memory through the target non-consistent memory access node. In response to the data access request being a data write request, the first data volume of the target non-consistent memory access node and the second data volume of the data to be written corresponding to the data write request are obtained, wherein the first data volume is the remaining data volume of the corresponding memory. Compare the first data volume and the second data volume; In response to the first data volume being greater than or equal to the second data volume, the data to be written is written into the memory corresponding to the target non-consistent memory access node.

2. The memory access method according to claim 1, characterized in that, The step of identifying multiple inconsistent memory access nodes and allocating resources to each of the inconsistent memory access nodes includes: The number of non-consistent memory access nodes is determined based on the hardware configuration; Create a corresponding number of thread pools and memory pools based on the number of non-consistent memory access nodes, and bind the threads in the thread pools and the memory in the memory pools to the processor cores of the corresponding non-consistent memory access nodes, respectively.

3. The memory access method according to claim 1, characterized in that, The storage objects in the storage system are divided into multiple data segments, including: Obtain the storage object in the storage system and the storage space of the storage object, wherein the storage space of the storage object is addressed according to linear space addressing; Set the spatial granularity and segment the storage space of the storage object according to the spatial granularity to obtain multiple data segments; The multiple data segments are sequentially numbered linearly to obtain the segment number of each data segment.

4. The memory access method according to claim 1, characterized in that, Before binding the plurality of data segments sequentially to the plurality of inconsistent memory access nodes, the method further includes: The memory device information of the inconsistent memory access node is obtained respectively, and the validity of the inconsistent memory access node is determined based on the memory device information. Based on the judgment result, determine the available non-consistent memory access nodes and obtain the node number of the available non-consistent memory access nodes.

5. The memory access method according to claim 4, characterized in that, The step of binding the multiple data segments sequentially to the multiple non-consistent memory access nodes includes: The data segments and the available non-consistent memory access nodes are sorted according to the segment number and node number, respectively, to form a data segment sequence and a node sequence; Based on the data segment sequence and the node sequence, establish a mapping relationship between the segment number of the data segment and the node number of the available non-consistent memory access node; According to the mapping relationship, the multiple data segments are sequentially and cyclically bound to the available non-consistent memory access nodes.

6. The memory access method according to claim 1, characterized in that, The response to the data access request being a data read request, including accessing the target data segments through the target inconsistent memory access node, includes: In response to the data access request being a data read request, computing resources and memory resources are obtained from the thread pool and memory pool corresponding to the target inconsistent memory access node, respectively. The target data is accessed in segments based on the computing and memory resources.

7. A memory access device, characterized in that, The device includes: An allocation module is used to identify multiple inconsistent memory access nodes and allocate resources to the inconsistent memory access nodes. The partitioning module is used to divide the storage objects in the storage system into multiple data segments; A binding module is used to bind the multiple data segments sequentially to the multiple non-consistent memory access nodes; An access module is configured to receive data access requests, including data write requests and data read requests; obtain the logical block address of the data access request and divide the logical block address of the data access request by the spatial granularity to determine the segment number of the target data segment corresponding to the data access request; determine the target non-consistent memory access node corresponding to the data access request based on the mapping relationship between the segment number and the node number; in response to the data access request being a data read request, perform memory access on the target data segment through the target non-consistent memory access node; in response to the data access request being a data write request, obtain a first data volume of the target non-consistent memory access node and a second data volume of the data to be written corresponding to the data write request, wherein the first data volume is the remaining data volume in the corresponding memory; compare the first data volume and the second data volume; in response to the first data volume being greater than or equal to the second data volume, write the data to be written into the memory corresponding to the target non-consistent memory access node.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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