Compression-based address mapping management in memory systems

Abstract

The invention relates to compression-based address mapping management in a memory system. A memory system may reduce the number of times a region of an address mapping table passes between a non-volatile memory and a local memory of the memory system. The memory system may selectively maintain regions of the address mapping table in local memory between checkpoint programs. During a checkpoint program, the memory system may compress the region of the address mapping table in the local memory, and may maintain the region in the local memory until a next checkpoint program if the region may be sufficiently compressed.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 18 / 771,713 filed on July 12, 2024 by He et al., entitled “Compression-Based Address Mapping Management in Memory Systems,” and priority to U.S. patent application No. 63 / 588,659 filed on October 6, 2023 by He et al., entitled “Compression-Based Address Mapping Management in Memory Systems,” each of which is assigned to the assignee of this patent application and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to compression-based address mapping management in memory systems. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented as a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, either of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selected memory, chalcogenide memory technology, NOR and NAND memory devices, etc. Memory cells can be described with respect to volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long period of time, even in the absence of an external power source. Memory cells configured in a volatile configuration may lose the stored state when disconnected from an external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: transfer a region of an address map associated with a first amount of data received from a host system from a non-volatile memory to a local memory; update the region of the address map with physical address information of the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compress the region of the address map in the local memory based at least in part on updating the region; and modify a bit value to indicate that transfer of the region to the non-volatile memory is to be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code, the code including instructions executable by a processor to: transfer a region of an address map associated with a first amount of data received from a host system from a non-volatile memory to a local memory; update the region of the address map with physical address information of the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compress the region of the address map in the local memory based at least in part on updating the region; and modify a bit value to indicate that transfer of the region to the non-volatile memory is to be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

[0008] A method is described. The method may include: transferring a region of an address map associated with a first amount of data received from a host system from a non-volatile memory to a local memory; updating the region of the address map with physical address information of the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compressing the region of the address map in the local memory based at least in part on updating the region; and modifying a bit value to indicate that transferring the region to the non-volatile memory is to be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting compression-based address map management in a memory system according to examples disclosed herein is shown.

[0010] Figure 2An example of a system supporting compression-based address map management in a memory system according to examples disclosed herein is shown.

[0011] Figure 3 An example of a process flow for supporting compression-based address map management in a memory system according to examples disclosed herein is shown.

[0012] Figure 4 A block diagram of a memory system supporting compression-based address map management in a memory system according to examples disclosed herein is shown.

[0013] Figure 5 A flow chart is shown illustrating one or more methods of supporting compression-based address map management in a memory system according to examples disclosed herein. DETAILED DESCRIPTION

[0014] The memory system may use an address mapping table to convert logical addresses (which may be used by the host system) to physical addresses (which may be used by the memory system), and vice versa. As the memory system writes host data to memory, the memory system may update regions of the address mapping table to reflect the physical addresses that map to the logical addresses associated with the data. To do this, the memory system may perform a checkpoint procedure in which the memory system retrieves a region of the address mapping table from nonvolatile memory, updates the region with the physical address information in local memory, and then returns (or "refreshes") the updated region to the nonvolatile memory. However, returning a region to the nonvolatile memory may be a time-consuming process that interferes with or delays other memory access procedures at the nonvolatile memory, among other disadvantages.

[0015] According to the technology described herein, a memory system can reduce the number of times that an area of ​​an address mapping table is returned to a non-volatile memory by selectively maintaining an area of ​​the address mapping table in a local memory between checkpoint procedures. During a checkpoint procedure, the memory system can compress an area of ​​the address mapping table in a local memory, and can cache the area (e.g., prevent it from being returned to a non-volatile memory) if the area is sufficiently compressible until the next checkpoint procedure. By caching an area in a local memory between checkpoint procedures, a memory system can reduce the number of times that an area of ​​an address mapping table is returned to a non-volatile memory, which can reduce overhead. The retention of compressed areas in a local memory can also allow a memory system to avoid retrieving the same area multiple times, as well as other advantages.

[0016] In addition to its applicability in the memory systems described herein, the techniques for compression-based address mapping management in memory systems can generally be implemented to improve the performance of various electronic devices and systems (including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games). Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, may be associated with relatively high processing requirements to meet user expectations. Therefore, improving the processing power of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density can improve user experience or attractiveness. Implementation of the techniques described herein can improve the performance of electronic devices by increasing the size of the L2P table that can be stored in local memory, which can increase the likelihood that the mapping of the logical address has been stored in the local memory 120 (e.g., the likelihood of a cache hit condition occurring increases). Such conditions can reduce processing or latency time, improve response time, or otherwise improve user experience, as well as other benefits.

[0017] The features of the present disclosure are first described in reference Figures 1 to 2 The features of the present disclosure are described in the context of systems, devices, and circuits. Figure 3 These and other features of the present disclosure are further described by reference to Figure 4 and 5 A device diagram and flow chart related to compression-based address mapping management in a memory system are shown and described in the context of the device diagram and flow chart.

[0018] Figure 1 An example of a system 100 supporting compression-based address mapping management in a memory system according to examples disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or any other computing device including a memory and a processing device.

[0019] The memory system 110 may be or include any device or device set, wherein the device or device set includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM) or a non-volatile DIMM (NVDIMM), among other devices.

[0020] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include interfacing with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0021] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105) using an associated protocol. Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0022] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (eg, non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to examples as described herein. The memory system controller 115 may also be coupled to and communicate with the memory devices 130 to perform operations, such as reading data, writing data, erasing data, or refreshing data at the memory devices 130—and other such operations—which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130. In some cases, the memory system controller 115 may exchange data (e.g., in response to or otherwise associated with commands from the host system 105) with the host system 105 and one or more memory devices 130. For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBA)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses (PBA)) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0026] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for internal storage or computation, e.g., related to the functions attributed herein to the memory system controller 115.

[0027] The memory device 130 may include one or more non-volatile memory cell arrays. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more volatile memory cell arrays. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0028] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As shown in , memory device 130 - a may include a local controller 135 - a, and memory device 130 - b may include a local controller 135 - b.

[0029] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package including one or more die 160. In some examples, die 160 may be a piece of electronic device-level semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, each page 175 may include a set of memory cells.

[0030] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity in supporting circuitry.

[0031] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed on different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, an individual block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may be performed. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d located in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 may have one or more restrictions, such as when the parallel operations are performed on memory cells within different pages 175 having the same page address within the respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes 165).

[0032] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0033] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof), but may be erased at a second granularity (e.g., at a block granularity). That is, page 175 may be the smallest unit of memory (e.g., a set of memory cells) that may be independently programmed or read (e.g., programmed or read in parallel as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a set of memory cells) that may be independently erased (e.g., erased in parallel as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they may be rewritten with new data. Thus, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0034] In some cases, an L2P table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated due to a more recent or updated version of the data being stored in a different page 175 of the memory device 130. Invalid data was previously programmed to an invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of such data stored on the memory device 130. A page 175 that contains no data may be a page 175 that has never been written to or has been erased.

[0035] In some cases, the memory system controller 115 or the local controller 135 may perform operations of the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting for some or all of the pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "garbage collection" may be invoked so that the block 170 is erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations including, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in a block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of blocks 170 that have been erased may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105).

[0036] In some cases, memory system 110 may use memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0037] The system 100 may include any number of non-transitory computer-readable media that support compression-based address mapping management in a memory system. For example, the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed to the host system 105, the memory system 110, or the memory device 130 herein. For example, such instructions, when executed by the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0038] The memory system 110 may use an address map, such as an L2P table, to perform address translation between logical addresses and physical addresses. To ensure maintenance of the address map (e.g., in the event of a power outage), the memory system 110 may store the address map in a non-volatile memory, such as one or more of the memory devices 130. To update or use the address map, the memory system 110 may transfer a region of the address map from the non-volatile memory to the local memory 120, which may be a volatile memory that is not large enough to hold the entire address map.

[0039] The address information used to update the address map can be maintained in a change log, and the memory system 110 can initiate a checkpoint procedure to update the address map if the size of the change log reaches a threshold size. For example, the memory system 110 can initiate a checkpoint procedure when it determines that the change log is x kB, which can correspond to the memory system 110 receiving a threshold amount of data from the host system 105. In other examples, the memory system can initiate a checkpoint procedure when it determines that the amount of data received from the host system 105 (e.g., for writing) meets the threshold amount.

[0040] During the checkpoint procedure, the memory system 110 may retrieve (from the non-volatile memory) an address-mapped region associated with the data received from the host system. For example, if the data received from the host system is associated with a set of logical addresses, the memory system 110 may retrieve an address-mapped region associated with a logical address in the set of logical addresses. In a sequential write, the set of logical addresses may be consecutively indexed logical addresses. In a random write, the set of logical addresses may be non-consecutively indexed. If the address mapping is organized according to consecutively indexed logical addresses, the number of regions retrieved for sequential writes may be greater than the number of regions retrieved for random writes. After retrieving the address-mapped region and writing the region to the local memory 120, the memory system 110 may update the region using a change log. Updating the region may include updating a physical address mapped to a logical address (e.g., updating an entry for logical address x to indicate that logical address x maps to physical address y).

[0041] At the end of the checkpoint procedure (e.g., after updating the region), the memory system 110 can transfer (e.g., flush) the region back to the non-volatile memory. However, flushing the region at the end of each checkpoint procedure may increase the latency of the memory system 110 (e.g., because writing the region to the non-volatile memory may interfere with other memory access operations of the non-volatile memory). Flushing the region at the end of each checkpoint procedure may also increase the number of times a given region is retrieved from the non-volatile memory, which may increase the overhead and latency associated with address translation.

[0042] According to the techniques described herein, the memory system 110 can selectively prevent a region of an address map from being flushed to non-volatile memory at the end of a checkpoint procedure. For example, after executing a first checkpoint procedure, the memory system 110 can delay refreshing the region associated with the first checkpoint procedure until a second (e.g., subsequent) checkpoint procedure ends. The condition for delaying the refresh can be that the region associated with the first checkpoint can be compressed (or has been compressed) by a threshold amount given by a compression factor.

[0043] Figure 2 An example of a system 200 for supporting compression-based address mapping management in a memory system according to an example disclosed herein is shown. The system 200 may be a reference Figure 1 The system 200 may include a memory system 210 configured to store data received from the host system 205 and send data to the host system 205 when requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may implement reference Figure 1The various aspects of the system 100 described herein. For example, the memory system 210 and the host system 205 may be instances of the memory system 110 and the host system 105, respectively. The memory system 210 may include: a local memory 220, which may be a reference Figure 1 The examples of local memory 120 described; and non-volatile memory device 215, which may be referenced Figure 1 Examples of one or more memory devices 130 are described.

[0044] The memory system 210 may receive a write command and associated data and logical addresses from the host system 205. For example, the memory system 210 may receive a write command for a set of data associated with a set of logical addresses, which in turn are associated with a set of regions of an address mapping table 230 stored by the non-volatile memory device 215. The address mapping table may also be referred to as an address map, address mapping information, or other suitable terms. A region of an address mapping table may refer to a set of entries having address mapping information for mapping a logical address to a physical address. A region of an address mapping table may also be referred to as a portion of an address mapping table, a subset of an address mapping table, or other suitable terms. In some cases, a region of an address mapping table may be a portion of an address mapping table that is transferred between a non-volatile memory device and a local memory.

[0045] The address mapping table 230 can be divided into regions that provide mapping information for different ranges of logical addresses. For example, region n can provide mapping information for N+1 consecutively indexed logical addresses, such as logical address k to logical address k+N. Each entry in a region can indicate a mapping (e.g., a corresponding relationship) between the logical address and the physical address of the entry. For example, region n can indicate that logical address k is mapped to physical address n. Although each entry is shown with an associated logical address and physical address pair, in some instances, a region may contain only physical addresses (e.g., a logical address may be implicitly associated with an entry, rather than necessarily being stored in the address mapping table 230).

[0046] Upon determining that a trigger condition for initiating a checkpoint procedure has been met, the memory system 210 may transfer a region of the address mapping table 230 from the non-volatile memory device 215 to the local memory 220 for updating. In some instances, the trigger condition may be that the size of the change log table 225 meets a threshold size. The change log table 225 may refer to a set of entries that indicate mapping information for mapping a logical address to a physical address. Upon receiving a command from the host system 205, the memory system 210 may temporarily store changes to the address mapping table 230 in the change log table 225. Such techniques may enable the memory system 210 to batch updates of the address mapping table 230 and improve efficiency for updating the address mapping table 230. As discussed, the change log table 225 may be stored in the local memory 220 and may track the physical address assigned to the logical address when data associated with the logical address is written to (or designated for) the non-volatile memory device 215. Thus, changes to the mapping information for a set of logical addresses may be accumulated in the change log table 225 and used to update the address mapping table region during a checkpoint procedure.

[0047] The regions transferred to the local memory 220 for the checkpoint procedure may be associated with the data received from the host system 205 (and therefore associated with the logical addresses in the change log table). For example, if the data received from the host system 205 is associated with a group of regions including region 1 to region n, the memory system 210 may transfer the group of regions from the non-volatile memory device 215 to the local memory 220. After transferring the group of regions to the local memory 220, the memory system 210 may update the group of regions using the change log table 225. For example, the memory system 210 may "merge" the change log table 225 with the group of regions by updating the entry of the region to indicate the physical address mapped to the associated logical address (as indicated by the change log table 225). In some cases, the local memory 220 may include a merge buffer for the region that updates the address mapping table 230 using the entry in the change log table 225. After the address mapping table 230 is updated using the entry of the change log table 225, the entry is removed from the change log table 225.

[0048] After updating the set of regions, the memory system 210 may compress the set of regions currently stored in the local memory 220. In some examples, the memory system 210 may compress the set of regions if a compression condition is met. For example, the memory system 210 may compress the set of regions if the number of regions in the set of regions meets a threshold number. For example, if the compression scheme of the address mapping table 230 compresses the information to less than half the size of the uncompressed information, the memory system 210 may implement compression. The memory system 210 may use any threshold amount of compression to determine whether it is worth compressing and retaining in the local memory 220.

[0049] Compressing a region may include modifying the region so that the information in the region is smaller in size (e.g., takes up less memory space). In some examples, the memory system 210 may compress a region by removing some entries of a set of logical addresses that map to consecutively indexed physical addresses (in which case the memory system 210 may add an offset index indicating how many entries have been removed). For example, the memory system 210 may compress region n by removing entries for physical addresses 513 to 515 and removing entries for physical addresses 601 to 603. Such information may be replaced with an indication that a certain number of addresses map consecutively (e.g., sequential logical addresses map to sequential physical addresses).

[0050] The amount of compression (e.g., reduction in size) applied to a region can be referred to as a compression factor for the region, and the collective amount of compression applied to a group of regions (which can be an average of the region-specific compression factors) can be referred to as the compression factor for the group of regions. To illustrate, if the size of region n is halved (e.g., region n changes from y kB to y / 2 kB), then the compression factor can be two. The compression factors for different regions can be the same or different. For example, the compression factor for region 1 can be 1.3 and the compression factor for region n can be 2. Similarly, the compression factor for a region can be different from the compression factor for the group of regions that include the region. For example, the compression factor for region 1 can be 1.3 and the compression factor for the group of regions can be three. Thus, the size of the group of regions can be size A before compression and size B after compression, where size B is smaller than size A.

[0051] After compressing the set of regions, the memory system 210 may determine whether to maintain the set of regions in the local memory 220 until the next checkpoint or flush the set of regions back to the non-volatile memory device 215. If the memory system 210 determines that the compression factor meets (e.g., is greater than or equal to) a threshold value (which may be selected to ensure that there is sufficient space in the local memory 220 for the regions associated with the next checkpoint), the memory system 210 may maintain the set of regions in the local memory 220 until the next checkpoint. Thus, the memory system 210 may delay the transfer of the set of regions until the next checkpoint (e.g., until at least one region is updated again), which may reduce the number of times the regions are transferred between the local memory 220 and the non-volatile memory device 215. If the compression factor does not meet the threshold value, the memory system 210 may decompress the set of regions and flush (e.g., transfer) the set of regions back to the non-volatile memory device 215.

[0052] In some examples, the memory system 210 may refrain from compressing the set of regions unless the memory system 210 predicts that the compression factor of the set of regions is likely to meet a threshold. Such techniques may allow the memory system 210 to avoid unnecessarily compressing the set of regions, decompressing the set of regions only upon determining (after compressing the set of regions) that the compression factor does not meet the threshold.

[0053] If a set of regions is maintained in the local memory 220 between a first checkpoint procedure and a second checkpoint procedure involving the second set of regions, the memory system 210 may prevent the second set of regions from being compressed (or maintained in the local memory 220). In other words, if the checkpoint procedure involving compression and maintenance of regions in the local memory 220 is referred to as an enhanced checkpoint procedure, the memory system 210 may avoid performing multiple enhanced checkpoint procedures back to back. To do so, the memory system 210 may use an indicator (e.g., a bit, a mode register bit) to track the enhanced checkpoint procedures (e.g., indicating that a set of regions has been maintained in the local memory 220 between checkpoint procedures). For example, the memory system 210 may set the indicator to a first value to indicate that a set of regions has been maintained in the local memory 220 between checkpoint procedures, and may set the indicator to a second value after flushing the set of regions to the non-volatile memory device 215. In some instances, the indicator may be referred to as an enhanced checkpoint bit. In some cases, the indicator may be multiple bits and may indicate more information. In such instances, the compressed region of the address mapping table 230 may be stored in the local memory 220 for more than one checkpoint procedure. For example, if the indicator is two bits, then the compressed region of the address mapping table 230 may be enabled to remain in the local memory 220 for up to four checkpoint procedures. The indicator may be any number of bits (e.g., one, two, three, four, five, six, seven, eight).

[0054] The compressed set of regions may remain in the local memory 220 until the second checkpoint procedure ends, at which time the set of regions may be flushed to the non-volatile memory device 215 (and the second set of regions associated with the second checkpoint procedure). In some instances, the second set of regions may include one or more regions (referred to as shared regions) in the set of regions associated with the enhanced checkpoint procedure. In such instances, the memory system 210 may prevent the shared regions from being transferred from the non-volatile memory device 215 to the local memory 220 for the second checkpoint procedure (e.g., because the shared regions are already in the local memory 220 and the versions in the non-volatile memory device 215 are outdated). In practice, the memory system 210 may update (e.g., after decompression) the shared regions that are already in the local memory 220. After updating the second set of regions associated with the second checkpoint procedure (which may include the shared regions associated with the enhanced checkpoint procedure), the memory system 210 may decompress (when appropriate) the regions in the local memory 220 and transfer the regions to the non-volatile memory device 215.

[0055] Thus, the memory system 210 may implement an enhanced checkpoint procedure in which a region of the address mapping table is compressed and maintained in the local memory 220 between the enhanced checkpoint procedure and a second subsequent checkpoint procedure.

[0056] Figure 3 An example of a process flow 300 for supporting compression-based address mapping management in a memory system according to an example disclosed herein is shown. The process flow 300 may be implemented by a memory system, for example, referring to Figure 1 and 2 The described memory system 110 or the memory system 210. Process flow 300 may illustrate the operation of a memory system implementing the enhanced checkpointing procedure described herein.

[0057] Aspects of process flow 300 may be implemented by a controller and other components. Additionally or alternatively, aspects of process flow 300 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a memory system). For example, the instructions, when executed by a controller (e.g., memory system controller 115, local controller 135), may cause the controller to perform operations of process flow 300.

[0058] At 305, data may be received. For example, the data may be received by a memory system (e.g., memory system 210) from a host system (e.g., host system 205) and may be associated with an access command (e.g., a write command, a read command). The data may be a first amount of data and may be associated with a first set of logical addresses. For example, if a write command is received, the memory system may also receive a logical address associated with the data to be stored in the memory system. The memory system may then store the data in a non-volatile memory device at a physical address of the non-volatile memory device of the memory system. The memory system may then create an entry in a change log table indicating a relationship between the logical address received as part of the write command and the physical address at which the data is stored.

[0059] At 310, it may be determined (e.g., by the memory system 210) that a condition for triggering a checkpoint procedure has been met. In some instances, the memory system 210 may determine that the condition has been met by determining that the size of the change log table 225 meets (e.g., is greater than or equal to) a threshold size. In other words, the address mapping table 230 may be updated based on the change log table 225 becoming full or almost full. In some instances, the memory system 210 may determine that the condition has been met by determining that the first amount of data meets (e.g., is greater than or equal to) a threshold amount. If the threshold has not been met, the memory system may continue to receive data (e.g., at 305). If the threshold has been met, the memory system may initiate a checkpoint procedure and move to 310.

[0060] At 315, it may be determined (e.g., by the memory system 210) whether the enhanced checkpoint indicator indicates whether the previous checkpoint procedure (e.g., immediately before the current checkpoint procedure) was an enhanced checkpoint procedure. If the indicator is set (e.g., the last checkpoint enhanced), then the compressed region of the address mapping table 230 is still stored in the local memory 220. If the indicator is not set, then the memory system may determine whether this checkpoint procedure will include compressing regions of the address mapping table 230 and maintaining those compressed portions in the local memory 220. If at 315, it is determined that the enhanced checkpoint indicator has a first value (e.g., is set), then the memory system 210 may proceed to 320 and associated procedures. If at 315, it is determined that the enhanced checkpoint indicator has a second value (e.g., is not set), then the memory system 210 may proceed to 345 and associated procedures.

[0061] At 320, the region of the address mapping table 230 stored in the local memory 220 may be decompressed based on the enhanced checkpoint indicator being set. If the enhanced checkpoint indicator is set, it indicates that the region of the address mapping table 230 stored in the local memory 220 will be transferred to the non-volatile memory device 215 and compression will not be attempted. Before transferring such information, the memory system 210 may update the relevant region of the address mapping table 230 associated with the checkpoint procedure. For example, an entry in the change log table 225 may be used to update the address mapping table 230. Decompressing the region of the address mapping table 230 stored in the local memory 220 may be suitable for facilitating the updating of the address mapping table 230.

[0062] At 325, a set of regions of the address mapping table 230 (e.g., L2P table) may be transferred (e.g., retrieved, extracted) from the non-volatile memory device 215 of the memory system 210 and loaded (e.g., written) into the local memory 220 of the memory system 210. In some cases, this step may not be performed. For example, if the change log table 225 indicates that all regions to be updated are already stored in the local memory 220. In some cases, the transfer of regions from the non-volatile memory device 215 to the local memory 220 may be performed before the function of 320, at least partially overlapped with the execution of the function of 320, after the function of 320, before the function of 330, at least partially overlapped with the execution of the function of 330, or any combination thereof. The transferred regions may be instances of regions that the change log table 225 indicates are to be updated as part of a checkpoint procedure.

[0063] At 330, the set of regions of the address mapping table 230 may be updated. For example, the memory system 210 may update the set of regions with physical address information of the entry from the change log table 225. The update may include associating the logical address in the address mapping table 230 with the physical address indicated in the change log table 225. The physical address information may refer to information indicating one or more physical addresses of the non-volatile memory device 215 of the memory system 210.

[0064] At 335, the region of the address mapping table 230 stored in the local memory 220 may be transferred from the local memory 220 to the non-volatile memory device 215. Transferring the address mapping table 230 may protect the address mapping table 230 from losing data in the event of an asynchronous power outage. For example, if an asynchronous power outage occurs, the information stored in the local memory 220 may be lost, but the information stored in the non-volatile memory device 215 may be maintained.

[0065] At 340, the enhanced checkpoint indicator may be updated. In the case where the region of the address mapping table 230 is transferred to the non-volatile memory device 215, the indicator is updated to a second value associated with indicating that compression may be attempted at the next checkpoint procedure. In the case where the region of the address mapping table 230 is compressed and stored in the local memory 220, the indicator is updated to a first value associated with indicating that compression will not be attempted at the next checkpoint procedure.

[0066] In the above description, the enhanced checkpoint indicator is a binary indicator. In some cases, the enhanced checkpoint indicator may be configured to indicate more information than two states. In such cases, the memory system 210 may be configured to attempt compression of the address mapping table 230 before transferring (e.g., refreshing) the address mapping table 230 stored in the local memory 220 to the non-volatile memory device 215 during multiple consecutive checkpoint procedures. In such cases, a single state of the enhanced checkpoint indicator may indicate that the compression will not be attempted at the next checkpoint procedure, and multiple states of the enhanced checkpoint indicator may indicate that compression may be attempted at the next checkpoint procedure.

[0067] In the event that it is determined at 315 that the enhanced checkpoint indicator has a second value (e.g., not set), the memory system 210 may proceed to 345 and its associated procedures. In such an event, the enhanced checkpoint indicator indicates that the local memory 220 does not contain a compressed version of the address mapping table 230, and that the region of the address mapping table 230 is to be transferred from the non-volatile memory device 215.

[0068] At 345, it may be determined whether the number of regions of the address mapping table 230 meets a threshold. The updated number of regions may be used to roughly estimate the scope of the address space being updated. If the scope of the address space being updated is relatively small (e.g., does not meet the threshold), the cost (e.g., latency, power consumption, processing time) of compressing the address mapping table 230 may exceed the benefits of implementing the subsequent checkpoint program. In such cases, the memory system 210 may not attempt compression, and may continue with a checkpoint program that is not based on compression. In such cases, the memory system 210 may proceed to 325, 330, 335, and 340 to complete the checkpoint program. However, if it is determined that the region of the address mapping table 230 meets the threshold, the memory system 210 may proceed to 350 and attempt to compress the region of the address mapping table 230.

[0069] At 350, a set of regions of the address mapping table 230 (e.g., L2P table) may be transferred (e.g., retrieved, extracted) from the non-volatile memory device 215 of the memory system 210 and loaded (e.g., written) into the local memory 220 of the memory system 210. In some cases, the transfer of the regions from the non-volatile memory device 215 to the local memory 220 may be performed before, at least partially overlapped with, after, or any combination of the functions of 355. The transferred regions may be instances of regions that the change log table 225 indicates are to be updated as part of a checkpoint procedure.

[0070] At 355, the set of regions of the address mapping table 230 may be updated. For example, the memory system 210 may update the set of regions with physical address information of the entry from the change log table 225. The update may include associating the logical address in the address mapping table 230 with the physical address indicated in the change log table 225. The physical address information may refer to information indicating one or more physical addresses of the non-volatile memory device 215 of the memory system 210.

[0071] At 360, a region of the address mapping table 230 may be compressed (e.g., by the memory system 210). For example, a first set of regions may be compressed from a first size to a second size according to a compression factor. The first set of regions may be compressed based on an enhanced checkpoint indicator indicating that a previous checkpoint procedure was an unenhanced checkpoint procedure or an enhanced checkpoint indicator indicating that subsequent checkpoints may continue to be compressed. Compressing a region may include modifying a region so that information in the region is of a smaller size (e.g., occupies less memory space). In some examples, the memory system 210 may compress a region by removing some entries of consecutively indexed logical addresses that map to consecutively indexed physical addresses. In response to the consecutively indexed logical addresses being mapped to consecutively indexed physical addresses, some entries in the address mapping table 230 may be replaced with an indicator of a starting logical address in a consecutively indexed set, a starting physical address of the consecutively indexed set, and a length of the consecutively indexed set. In this way, a logical to physical address mapping may be stored in the local memory 220 using less memory without losing information about the mapping. However, such compression may make it challenging to update such mappings. Thus, in some cases, if the mapping is to be updated, it may be decompressed first. Other examples of compression are also possible. In other examples, the memory system 210 may compress region n by removing entries from physical addresses 513 to 515 and removing entries from physical addresses 601 to 603. Such information may instead be an indication of a number of consecutive mappings of addresses (e.g., sequential logical addresses mapped to sequential physical addresses).

[0072] At 365, it may be determined whether the compression factor of the compression of the address mapping table meets a threshold. If the compression factor fails to meet the threshold, the address mapping may be decompressed (at 370) and the region transferred to the non-volatile memory device 215 (at 335). In such cases, the cost of compressing and storing the data in the local memory 220 may not justify the benefit of a faster invocation at the next checkpoint procedure. However, if the compression factor does meet the threshold, the memory system 210 may proceed to 375 and maintain the compressed region of the address mapping table 230 stored in the local memory 220 until after the next checkpoint procedure. After determining to maintain the compressed region in the local memory 220, the memory system 210 may update the enhanced checkpoint indicator at 340 and continue the process. In some instances, the threshold for the compression factor is two (2). In such instances, the memory system 210 may flush the address mapping table 230 from the local memory 220 to the non-volatile memory device 215 unless the region of the address mapping table 230 is compressed to equal to or less than 50% of the original information size. Examples of compression thresholds may include compression factors of 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 4.0, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8, 4.9, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, and 8.0.

[0073] At 375, the compressed region may be stored in local memory 220 for use by the next checkpoint procedure. In some examples, the compressed region of address mapping table 230 may be stored in a merge buffer of local memory 220. The merge buffer may be a portion of local memory dedicated to updating a region of address mapping table 230 using change log table 225 as part of a checkpoint procedure.

[0074] In some alternative examples, it may be predicted whether a compression factor of a region of the address mapping table 230 stored in the local memory 220 may be compressed to a compression factor that satisfies a threshold. In such cases, the memory system 210 may perform a process of predicting whether the compression factor is likely to meet the threshold, rather than compressing the region (at 360) and then comparing the compression factor of the compressed region to the threshold. If the predicted value will meet the threshold, the memory system 210 may proceed with the compression. However, if the predicted value fails to meet the threshold, the memory system 210 may proceed to transfer the region from the local memory 220 to the non-volatile memory device 215 without compressing the data (e.g., at 335).

[0075] Such compression techniques may be configured to reduce the number of transfers of the address mapping table 230 between the non-volatile memory device 215 and the local memory 220, which may improve latency and power consumption, among other benefits. In addition, such techniques may improve latency of access operations over a wider range of addressing spaces (e.g., over a wider range of host data being accessed). Alternative examples of the foregoing may be implemented, in which some operations are performed in an order different from the order described, in parallel, or not performed at all. In some cases, the operations may include additional features not mentioned herein, or other operations may be added. In addition, certain operations may be performed multiple times, or certain combinations of operations may be repeated or looped.

[0076] Figure 4 A block diagram 400 is shown of a memory system 420 that supports compression-based address mapping management in a memory system according to examples disclosed herein. The memory system 420 may be a reference Figures 1 to 3 4. The memory system 420 or its various components may be examples of means for performing various aspects of compression-based address mapping management in the memory system described herein. For example, the memory system 420 may include a mapping component 425, a merging component 430, a compression component 435, a communication component 440, a decompression component 445, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0077] The mapping component 425 may be configured as or otherwise support means for transferring a region of an address map associated with a first amount of data received from a host system from a non-volatile memory to a local memory. The merging component 430 may be configured as or otherwise support means for updating a region of an address map with physical address information of the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data. The compression component 435 may be configured as or otherwise support means for compressing a region of an address map in a local memory based at least in part on updating the region. In some instances, the mapping component 425 may be configured as or otherwise support means for modifying a bit value to indicate that the transfer of the region to the non-volatile memory will be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

[0078] In some examples, compression component 435 may be configured or otherwise support means for determining that a region transferred to local memory contains more than a threshold number of regions, wherein the region is compressed based at least in part on the region containing more than the threshold number of regions.

[0079] In some examples, communication component 440 may be configured or otherwise support means for receiving a second amount of data from a host system. In some examples, merge component 430 may be configured or otherwise support means for updating one or more of the regions based at least in part on the second amount of data.

[0080] In some examples, communication component 440 can be configured or otherwise support means for transferring regions to non-volatile memory based at least in part on updating the one or more regions.

[0081] In some examples, decompression component 445 may be configured or otherwise support means for decompressing a region in local memory, wherein the region is transferred to non-volatile memory based at least in part on decompressing the region.

[0082] In some examples, the decompression component 445 may be configured as or otherwise support means for decompressing the one or more regions based at least in part on the one or more regions being associated with a second amount of data, wherein the one or more regions are updated based at least in part on decompressing the one or more regions.

[0083] In some examples, communication component 440 may be configured or otherwise support means for transferring an additional region of the address map associated with the second amount of data from the nonvolatile memory to the local memory, wherein the region is transferred to the nonvolatile memory after the additional region is transferred to the local memory.

[0084] In some examples, communication component 440 can be configured or otherwise support means for determining that a condition has been met to transfer an additional region, wherein the region is transferred based at least in part on determining that the condition has been met.

[0085] In some examples, communication component 440 can be configured or otherwise support means for determining that a first amount of data satisfies a threshold amount, wherein the region is communicated based at least in part on determining that the first amount of data satisfies the threshold amount.

[0086] In some examples, compression component 435 can be configured or otherwise support means for determining that a size of a change log satisfies a threshold size, wherein a region is transferred based at least in part on determining that the size of the change log satisfies the threshold size.

[0087] In some examples, the bit value includes a flag indicating whether the region of the address map is to be compressed.

[0088] Figure 5A flowchart according to an example disclosed herein is shown, illustrating a method 500 for supporting compression-based address mapping management in a memory system. The operations of the method 500 may be implemented by the memory system or components thereof described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4 The described memory system performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the wireless memory system may use dedicated hardware to perform various aspects of the described functions.

[0089] At 505, the method may include transferring a region of an address map associated with a first amount of data received from a host system from a non-volatile memory to a local memory. Operation 505 may be performed according to examples disclosed herein. In some examples, aspects of operation 505 may be described with reference to Figure 4 The described mapping component 425 performs.

[0090] At 510, the method may include: updating a region of the address map with physical address information of the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data. Operation 510 may be performed according to examples disclosed herein. In some examples, aspects of operation 510 may be implemented by reference to Figure 4 The described merge component 430 performs.

[0091] At 515, the method may include: compressing the region of the address map in the local memory based at least in part on the update region. Operation 515 may be performed according to examples disclosed herein. In some examples, aspects of operation 515 may be described by reference to Figure 4 The described compression component 435 performs.

[0092] At 520, the method may include: modifying the bit value to indicate that the transfer of the region to the non-volatile memory will be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by the threshold factor. Operation 520 may be performed according to examples disclosed herein. In some examples, aspects of operation 520 may be described with reference to Figure 4 The described mapping component 425 performs.

[0093] In some examples, the apparatus described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0094] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transferring a region of an address map associated with a first amount of data received from a host system from a non-volatile memory to a local memory; updating the region of the address map with physical address information of the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compressing the region of the address map in the local memory based at least in part on updating the region; and modifying a bit value to indicate that transfer of the region to the non-volatile memory will be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

[0095] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that the region transferred to the local memory contains more than a threshold number of regions, wherein the region is compressed at least in part based on the region containing more than the threshold number of regions.

[0096] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 2, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a second amount of data from the host system, and updating one or more of the regions based at least in part on the second amount of data.

[0097] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of Aspect 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transferring the region to the non-volatile memory based at least in part on updating the one or more regions.

[0098] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 3 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: decompressing the area in the local memory, wherein the area is transferred to the non-volatile memory based at least in part on decompressing the area.

[0099] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 3 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: decompressing the one or more regions based at least in part on the one or more regions being associated with the second amount of data, wherein the one or more regions are updated based at least in part on the decompression of the one or more regions.

[0100] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 3 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transferring an additional area of ​​the address mapping associated with the second amount of data from the non-volatile memory to the local memory, wherein the area is transferred to the non-volatile memory after the additional area is transferred to the local memory.

[0101] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of Aspect 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that a condition for transferring the additional region has been met, wherein the region is transferred at least in part based on determining that the condition has been met.

[0102] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that the first amount of data satisfies a threshold amount, wherein the area is passed at least in part based on determining that the first amount of data satisfies the threshold amount.

[0103] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: determining that the size of the change log satisfies a threshold size, wherein the area is transferred at least in part based on determining that the size of the change log satisfies the threshold size.

[0104] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 10, wherein the bit value comprises a flag indicating whether the region of the address map is to be compressed.

[0105] It should be noted that the techniques described include possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, portions from two or more of the described methods may be combined.

[0106] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0107] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are electronically connected to each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupled" (e.g., "electrically coupled") may refer to a condition of moving from an open circuit relationship between components, in which signals are currently unable to be transmitted between components via conductive paths, to a closed circuit relationship between components, in which signals are able to be transmitted between components via conductive paths. If a component, such as a controller, couples other components together, then the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0109] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If there is a break between the components, then they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller implements the following change: the signal is prevented from flowing between the components using the conductive path that previously permitted the signal to flow.

[0110] The terms "if", "when", "based on", or "based at least in part on" are used interchangeably. In some instances, if the terms "if", "when", "based on", or "based at least in part on" are used to describe a conditional action, a conditional process, or a connection between process parts, then these terms are interchangeable.

[0111] The term "in response to" may refer to a condition or action that occurs at least in part (if not entirely) as a result of a prior condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0112] In addition, the term "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of a previous condition or action, so that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition and performed may be performed in addition or alternatively (e.g., in an alternative instance) "directly in response to" or "directly in response to" such other conditions or actions.

[0113] The devices including memory arrays discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0114] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0115] The descriptions set forth herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferable" or "advantageous" over other examples. The detailed description includes specific details in order to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid confusing the concepts of the described examples.

[0116] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0117] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0118] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0119] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be understood as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0120] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that helps to transfer a computer program from one place to another. Non-transitory storage media can be any available media, which can be accessed by a general or special computer. For example and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. And, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these items are also included within the scope of computer-readable media.

[0121] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a controller associated with the memory device, wherein the controller is configured to cause the apparatus to: transferring a region of the address map associated with a first amount of data received from the host system from the non-volatile memory to the local memory; updating the region of the address map with physical address information for the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compressing the region of the address map in the local memory based at least in part on updating the region; as well as A bit value is modified to indicate that transfer of the region to the non-volatile memory is to be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

2. The device of claim 1, wherein the controller is further configured to cause the device to: A determination is made that the region transferred to the local memory includes more than a threshold number of regions, wherein the region is compressed based at least in part on the region including more than the threshold number of regions.

3. The device of claim 1, wherein the controller is further configured to cause the device to: receiving a second amount of data from the host system; and One or more of the regions are updated based at least in part on the second amount of data.

4. The device of claim 3, wherein the controller is further configured to cause the device to: Based at least in part on updating the one or more regions, transferring the regions to the non-volatile memory.

5. The device of claim 3, wherein the controller is further configured to cause the device to: The region in the local memory is decompressed, wherein the region is transferred to the non-volatile memory based at least in part on decompressing the region.

6. The device of claim 3, wherein the controller is further configured to cause the device to: Based at least in part on the one or more regions being associated with the second amount of data, the one or more regions are decompressed, wherein the one or more regions are updated based at least in part on decompressing the one or more regions.

7. The device of claim 3, wherein the controller is further configured to cause the device to: An additional region of the address map associated with the second amount of data is transferred from the nonvolatile memory to the local memory, wherein the region is transferred to the nonvolatile memory after the additional region is transferred to the local memory.

8. The device of claim 7, wherein the controller is further configured to cause the device to: A determination is made that a condition for delivering the additional region has been met, wherein delivering the region is based at least in part on determining that the condition has been met.

9. The device of claim 1, wherein the controller is further configured to cause the device to: A determination is made that the first amount of data satisfies a threshold amount, wherein the region is passed based at least in part on the determination that the first amount of data satisfies the threshold amount.

10. The device of claim 1, wherein the controller is further configured to cause the device to: A determination is made that a size of the change log satisfies a threshold size, wherein the region is transferred based at least in part on determining that the size of the change log satisfies the threshold size.

11. The apparatus of claim 1, wherein the bit value comprises a flag indicating whether the region of the address map is to be compressed.

12. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: transferring a region of the address map associated with a first amount of data received from the host system from the non-volatile memory to the local memory; updating the region of the address map with physical address information for the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compressing the region of the address map in the local memory based at least in part on updating the region; as well as A bit value is modified to indicate that transfer of the region to the non-volatile memory is to be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the processor to: A determination is made that the region transferred to the local memory includes more than a threshold number of regions, wherein the region is compressed based at least in part on the region including more than the threshold number of regions.

14. The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the processor to: receiving a second amount of data from the host system; and One or more of the regions are updated based at least in part on the second amount of data.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processor to: Based at least in part on updating the one or more regions, transferring the regions to the non-volatile memory.

16. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processor to: The region in the local memory is decompressed, wherein the region is transferred to the non-volatile memory based at least in part on decompressing the region.

17. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processor to: Based at least in part on the one or more regions being associated with the second amount of data, the one or more regions are decompressed, wherein the one or more regions are updated based at least in part on decompressing the one or more regions.

18. The non-transitory computer-readable medium of claim 14, wherein the instructions are further executable by the processor to: An additional region of the address map associated with the second amount of data is transferred from the nonvolatile memory to the local memory, wherein the region is transferred to the nonvolatile memory after the additional region is transferred to the local memory.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions are further executable by the processor to: A determination is made that a condition for delivering the additional region has been met, wherein delivering the region is based at least in part on determining that the condition has been met.

20. A method comprising: transferring a region of the address map associated with a first amount of data received from the host system from the non-volatile memory to the local memory; updating the region of the address map with physical address information for the first amount of data based at least in part on a change log indicating physical addresses associated with the first amount of data; compressing the region of the address map in the local memory based at least in part on updating the region; as well as A bit value is modified to indicate that transfer of the region to the non-volatile memory is to be delayed until at least one of the regions is updated again, wherein the bit value is modified based at least in part on the region being compressed by a threshold factor.

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