Multi-communication driving circuit based on FPGA

Abstract

The invention discloses a multi-communication driving circuit based on an FPGA (Field Programmable Gate Array). The multi-communication driving circuit comprises a communication driving circuit and an FPGA communication circuit, the communication drive circuit comprises a CAN line drive circuit, a LINE line drive circuit and a serial port drive circuit. The CAN line driving circuit and the LINE line driving circuit are respectively connected with the FPGA communication circuit and transmit data of the OBD interface to the FPGA communication circuit; and the FPGA communication circuit converts the received protocol, processes data, forwards the data to the MCU through the serial port driving circuit, receives an instruction sent by the MCU through a serial port, selects different protocols for communication, and realizes different protocol communication. According to the invention, flexible conversion and circuit driving of multiple communication protocol modes are realized.

Description

Technical Field

[0001] The invention relates to the field of automobile fault diagnosis, and in particular to a multi-communication driving circuit based on FPGA. Background Art

[0002] The electronic systems of modern cars are becoming more and more complex, covering a wide range of areas from engine management, ABS, body control to infotainment systems. These systems usually use various communication protocols to achieve effective data exchange between internal and external devices. In this process, the role of the automobile fault diagnosis system is particularly important. It can monitor and analyze the operating status of various electronic components of the car in real time, detect and diagnose potential faults in a timely manner, thereby improving the safety, reliability and maintenance efficiency of the vehicle.

[0003] At present, automobile fault diagnosis systems mainly rely on standard diagnostic communication protocols, such as CAN (Controller Area Network), LIN (Local Interconnect Network) and serial communication (RS232 or RS485). These communication protocols provide standards for data exchange between various control modules inside the car, but there are differences between different protocols in terms of transmission methods, signal characteristics, etc. In order to achieve interconnection between multiple protocols, automobile fault diagnosis systems often need to rely on specialized hardware circuits or middleware for protocol conversion and signal driving. This increases the design complexity of the system and may affect the diagnostic efficiency.

[0004] Therefore, there is an urgent need to achieve rapid conversion between multiple communication protocols and directly drive different types of communication lines so as to improve the flexibility and adaptability of the automobile fault diagnosis system. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a multi-communication driving circuit based on FPGA, which can realize the interconnection and intercommunication of different communication protocols in automobile fault diagnosis, and convert the OBD interface data into serial communication mode and transmit it to MCU through the FPGA communication circuit, thereby improving the fault diagnosis efficiency.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions: A FPGA-based multi-communication drive circuit includes a communication drive circuit and an FPGA communication circuit; the communication drive circuit includes a CAN line drive circuit, a LINE line drive circuit and a serial port drive circuit; the CAN line drive circuit and the LINE line drive circuit are respectively connected to the FPGA communication circuit to transmit the data of the OBD interface to the FPGA communication circuit; The FPGA communication circuit converts the received protocol and processes the data, forwards the data to the MCU through the serial port driver circuit, and also receives the instructions sent by the MCU through the serial port, selects the CAN line driver circuit or the LINE line driver circuit to communicate to realize different protocol communications.

[0007] A further technical solution is that the FPGA communication circuit includes an FPGA chip and a communication control module inside the FPGA chip; the communication control module multiplexes the outputs of multiple pins of the FPGA, selects different signal paths and controls the status of the communication protocol to achieve control of bus communication.

[0008] A further technical solution is that the FPGA chip includes a LINE0 serial port receiving pin, a LINE0 serial port sending pin, a CAN1 serial port receiving pin, a CAN1 serial port sending pin, a LINE1 serial port receiving pin, a LINE1 serial port sending pin, an MCU serial port 5 sending pin, an MCU serial port 5 receiving pin, a CAN0 serial port receiving pin, a CAN0 serial port sending pin and a GPIO pin; the MCU serial port 5 sending pin communicates with the receiving MCU serial port, receives commands, and performs logic switching according to the received commands; the MCU serial port 5 receiving pin communicates with the MCU serial port, returns commands, and returns parameters after executing the commands; the LINE0 serial port receiving pin, the LINE0 serial port sending pin, the LINE1 serial port receiving pin and the LINE1 serial port sending pin are connected to the LINE line driving circuit for LINE line communication; the CAN1 serial port receiving pin, the CAN1 serial port sending pin, the CAN0 serial port receiving pin and the CAN0 serial port sending pin are connected to the CAN line driving circuit to realize CAN line communication; The communication control module includes a first register, a second register and a pin output control register arranged inside the FPGA chip; the first register and the second register have different addresses, and the first register and the second register are used to store control information sent by the MCU, and the information is used to configure the pin output control register, thereby controlling the pin state of the FPGA chip to realize CAN line communication or LINE line communication. By controlling the high and low levels of the CAN0 pin and the CAN1 pin on the FPGA chip, different communication modes are selected, and the output of the LINE0 pin and the LINE1 pin on the FPGA chip is controlled by adjusting the high four bits and the fourth bit of the second register.

[0009] A further technical solution is to control the high and low levels of the CAN0 pin and the CAN1 pin on the FPGA chip through the first register to select different communication modes, specifically: The address of the first register is 0x03, the reset value is 0x00, and the 7th, 6th and 3rd bits of the register are reserved; the 5th and 4th bits are set to CAN1_PHY_SEL[1:0], and different CAN transceivers are selected by setting the parameters of the 5th and 4th bits, thereby controlling the CAN1 pin on the FPGA chip to output high or low, and connecting with the CAN line drive circuit to realize CAN line communication; the 2nd, 1st and 0th bits of the first register are set to CAN0_PHY_SEL[2:0], and the values ​​of these three bits are set to configure the CAN0 pin on the FPGA chip to output high or low; The output of the LINE0 pin and the LINE1 pin on the FPGA chip are controlled by the difference between the high four bits and the fourth bit of the second register, specifically: The address of the second register is 0x04, the reset value is 0x00, the high bits 7, 6, 5, and 4 of the register are set to LINE_RX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE receive signal pin on the FPGA chip by setting the difference of these four bits to realize the communication of the LINE line; the low bits 3, 2, 1, and 0 of the second register are set to LINE_TX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE send signal pin on the FPGA chip by setting the difference of these four bits to realize the communication of the LINE line.

[0010] A further technical solution is that the CAN line driving circuit includes a CAN line initial level driving circuit, a CAN line sending driving circuit and a CAN line serial port conversion receiving driving circuit. The CAN line initial level driving circuit controls the level of the CAN bus to be in an idle state. The CAN line sending driving circuit transmits the data sent by the FPGA through the CAN bus. The CAN line serial port conversion receiving driving circuit converts the received CAN data into a serial port signal and transmits it to the MCU through the FPGA communication circuit.

[0011] A further technical solution is that the CAN line initial level driving circuit includes an analog switch chip U14, and the pins on the analog switch chip U14 adjust CAN_H and CAN_L by receiving control signals from the FPGA chip, providing an initial level state for the CAN line sending driving circuit to ensure that there is no misoperation during the communication process; The analog switch chip U14 includes a first input pin IN1, a second input pin IN2, a third input pin IN3, a fourth input pin IN4, a first control pin D1, a second control pin D2, a third control pin D3, a fourth control pin D4, a first output pin S1, a second output pin S2, a third output pin S3, a fourth output pin S4, a pin V-, a pin GND, a pin V+ and a pin VL; the first input pin IN1, the second input pin IN2, the third input pin IN3, and the fourth input pin IN4 are respectively connected to the first 24VCAN uplink level driving pin, the second 24VCAN uplink level driving pin, the second 24VCAN downlink level driving pin and the first 24VCAN downlink level control pin, and the first control pin D1 is connected to the first 24VCAN uplink level driving pin through a resistor R133. The cathode of the diode D15 is connected; the second control pin D2 is connected to the cathode of the diode D15 through the resistor R134, and the anode of the diode D15 is connected to the VCC_IN power input terminal; the third control pin D3 and the fourth control pin D4 are respectively connected to the resistor R138 and the resistor R139 and then grounded; the first output pin S1 and the fourth output pin S4 are respectively connected to the CAN1_H pin of the CAN line sending drive circuit; the second output pin S2 and the third output pin S3 are respectively connected to the CAN1_L pin of the CAN line sending drive circuit; the pin V- and the pin GND are grounded; the pin V+ and the pin VL are respectively connected to the VCC_IN terminal and the VCC_5V power supply, and at the same time, the VCC_IN power supply terminal and the VCC_5V power supply terminal are connected to the ground through the capacitor C114 and the capacitor C115.

[0012] A further technical solution is that the CAN line sending drive circuit drives CAN_H / CAN_L to form a differential level circuit to send data to the receiving drive circuit of the CAN line serial port conversion; the CAN line sending drive circuit includes MOSFET tube Q4, MOSFET tube Q3 and MOSFET tube Q5; the gate of the MOSFET tube Q4 is connected to the 24VCAN_UP0 pin of the FPGA chip through a resistor R135, the C112 capacitor is connected in parallel with the resistor R135, and the gate of the MOSFET tube Q4 is connected to the pull-down resistor R136 and then grounded; the source of the MOSFET tube Q4 is grounded; the drain of the MOSFET tube Q4 is connected to the gate of the high-side driving part MOSFET tube Q3 through a current limiting resistor R132; the gate of the MOSFET tube Q3 is connected to the power supply VCC_IN through a resistor R131, and the power supply VCC_IN is connected to the ground through the C111 capacitor. The diode D14 is connected in parallel with the resistor R131; the source of the MOSFET tube Q3 is connected to the power supply VCC_IN; the drain of Q3 is connected in series with the diode D16 and the resistor R137 to form the CAN1_H signal output terminal; In the CAN_L part, the gate of the MOSFET tube Q5 is connected to the 24VCAN_PD0 pin of the FPGA chip through the current limiting resistor R141, which is used to receive the digital logic signal transmitted from the FPGA chip. The resistor R141 is connected in parallel with the capacitor C113, and the gate of the MOSFET tube Q5 is grounded through the pull-down resistor R142 to ensure signal stability; the capacitor C113 is connected in parallel with the resistor R141 to filter out high-frequency noise and improve signal stability. The source of the MOSFET tube Q5 is grounded, and the drain of the MOSFET tube Q5 is connected to the current limiting resistor R140 to form the CAN_L output terminal. When the 24VCAN_PD0 pin changes from low to high, the MOSFET tube Q5 is turned on, and the drain voltage of Q5 is pulled down, driving the CAN_L signal line to output a low level.

[0013] A further technical solution is that the receiving drive circuit of the CAN line conversion serial port includes a CAN transceiver chip U16 and a switch chip J16, and the CAN transceiver chip U16 includes pins TXD, RXD, CANH, CANL, VSS, S, VDD, and VIO; pins TXD and RXD are respectively connected to pins CAN1_TXD and CAN1_RXD of the FPGA chip, pin CAN1_TXD is used to receive digital signals from the FPGA chip, and pin CAN1_RXD is used to send digital signals on the CAN bus. ; Pin CANH and pin CANL are respectively connected to the CAN1_H and CAN1_L differential signals of the CAN line transmission drive circuit, pin CANH is connected to one end of capacitor C125, pin CANL is connected to one end of capacitor C124, and the other end of capacitor C124 is connected to the other end of capacitor C125 and then grounded; pin VSS and pin S are both grounded; pin VDD is connected to the VCC_5V power supply, and at the same time connected to capacitor C122 and then grounded to ensure stable power supply; VIO pin is connected to a 3.3V power supply to match the logic level of the MCU, and at the same time connected to capacitor C123 and then grounded to bypass clutter; Pin 2 of the switch chip J16 is designed as CAN120_SW1 to transmit CAN signals corresponding to different channels; Pin 1 of the J16 chip is connected to a 3.3V power supply, and pins 3 and 4 are connected to the CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit through matching resistors R145 and R146 respectively, and pin 3 is connected to capacitor C121 and then grounded.

[0014] According to a further technical solution, the FPGA chip model is GW1N-4K-LQFP100.

[0015] In a further technical solution, the model of the analog switch chip U14 is DG445 / SGM4512. The resistance values ​​of R133 and R139 are 1.8K, and the resistance values ​​of R134 and R138 are 910 ohms.

[0016] According to a further technical solution, the model of the MOSFET tube Q4 is 2N7002, the model of the MOSFET tube Q3 is LP2309LT1G, the model of the MOSFET tube Q5 is CJ2310, the resistance values ​​of R138 and R134 are 910 ohms, and the resistance values ​​of R137 and R140 are 220 ohms.

[0017] According to a further technical solution, the CAN transceiver chip U16 has a chip model of MCP2558FD-H / SN.

[0018] The FPGA communication circuit of the present invention performs data processing and protocol control with the MCU, and the CAN line driving circuit is responsible for converting these data into physical signals of the CAN bus and sending the data to the bus. The two work together to achieve efficient communication between the FPGA and the MCU through signal control and timing coordination control. Timing coordination means that the FPGA first receives the command from the MCU, and then controls the CAN or LINE communication. When no communication instruction is received from the MCU, the CAN communication is stabilized in a ready-to-send state by the CAN initial level driving circuit. The FPGA communication circuit includes a port design for the FPGA chip to connect to the MCU, and the FPGA chip converts the CAN protocol and LINE protocol data into a serial port and sends it to the MCU port. After the connection between the FPGA chip and the MCU is established, the driving function is determined by the MCU. By using the FPGA chip pin multiplexing output, according to the instruction, the function of the MCU interface is multiplexed to the FPGAIO pin to realize the multiplexing function or realize the logical function. Beneficial Effects Compared with the prior art, the present invention has the following significant advantages:

[0019] 1. The present invention uses an FPGA circuit to convert and transmit the OBD interface data to the MCU port. Only one driving circuit is required to realize multi-mode, multi-protocol and multi-channel communication, which greatly improves the convenience and flexibility of diagnosis.

[0020] 2. The present invention sets a reasonable initial level through the CAN line initial level driving circuit, which can prevent bus noise and unstable levels from causing data errors or false triggering, and ensure that the CAN bus is in a stable state when idle, thereby improving the stability and anti-interference ability of the entire communication system.

[0021] 3. The CAN line transmission drive circuit in the present invention can ensure fast and stable data transmission under high-frequency switching conditions by using an efficient transmission drive circuit, reduce signal reflection and loss, and reduce power consumption.

[0022] 4. The CAN line to serial port drive circuit of the present invention enables the CAN bus device to be interconnected and exchange data with the serial port communication device through effective signal conversion, thereby improving the flexibility and applicability of the system.

[0023] 5. The present invention sets two 8-bit registers and adjusts different communication parameters of the registers to enable free switching of CAN lines and LINE lines. The receiving and sending mode is flexible and efficient, and is suitable for multi-channel communication driving. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 This is the circuit diagram of the FPGA chip; Figure 3 This is the CAN line initial level driving circuit diagram; Figure 4 (a) is a CAN_H circuit diagram of the CAN line transmission drive circuit diagram; Figure 4 (b) is the CAN_L circuit diagram of the CAN line transmission drive circuit diagram; Figure 5 This is the CAN line level logic diagram; Figure 6 This is the CAN line to serial port driver diagram. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Example

[0026] like Figure 1-5 As shown in the figure, the FPGA chip receives information from the vehicle OBD port by controlling the receiving circuit on the CAN bus interface. This information is transmitted through the CAN protocol, and the FPGA can perform further data processing, analysis or storage after decoding. The FPGA chip converts the CAN bus data into serial port signals as needed, or exchanges data with other modules through the LINE bus when necessary. The system needs to transmit data to an external device (such as a PC or diagnostic tool) through the serial port. The FPGA will process the CAN signal and send the data out according to the serial communication protocol. At this time, the role of the serial port is to provide a low-speed communication channel for the system for configuration, diagnosis or data recording.

[0027] A multi-communication drive circuit based on FPGA, comprising a communication drive circuit and an FPGA communication circuit; the communication drive circuit comprises a CAN line drive circuit, a LINE line drive circuit and a serial port drive circuit; the CAN line drive circuit and the LINE line drive circuit are respectively connected to the FPGA communication circuit to transmit the data of the OBD interface to the FPGA communication circuit; The FPGA communication circuit converts the received protocol and processes the data, forwards the data to the MCU through the serial port driver circuit, and also receives the instructions sent by the MCU through the serial port, selects different protocols for communication, and realizes different protocol communications; The FPGA communication circuit includes an FPGA chip and a communication control module inside the FPGA chip; the communication control module multiplexes the outputs of multiple pins of the FPGA, selects different signal paths and controls the state of the communication protocol to achieve control of bus communication.

[0028] The FPGA chip model is GW1N-4K-LQFP100, and the FPGA chip includes LINE0 serial port receiving pin PZ07_LINE0_RXD, LINE0 serial port sending pin PZ06_LINE0_TXD, CAN1 serial port receiving pin PZ05_CAN1_RXD, CAN1 serial port sending pin PZ04_CAN1_TXD, LINE1 serial port receiving pin PZ03_LINE1_RXD, LINE1 serial port sending pin PZ02_LINE1_TXD, MCU serial port 5 sending pin PB8_UART5_TXD, MCU serial port 5 receiving pin PB9_UART5_RXD, CAN0 serial port receiving pin PC10_CAN0_RXD, CAN0 serial port sending pin PC09_CAN N0_TXD and GPIO pin PY5_FPGA_GPIO; the MCU serial port 5 sending pin communicates with the receiving MCU serial port, receives commands, and performs logic switching according to the received commands; the MCU serial port 5 receiving pin communicates with the MCU serial port, returns commands, and returns parameters after executing the commands; the LINE0 serial port receiving pin, LINE0 serial port sending pin, LINE1 serial port receiving pin and LINE1 serial port sending pin are connected to the LINE line driving circuit for LINE line communication; the CAN1 serial port receiving pin, CAN1 serial port sending pin, CAN0 serial port receiving pin and CAN0 serial port sending pin are connected to the CAN line driving circuit to realize CAN line communication; the FPGA chip also includes other pins, which are not involved in this patent and will not be described in detail.

[0029] The communication control module includes a first register, a second register and a pin output control register arranged inside the FPGA chip; The addresses of the first register and the second register are different. The first register and the second register are used to store the control information sent by the MCU. This information is used to configure the pin output control register, and then control the pin state of the FPGA chip to achieve CAN line communication or LINE line communication. The high and low levels of the CAN0 pin and the CAN1 pin on the FPGA chip are controlled by the first register to select different communication modes, specifically: The address of the first register is 0x03, the reset value is 0x00, and the 7th, 6th and 3rd bits of the register are reserved; the 5th and 4th bits are set to CAN1_PHY_SEL[1:0], and different CAN transceivers (including fault-tolerant CAN transceivers, CANFD0 transceivers, etc.) are selected by setting the parameters of the 5th and 4th bits, thereby controlling the CAN1 pin on the FPGA chip to output high or low, and connecting with the CAN line drive circuit to realize CAN line communication; the 2nd, 1st and 0th bits of the first register are set to CAN0_PHY_SEL[2:0], and the CAN0 pin on the FPGA chip is configured to output high or low by setting the values ​​of these three bits; The specific settings of the 5th and 4th bits of the first register are: 10: select the 24V CAN transceiver E6 pin; 01: select the CAN FD1 transceiver E6 pin; 00: do not select the CAN transceiver. The specific settings of the 2nd, 1st, and 0th bits are: 100: select the fault-tolerant CAN transceiver 2 (LINE0LINE1 simulation); 011: single-line CAN transceiver LINE0; 010: select the fault-tolerant CAN transceiver 1 (fault-tolerant CAN dedicated chip); 001: select the CAN FD0 transceiver LINE01; 000: do not select the CAN transceiver.

[0030] The output of the LINE0 pin and the LINE1 pin on the FPGA chip are controlled by the difference between the high four bits and the fourth bit of the second register, specifically: The address of the second register is 0x04, the reset value is 0x00, the high bits 7, 6, 5, and 4 of the register are set to LINE_RX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE receive signal pin on the FPGA chip by setting the difference of these four bits to realize the communication of the LINE line; the low bits 3, 2, 1, and 0 of the second register are set to LINE_TX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE send signal pin on the FPGA chip by setting the difference of these four bits to realize the communication of the LINE line.

[0031] The 7th, 6th, 5th and 4th high four bits LINE_RX_SEL[3:0] of the second register are specifically set to: 1011: LINE_DIFF_RXD positive phase; 1010: LINE_DIFF_RXD positive phase; 1001: select industrial CAN transceiver (National Five free from disassembly); 1000: LINE0_RXD, LINE1_RXD differential inversion; 0111: LINE0_RXD, LINE1_RXD differential positive phase; 0110: LINE01_RXD inversion; 0101: LINE01_RXD positive phase; 0100: LINE1_RXD inversion; 0011: LINE1_RXD positive phase; 0010: LINE0_RXD inversion; 0001: LINE0_RXD positive phase; 0000: not selected. The 3rd, 2nd, 1st, and 0th low four bits of the LINE_TX_SEL[3:0] parameters are specifically set as follows: 1001: Select industrial CAN transceiver (national five free disassembly); 1000: LINE0, LINE1 differential, LINE1 positive phase, LINE0 negative phase; 0111: LINE0, LINE1 differential, LINE0 positive phase, LINE1 negative phase; 0110: LINE0 negative phase, LINE1 negative phase; 0101: LINE0 positive phase, LINE1 positive phase; 0100: LINE1 negative phase, LINE0 floating; 0011: LINE1 positive phase, LINE0 floating; 0010: LINE0 negative phase, LINE1 floating; 0001: LINE0 positive phase, LINE1 floating; 0000: LINE0 floating, LINE1 floating. Single-line CAN and LINEPHY cannot be selected at the same time in the register setting.

[0032] The CAN line driving circuit includes a CAN line initial level driving circuit, a CAN line sending driving circuit and a CAN line serial port conversion receiving driving circuit. The CAN line initial level driving circuit controls the level of the CAN bus to be in an idle state. The CAN line sending driving circuit transmits the data sent by the FPGA through the CAN bus. The CAN line serial port conversion receiving driving circuit converts the received CAN data into a serial port signal and transmits it to the MCU through the FPGA communication circuit.

[0033] The CAN line initial level driving circuit includes an analog switch chip U14. The pins on the analog switch chip U14 adjust CAN_H and CAN_L by receiving control signals from the FPGA chip, providing an initial level state for the CAN line sending driving circuit to ensure that there is no misoperation during the communication process. The analog switch chip U14 includes a first input pin IN1, a second input pin IN2, a third input pin IN3, a fourth input pin IN4, a first control pin D1, a second control pin D2, a third control pin D3, a fourth control pin D4, a first output pin S1, a second output pin S2, a third output pin S3, a fourth output pin S4, a pin V-, a pin GND, a pin V+ and a pin VL; the first input pin IN1, the second input pin IN2, the third input pin IN3, and the fourth input pin IN4 are respectively connected to the first 24VCAN uplink level driving pin (pin 6), the second 24VCAN uplink level driving pin (pin 17), the second 24VCAN downlink level driving pin (pin 18) and the first 24VCAN downlink level control pin (pin 7) of the FPGA chip ,,The first control pin D1 is connected to the cathode of the diode D15 through the resistor R133; the second control pin D2 is connected to the cathode of the diode D15 through the resistor R134, and the anode of the diode D15 is connected to the VCC_IN power input terminal; the third control pin D3 and the fourth control pin D4 are respectively connected to the resistor R138 and the resistor R139 and then grounded; the first output pin S1 and the fourth output pin S4 are respectively connected to the CAN1_H pin of the CAN line sending drive circuit; the second output pin S2 and the third output pin S3 are respectively connected to the CAN1_L pin of the CAN line sending drive circuit; the pin V- and the pin GND are grounded; the pin V+ and the pin VL are respectively connected to the VCC_IN terminal and the VCC_5V power supply, and at the same time, the VCC_IN power supply terminal and the VCC_5V power supply terminal are connected to the ground through the capacitor C114 and the capacitor C115.

[0034] The model of the analog switch chip U14 is DG445 / SGM4512. The resistance values ​​of R133 and R139 are 1.8K, and the resistance values ​​of R134 and R138 are 910 ohms. Pins IN1, IN2, IN3 and IN4 on the U14 chip are defined as 24VCAN_UP1, 24VCAN_UP2, 24VCAN_PD2 and 24VCAN_PD1, respectively. When 24VCAN_UP1 / 24VCAN_PD1 and 24VCAN_UP2 / 24VCAN_PD2 are high at the same time, the 24VCAN circuit is driven, and resistors R133 and R138 are connected in series, and resistors R134 and R139 are connected in series. At this time, the initial level of CAN_H (CAN high) satisfies formula 1, that is, the voltage is about 8V: VCAN_H=[R138 / (R133+R138)]*VCC_IN =[910 / (1800+910)]*VCC_IN=8V (Formula 1) The initial level of CAN_L (CAN low) satisfies equation 2, that is, the voltage is about 16V.

[0035] VCAN_L= R139 / (R134+R139)*VCC_IN=[1800 / (910+1800)]*VCC_IN=16V (Formula 2) When 24VCAN_UP1 / 24VCAN_PD1 and 24VCAN_UP2 / 24VCAN_PD2 are both low, the driver is turned off.

[0036] This circuit adjusts CAN_H and CAN_L by receiving the control signal from the FPGA chip, and provides the initial level state for the CAN line sending drive circuit to ensure that there is no misoperation during the communication process.

[0037] The CAN line sending drive circuit drives CAN_H / CAN_L to form a differential level circuit to send data to the receiving drive circuit of the CAN line serial port conversion; the CAN line sending drive circuit includes MOSFET tube Q4, MOSFET tube Q3 and MOSFET tube Q5; the gate of the MOSFET tube Q4 is connected to the 24VCAN_UP0 pin of the FPGA chip through a resistor R135, and the C112 capacitor is connected in parallel with the resistor R135 to provide a filtering function for the input signal and reduce noise interference. The gate of the MOSFET tube Q4 is connected to the pull-down resistor R136 and then grounded; the source of the MOSFET tube Q4 is grounded; the drain of the MOSFET tube Q4 is connected to the gate of the high-side driving part MOSFET tube Q3 through a current limiting resistor R132; the gate of the MOSFET tube Q3 is connected to the power supply VCC_IN through a resistor R131, and the power supply VCC_IN is connected to the C111 capacitor and then grounded. The diode D14 is connected in parallel with the resistor R131; the source of the MOSFET tube Q3 is connected to the power supply VCC_IN; the drain of Q3 is connected in series with the diode D16 and the resistor R137 to form the CAN1_H signal output terminal; in this circuit, the diode D14 is connected in parallel with the resistor R131 to protect the MOSFET tube Q3 from current or voltage damage. When the 24VCAN_UP0 pin changes from low to high, the MOSFET tubes Q4 and Q3 are turned on, driving CAN_H to output a high level.

[0038] In the CAN_L part, the gate of the MOSFET tube Q5 is connected to the 24VCAN_PD0 pin of the FPGA chip through the current limiting resistor R141, which is used to receive the digital logic signal transmitted from the FPGA chip. The resistor R141 is connected in parallel with the capacitor C113, and the gate of the MOSFET tube Q5 is grounded through the pull-down resistor R142 to ensure signal stability; the capacitor C113 is connected in parallel with the resistor R141 to filter out high-frequency noise and improve signal stability. The source of the MOSFET tube Q5 is grounded, and the drain of the MOSFET tube Q5 is connected to the current limiting resistor R140 to form the CAN_L output terminal. When the 24VCAN_PD0 pin changes from low to high, the MOSFET tube Q5 is turned on, and the drain voltage of Q5 is pulled down, driving the CAN_L signal line to output a low level.

[0039] After the CAN line initial level driving circuit sets the initial state of the CAN communication bus to ensure that the logic level of the CAN bus is in a stable initial state that meets the protocol requirements before the communication starts, the CAN line transmission driving circuit can start working. As shown in Figure 4, the CAN line transmission driving circuit drives CAN_H / CAN_L to form a differential level circuit to send data. The differential signal level conversion is as follows: Figure 5 As shown. From the figure, we can see how the level relationship of the differential signals of the two signal lines CAN_H and CAN_L in the CAN bus differential signal expresses the logic "0" (dominant, dominant state) and the logic "1" (recessive, recessive state). Among them, when the bus state is in the dominant state, the CAN_H level is higher and the CAN_L level is lower. During bus arbitration, the dominant state has a higher priority and can cover the recessive state. When there is a communication demand, this state is used; when the bus is in the recessive state, the CAN_H level is lower and the CAN_L level is higher, or there is no differential voltage between the two. This state is used when the bus is idle.

[0040] The model of the MOSFET tube Q4 is 2N7002, the model of the MOSFET tube Q3 is LP2309LT1G, the model of the MOSFET tube Q5 is CJ2310, the resistance values ​​of R138 and R134 are 910 ohms, and the resistance values ​​of R137 and R140 are 220 ohms.

[0041] The CAN line transmission drive circuit drives CAN_H / CAN_L to form a differential level circuit to send data. In the CAN_H part, 24VCAN_UP0 is the signal receiving end, which is connected to the 24VCAN_UP0 pin of the FPGA chip to receive the digital logic signal transmitted from the FPGA chip. The 24VCAN_PD0 pin is connected to the 24VCAN_PD0 pin of the FPGA chip to receive the digital logic signal transmitted from the FPGA chip. When VCC_IN=24V level, when 24VCAN_UP0 changes from low to high, MOS tubes Q4 and Q3 are turned on, driving the CAN1_H signal from the initial level to meet the VCAN_H voltage of about 8V to meet the voltage of about 16V. The calculation formula is shown in Formula 3: VCAN_H= [R138 / (R137+R138)]*VCC_IN=[910 / (220+910)]*VCC_IN=19.3V (Formula 3) When 24VCAN_UD0 changes from low to high, MOS tube Q5 is turned on, driving the CAN1_L signal from the initial level that satisfies the VCAN_L voltage of about 16V to the voltage that satisfies the voltage of about 8V. The calculation formula is shown in Formula 4: VCAN_L=[R140 / (R140+R134)]*VCC_IN=[220 / (220+910)]*VCC_IN=4.7V (Formula 4) When VCC_IN=12V level is applied at the same time, 12VCAN_UP0 / 24VCAN_UD0 is sent according to the CAN bus TX signal protocol, which complies with the CAN protocol standard. The baud rate can reach up to 125K.

[0042] The receiving drive circuit for converting the CAN line to the serial port includes a CAN transceiver chip U16 and a switch chip J16. The U16 chip model is MCP2558FD-H / SN, which is used to convert the serial port and CAN bus communication signals. The CAN transceiver chip U16 includes pins TXD, RXD, CANH, CANL, VSS, S, VDD, and VIO; pins TXD and RXD are respectively connected to pins CAN1_TXD and CAN1_RXD of the FPGA chip, pin CAN1_TXD is used to receive digital signals from the FPGA chip, and pin CAN1_RXD is used to send digital signals on the CAN bus; pins CANH and CANL are respectively connected to the CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit, and pins S, VDD, and VIO are respectively connected to the CAN1_TXD and CAN1_RXD of the FPGA chip, and pin CAN1_TXD is used to receive digital signals from the FPGA chip, and pin CAN1_RXD is used to send digital signals on the CAN bus. CANH is connected to one end of capacitor C125, pin CANL is connected to one end of capacitor C124, and the other end of capacitor C124 is connected to the other end of capacitor C125 and then grounded; pin VSS and pin S are both grounded; pin VDD is connected to VCC_5V power supply, and at the same time connected to capacitor C122 and then grounded to ensure stable power supply; pin VIO is connected to 3.3V power supply to match the logic level of MCU, and at the same time connected to capacitor C123 and then grounded to bypass noise; capacitor C124 and capacitor C125 are connected to the CAN1_H and CAN1_L differential signal lines to filter out high-frequency signal interference and stabilize the signal.

[0043] Pin 2 of the switch chip J16 is designed as CAN120_SW1 to transmit CAN signals corresponding to different channels; Pin 1 of the J16 chip is connected to a 3.3V power supply, and Pins 3 and 4 are respectively connected to the CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit through matching resistors R145 and R146 for terminal matching, and Pin 3 is connected to capacitor C121 and then grounded.

[0044] The line drive circuit adopts the existing circuit in the prior art, such as the patent applied by the applicant: Patent No. CN202320607364.0, the invention name is: A K-line drive circuit suitable for automobile bus, which can be used as the line drive circuit. The serial port drive circuit can adopt the commonly used RS485 and RS232 circuits.

[0045] The FPGA multi-communication driving circuit of the present invention, the communication system realizes data transmission and processing of different communication protocols through multiple circuit modules, and the specific working method is as follows: (1) First, the OBD data is transmitted to the FPGA communication circuit. After the FPGA identifies the data protocol type and processes it, it is sent to the MCU. The MCU selects CAN communication or LINE communication based on the transmitted data and sends a switching protocol instruction to the FPGA chip through the serial port. (2) When the MCU receives CAN communication data, during system initialization, that is, before CAN protocol communication, the CAN line initial level circuit will provide a certain voltage to keep the level stable, drive the CAN bus to the communication-ready state, and ensure that the CAN bus is in a stable state when idle; (3) When the FPGA chip receives the data that the MCU needs to send, the CAN line transmission drive circuit controls the level change of the CAN_H and CAN_L signals, and the data is transmitted to the CAN bus through differential signals. That is, the differential voltage of CAN_H and CAN_L changes according to the 1 and 0 values ​​of the data during the signal transmission process; (4) The data on the CAN bus is sent to the FPGA chip through the CAN line conversion serial port receiving driver circuit, and then sent to the MCU through the serial port.

[0046] (5) When data is sent on the CAN bus, the CAN line conversion receiving drive circuit receives differential signals from the CAN_H and CAN_L pins on the CAN bus. The received differential signals are converted into single-ended signals by the receiving circuit, that is, converted into serial data and transmitted to the FPGA chip. Through the coordinated work of these three circuits, the system can realize the conversion from CAN bus to serial communication and support data exchange of multiple protocols.

Claims

1. A multi-communication driving circuit based on FPGA, comprising a communication driving circuit, characterized in that: It also includes an FPGA communication circuit; the communication drive circuit includes a CAN line drive circuit, a LINE line drive circuit and a serial port drive circuit; the CAN line drive circuit and the LINE line drive circuit are respectively connected to the FPGA communication circuit to transmit the data of the OBD interface to the FPGA communication circuit; The FPGA communication circuit converts the received protocol and processes the data, and transmits the data to the MCU through the serial port driver circuit. It also receives the instructions sent by the MCU through the serial port, selects the CAN line driver circuit or the LINE line driver circuit for communication, and realizes different protocol communications.

2. The FPGA-based multi-communication driving circuit according to claim 1, characterized in that: The FPGA communication circuit includes an FPGA chip and a communication control module arranged inside the FPGA chip; the communication control module multiplexes the outputs of multiple pins of the FPGA, selects different signal paths and controls the status of the communication protocol to achieve control of bus communication.

3. The FPGA-based multi-communication driving circuit according to claim 2, characterized in that: The FPGA chip includes a LINE0 serial port receiving pin, a LINE0 serial port sending pin, a CAN1 serial port receiving pin, a CAN1 serial port sending pin, a LINE1 serial port receiving pin, a LINE1 serial port sending pin, an MCU serial port 5 sending pin, an MCU serial port 5 receiving pin, a CAN0 serial port receiving pin, a CAN0 serial port sending pin and a GPIO pin; the MCU serial port 5 sending pin communicates with the MCU serial port, receives commands, and performs logic switching according to the received commands; the MCU serial port 5 receiving pin communicates with the MCU serial port, returns commands, and returns parameters after executing the commands; the LINE0 serial port receiving pin, the LINE0 serial port sending pin, the LINE1 serial port receiving pin and the LINE1 serial port sending pin are connected to a LINE line driving circuit for LINE line communication; the CAN1 serial port receiving pin, the CAN1 serial port sending pin, the CAN0 serial port receiving pin and the CAN0 serial port sending pin are connected to a CAN line driving circuit to realize CAN line communication; The communication control module includes a first register, a second register and a pin output control register arranged inside the FPGA chip; the first register and the second register are used to store control information sent by the MCU, and this information is used to configure the pin output control register, thereby controlling the pin state of the FPGA chip to realize CAN line communication or LINE line communication.

4. The FPGA-based multi-communication driving circuit according to claim 3, characterized in that: The first register is used to control the high and low levels of the CAN0 and CAN1 pins on the FPGA chip to select different communication modes, specifically: The address of the first register is 0x03, the reset value is 0x00, and the 7th, 6th and 3rd bits of the register are reserved; the 5th and 4th bits are set to CAN1_PHY_SEL[1:0], and different CAN transceivers are selected by setting the parameters of the 5th and 4th bits, thereby controlling the CAN1 pin on the FPGA chip to output high or low, and connecting with the CAN line drive circuit to realize CAN line communication; the 2nd, 1st and 0th bits of the first register are set to CAN0_PHY_SEL[2:0], and the values ​​of these three bits are set to configure the CAN0 pin on the FPGA chip to output high or low; The output of the LINE0 pin and the LINE1 pin on the FPGA chip are controlled by the difference between the high four bits and the fourth bit of the second register, specifically: The address of the second register is 0x04, the reset value is 0x00, the high bits 7, 6, 5, and 4 of the register are set to LINE_RX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE receive signal pin on the FPGA chip by setting the difference of these four bits to realize the communication of the LINE line; the low bits 3, 2, 1, and 0 of the second register are set to LINE_TX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE send signal pin on the FPGA chip by setting the difference of these four bits to realize the communication of the LINE line.

5. The FPGA-based multi-communication driving circuit according to claim 1, characterized in that: The CAN line driving circuit includes a CAN line initial level driving circuit, a CAN line sending driving circuit and a CAN line serial port conversion receiving driving circuit. The CAN line initial level driving circuit controls the level of the CAN bus to be in an idle state. The CAN line sending driving circuit transmits the data sent by the FPGA through the CAN bus. The CAN line serial port conversion receiving driving circuit converts the received CAN data into a serial port signal and transmits it to the MCU through the FPGA communication circuit.

6. The FPGA-based multi-communication driving circuit according to claim 5, characterized in that: The CAN line initial level driving circuit includes an analog switch chip U14. The pins on the analog switch chip U14 adjust CAN_H and CAN_L by receiving control signals from the FPGA chip, providing an initial level state for the CAN line sending driving circuit to ensure that there is no misoperation during the communication process. The analog switch chip U14 includes a first input pin IN1, a second input pin IN2, a third input pin IN3, a fourth input pin IN4, a first control pin D1, a second control pin D2, a third control pin D3, a fourth control pin D4, a first output pin S1, a second output pin S2, a third output pin S3, a fourth output pin S4, a pin V-, a pin GND, a pin V+ and a pin VL; the first input pin IN1, the second input pin IN2, the third input pin IN3, and the fourth input pin IN4 are respectively connected to the first 24VCAN uplink level driving pin, the second 24VCAN uplink level driving pin, the second 24VCAN downlink level driving pin and the first 24VCAN downlink level control pin of the FPGA chip, and the first control pin D1 is connected to the first 24VCAN uplink level driving pin, the second 24VCAN downlink level driving pin and the first 24VCAN downlink level control pin through a resistor R133 is connected to the cathode of diode D15; the second control pin D2 is connected to the cathode of diode D15 through resistor R134, and the anode of diode D15 is connected to the VCC_IN power input terminal; the third control pin D3 and the fourth control pin D4 are respectively connected to resistor R138 and resistor R139 and then grounded; the first output pin S1 and the fourth output pin S4 are respectively connected to the CAN1_H pin of the CAN line sending drive circuit; the second output pin S2 and the third output pin S3 are respectively connected to the CAN1_L pin of the CAN line sending drive circuit; pin V- and pin GND are grounded; pin V+ and pin VL are respectively connected to the VCC_IN terminal and the VCC_5V power supply, and at the same time, the VCC_IN power supply terminal and the VCC_5V power supply terminal are connected to the ground through the capacitor C114 and the capacitor C115.

7. The FPGA-based multi-communication driving circuit according to claim 5, characterized in that: The CAN line transmission drive circuit forms a differential level circuit by driving CAN_H / CAN_L to send data to the receiving drive circuit of the CAN line conversion serial port; the CAN line transmission drive circuit includes MOSFET tube Q4, MOSFET tube Q3 and MOSFET tube Q5; the gate of the MOSFET tube Q4 is connected to the 24VCAN_UP0 pin of the FPGA chip through the resistor R135, the C112 capacitor is connected in parallel with the resistor R135, the gate of the MOSFET tube Q4 is connected to the pull-down resistor R136 and then grounded; the source of the MOSFET tube Q4 is grounded; the drain of the MOSFET tube Q4 is connected to the gate of the high-side driving part MOSFET tube Q3 through the current limiting resistor R132; the gate of the MOSFET tube Q3 is connected to the power supply VCC_IN through the resistor R131, and the power supply VCC_IN is connected to the ground through the capacitor C111. The diode D14 is connected in parallel with the resistor R131; the source of the MOSFET tube Q3 is connected to the power supply VCC_IN; the drain of Q3 is connected in series with the diode D16 and the resistor R137 to form the CAN1_H signal output terminal; In the CAN_L part, the gate of the MOSFET tube Q5 is connected to the 24VCAN_PD0 pin of the FPGA chip through the current limiting resistor R141, which is used to receive the digital logic signal transmitted from the FPGA chip. The resistor R141 is connected in parallel with the capacitor C113, and the gate of the MOSFET tube Q5 is grounded through the pull-down resistor R142; the capacitor C113 is connected in parallel with the resistor R141, the source of the MOSFET tube Q5 is grounded, and the drain of the MOSFET tube Q5 is connected to the current limiting resistor R140 to form the CAN_L output terminal.

8. The FPGA-based multi-communication driving circuit according to claim 5, characterized in that: The receiving drive circuit of the CAN line conversion serial port includes a CAN transceiver chip U16 and a switch chip J16. The CAN transceiver chip U16 includes pins TXD, RXD, CANH, CANL, VSS, S, VDD, and VIO. Pin TXD and pin RXD are respectively connected to pins CAN1_TXD and CAN1_RXD of the FPGA chip. Pin CAN1_TXD is used to receive digital signals from the FPGA chip, and pin CAN1_RXD is used to send digital signals on the CAN bus. Signal; Pin CANH and pin CANL are respectively connected to the CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit, pin CANH is connected to one end of capacitor C125, pin CANL is connected to one end of capacitor C124, and the other end of capacitor C124 is connected to the other end of capacitor C125 and then grounded; pin VSS and pin S are both grounded; pin VDD is connected to the VCC_5V power supply, and is connected to capacitor C122 and then grounded; VIO pin is connected to a 3.3V power supply to match the logic level of the MCU, and is connected to capacitor C123 and then grounded; Pin 2 of the switch chip J16 is designed as CAN120_SW1 to transmit CAN signals corresponding to different channels; Pin 1 of the J16 chip is connected to a 3.3V power supply, and pins 3 and 4 are connected to the CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit through matching resistors R145 and R146 respectively, and pin 3 is connected to capacitor C121 and then grounded.

9. The FPGA-based multi-communication driving circuit according to claim 2 or 3, characterized in that: The FPGA chip model is GW1N-4K-LQFP100.

10. The FPGA-based multi-communication driving circuit according to claim 6, characterized in that: The model of the analog switch chip U14 is DG445 / SGM4512, the resistance values ​​of R133 and R139 are 1.8K, and the resistance values ​​of R134 and R138 are 910 ohms; The model of the MOSFET tube Q4 is 2N7002, the model of the MOSFET tube Q3 is LP2309LT1G, the model of the MOSFET tube Q5 is CJ2310, and the resistance values ​​of R137 and R140 are 220 ohms; The model of the CAN transceiver chip U16 is MCP2558FD-H / SN.

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