Data transmission system and PCIe equipment

Abstract

The present application provides a data transmission system and a PCIe device. The data transmission system includes a first configuration device, a second configuration device, a PCIe switch, a first PCIe device and a second PCIe device. The first PCIe device and the second PCIe device are FPGAs respectively. The first configuration device configures the bus master enable and disable control services for the first PCIe device and the second PCIe device. The second configuration device configures address conversion parameters for the first PCIe device and the second PCIe device. The second configuration device sends read instructions and write instructions to the first PCIe device and the second PCIe device. The first PCIe device and the second PCIe device perform active read operations or active write operations through the PCIe switch based on the read instructions and the write instructions. The present application avoids the use of high-cost PCIe devices with DMA functions through the configuration process, saving material costs.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission system and a PCIe device. Background Art

[0002] In the application of the Peripheral Component Interconnect Express (PCIe) bus, in order to save the resource waste caused by the Central Processing Unit (CPU) as a data transfer, a peer-to-peer (P2P) communication technology is proposed. This technology allows PCIe devices to directly access other PCIe devices without the need for CPU transfer.

[0003] In the prior art, P2P technology is implemented by integrating a direct memory access (DMA) controller in a PCIe device. Specifically, the host can access the register space of the DMA controller, configure registers, and monitor the DMA status in a PCIe in-band manner, and enable the DMA engine to generate DMA read and write requests, so that PCIe devices can communicate directly.

[0004] However, PCIe devices with DMA functions are relatively expensive, and the process of data transmission through a DMA controller requires the development of a P2P driver and upper-level applications, which requires a lot of manpower and material resources. Summary of the invention

[0005] The purpose of this application is to provide a data transmission system and PCIe device to address the deficiencies in the above-mentioned prior art, so as to solve the problems in the prior art that the equipment cost is high and a large amount of manpower and material resources are required for research and development.

[0006] To achieve the above objectives, the technical solutions adopted in this application are as follows: In a first aspect, the present application provides a data transmission system, the data transmission system comprising a first configuration device, a second configuration device, a PCIe switch, a first PCIe device and a second PCIe device, wherein the first PCIe device and the second PCIe device are FPGAs; The first configuration device is used to configure bus master enable and disable model control service for the first PCIe device and the second PCIe device, wherein the bus master enable is used to enable the first PCIe device and the second PCIe device to have the ability to actively initiate read and write operations, and the disable model control service is used to enable the data transmission of the first PCIe device and the second PCIe device to be free from access control restrictions; The second configuration device is used to configure address conversion parameters for the first PCIe device and the second PCIe device, and the address conversion parameters are used to indicate an address conversion relationship between an AXI address and a PCIe address; The second configuration device is further used to issue a read instruction and a write instruction to the first PCIe device and the second PCIe device, wherein the read instruction is used to instruct the first PCIe device and the second PCIe device to read data through the PCIe switch, and the write instruction is used to instruct the first PCIe device and the second PCIe device to output data through the PCIe switch; The first PCIe device and the second PCIe device are used to perform an active read operation or an active write operation through a PCIe switch based on the read instruction and the write instruction.

[0007] Optionally, the read instruction includes: a read burst length and a read address identifier; The first PCIe device is specifically used for: receiving the read instruction sent by the second configuration device; Sending a read request to the second PCIe device through the PCIe switch according to the read instruction, wherein the read request includes the read burst length and the read address identifier; The first target data sent by the second PCIe device is received through the PCIe switch, and written into the static random access memory of the first PCIe device.

[0008] Optionally, the first PCIe device is specifically used for: storing the received first target data in a PCIe register; The first target data is read from the PCIe register in the first PCIe device according to the address conversion parameter and written into the AXI bridge register, and the first target data in the AXI bridge register is written into a static random access memory.

[0009] Optionally, the write instruction includes a write burst length and a write address identifier; The first PCIe device is specifically used for: receiving the write instruction sent by the second configuration device; Read the second target data in the static random access memory according to the write address identifier in the write instruction, and write the second target data into the AXI bridge register; The second target data in the AXI bridge register in the first PCIe device is read according to the address conversion parameter, and is written into the PCIe register, and the data is sent through the PCIe switch.

[0010] Optionally, the first configuration device is further used for: Before configuring the bus master enable and disable model control services for the first PCIe device and the second PCIe device, at least one PCIe device connected to the PCIe switch is enumerated, and the hardware test environment status of each PCIe device is determined according to the enumeration result, so as to configure the bus master enable and disable model control services for at least one PCIe device according to the hardware test environment status of each PCIe device.

[0011] Optionally, the first PCIe device is further used for: Perform traffic statistics on the data stored in the static random access memory, and send the traffic statistics result to the second configuration device.

[0012] Optionally, the first PCIe device is further used for: Perform bit error statistics on the data stored in the static random access memory, and send the bit error statistics result to the second configuration device.

[0013] Optionally, the second configuration device is further used for: According to the bit error statistics result and the bit error rate threshold, it is determined whether the data transmission environment of the first PCIe device is normal.

[0014] Optionally, the second configuration device communicates with the first PCIe device via a USB bus and an IIC bus, and the first PCIe device further includes: an IIC protocol to AXI protocol conversion module; The second configuration device is specifically used to send the address conversion parameter to the first PCIe device through the USB bus and the IIC bus; The first PCIe device is used to perform protocol conversion on the address conversion parameters through the IIC protocol to AXI protocol module and store the converted parameters in an AXI bridge register in the first PCIe device.

[0015] In a second aspect, the present application provides a PCIe device, which is the first PCIe device or the second PCIe device as described in the first aspect, the PCIe device is connected to the first configuration device through a PCIe switch, and the PCIe device is connected to the second configuration device through a USB bus.

[0016] The beneficial effect of the present application is that: in the data transmission system, the first PCIe device and the second PCIe device are FPGAs, respectively, so that the PCIe device can be adjusted and reconfigured according to different requirements and environmental conditions, thereby reconstructing the functions of the PCIe device to adapt to new tasks and functions. The first configuration device configures the bus master enable and disables the control service of the first PCIe device and the second PCIe device, and the second configuration device configures the address conversion parameters of the first PCIe device and the second PCIe device, so that the PCIe devices have active read and write capabilities. After the configuration is completed, the second configuration device sends read instructions and write instructions to the first PCIe device and the second PCIe device, so that the first PCIe device and the second PCIe device perform active read operations or active write operations through the PCIe switch based on the read instructions and the write instructions. The present application realizes active read and write by pre-configuring the PCIe device, thereby avoiding the use of high-cost PCIe devices with DMA functions, saving material costs, and does not require software development engineers to participate in development, saving labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the architecture of a data transmission system provided in an embodiment of the present application; Figure 2 It is a schematic diagram of a flow chart of a first PCIe device performing a read operation provided by an embodiment of the present application; Figure 3 It is a flowchart of a first PCIe device performing an active write operation provided by an embodiment of the present application; Figure 4 It is a schematic diagram of a configuration flow of a second configuration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0020] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0022] In the prior art, the host can access the register space of the DMA controller, configure registers, and monitor the DMA status in the PCIe in-band mode, and enable the DMA engine to generate DMA read and write requests, so that PCIe devices can communicate directly. However, this method is costly, and the development of P2P drivers and upper-layer applications requires a lot of manpower and material resources.

[0023] Based on this, the present application proposes a data transmission system, which configures the bus master enable and disable control service for the PCIe device connected to the PCIe switch through a first configuration device, and configures the address conversion parameters for the PCIe device through a second configuration device. Through the above configuration process, the PCIe device has active read and write capabilities and is not restricted by access control. After the configuration is completed, the second configuration device sends a read instruction or a write instruction to the PCIe device so that the PCIe device performs an active read operation or an active write operation through the PCIe switch. The present application realizes active reading and writing by pre-configuring the PCIe device, thereby avoiding the use of high-cost PCIe devices with DMA functions, and does not require software development engineers to participate in the development, saving manpower costs.

[0024] Figure 1 is a schematic diagram of the architecture of a data transmission system provided in an embodiment of the present application. Figure 1 The architecture of the data transmission system is introduced. The data transmission system includes a first configuration device, a second configuration device, a PCIe switch, a first PCIe device and a second PCIe device, wherein the first PCIe device and the second PCIe device are field programmable gate arrays (FPGAs). The first configuration device may be a host device, and the second configuration device may be a PC device.

[0025] Among them, FPGA is used to implement the first PCIe device and the second PCIe device. Since FPGA has high flexibility, it can be adjusted and reconfigured according to different needs and environmental conditions, and the functions of the PCIe device can be reconstructed, such as the secondary development of the user interface, to adapt to new tasks and functions.

[0026] It is worth noting that the PCIe switch has multiple ports and can connect multiple PCIe devices, thereby forming a complex topology. This application is introduced by taking the example of a PCIe switch connected to a first PCIe device and a second PCIe device.

[0027] Specifically, the first PCIe device and the second PCIe device are respectively connected to the PCIe switch, the PCIe switch is connected to the first configuration device, the first configuration device and the second configuration device are independently configured, the first configuration device can access the first PCIe device and the second PCIe device in an in-band manner, and the second configuration device can access the first PCIe device and the second PCIe device through a universal serial bus (USB) bus and an inter-integrated circuit (IIC) bus.

[0028] Optionally, the PCIe device may include an AXI bridge register and a static random access memory. In addition, the PCIe device also includes a configuration space register and a PCIe core module (PCIe core), wherein the configuration space register includes a command register and an ACS extended function register.

[0029] Optionally, the PCIe device may be GEN3X4, and the maximum length of the payload in the transaction layer packet may be 128B. If the burst length is set to 4KB, the data transmission rate may reach 2600 Mbps.

[0030] Next, the configuration and application process of the data transmission system are introduced.

[0031] Optionally, the first configuration device is used to configure bus master enable and disable model control service for the first PCIe device and the second PCIe device, the bus master enable is used to enable the first PCIe device and the second PCIe device to have the ability to actively initiate read and write operations, and the disable model control service is used to enable the data transmission between the first PCIe device and the second PCIe device to be unrestricted by access control.

[0032] The first configuration device may configure bus master enabling and disabling control services for the first PCIe device and the second PCIe device through a PCIe switch.

[0033] Specifically, since the PCIe device itself does not support the function of actively initiating read and write, the active read and write function is enabled by configuring the bus master enable and disabling the ACS service. Specifically, the bus master enable (bus master enable) can be set in the Command register, and the ACS service (disable ACS) can be set in the ACS extended function register.

[0034] Optionally, the second configuration device is used to configure address conversion parameters for the first PCIe device and the second PCIe device, where the address conversion parameters are used to indicate an address conversion relationship between an AXI address and a PCIe address.

[0035] Optionally, the AXI address may be an address of data in an AXI bridge register, and the PCIe address may be an address of data in a PCIe register.

[0036] Specifically, the second configuration device configures the address conversion parameters for the first PCIe device and the second PCIe device through the configuration interface. Specifically, the second configuration device sends the address conversion parameters to the first PCIe device through the configuration interface, and the first PCIe device is used to write the address conversion parameters into the AXI bridge register. The address conversion parameters can record the address mapping table of the mapping relationship between the AXI address and the PCIe address.

[0037] As an optional implementation, each PCIe device may further include a first write execution module, a second write execution module, a first read execution module, a second read execution module, a first AXI slave interface, a second AXI slave interface and an AXI master interface. After the second configuration device sends the address conversion parameter, the address conversion parameter is written into the AXI bridge register through the first AXI slave interface through the first write execution module. The first read execution module is used to read data from the AXI bridge register and send it to the second configuration device. The second write execution module is used to perform an active write operation through the second AXI slave interface, and the second read execution module is used to perform an active read operation through the second AXI slave interface. The AXI master interface is used to transmit data in a static random access memory.

[0038] As an optional implementation, in addition to configuring the address conversion parameters, the second configuration device can also configure the MSI interrupt. Specifically, the interrupt is triggered by sending data to a specific address, thereby realizing an efficient and scalable interrupt mechanism, improving the system response speed and throughput, and simplifying the interrupt management and debugging process.

[0039] Optionally, the second configuration device is also used to send read instructions and write instructions to the first PCIe device and the second PCIe device, the read instructions are used to instruct the first PCIe device and the second PCIe device to read data through the PCIe switch, and the write instructions are used to instruct the first PCIe device and the second PCIe device to output data through the PCIe switch.

[0040] Optionally, the read instruction may include a read address identifier, the read address identifier includes a read source address and a read destination address, wherein the read source address and the read destination address are used to indicate the receiving end and the sending end of the read operation. The write instruction may include a write address identifier, the write address identifier includes a write source address and a write destination address, wherein the write source address and the write destination address are used to indicate the receiving end and the sending end of the write operation.

[0041] As an optional implementation, after the configuration is completed, the second configuration device sends a read instruction to the first PCIe device, so that the first PCIe device obtains data from the static random access memory in the second PCIe device through the PCIe switch and stores it in the static random access memory in the first PCIe device.

[0042] As another optional implementation, after the configuration is completed, the second configuration device sends a write instruction to the first PCIe device, so that the first PCIe device sends the data in the static random access memory to the first PCIe device through the PCIe switch, and the first PCIe device stores the received data in the static random access memory.

[0043] Optionally, the first PCIe device and the second PCIe device are used to perform an active read operation or an active write operation through a PCIe switch based on a read instruction and a write instruction.

[0044] Specifically, after receiving the read instruction and the write instruction, the first PCIe device and the second PCIe device perform an active read operation or an active write operation according to the source address and the destination address in the read instruction or the write instruction.

[0045] In this embodiment, in the data transmission system, the first PCIe device and the second PCIe device are FPGAs, so that the PCIe device can be adjusted and reconfigured according to different requirements and environmental conditions, thereby reconstructing the functions of the PCIe device to adapt to new tasks and functions. The first configuration device configures the bus master enable and disables the control service of the first PCIe device and the second PCIe device, and the second configuration device configures the address conversion parameters of the first PCIe device and the second PCIe device, so that the PCIe devices have active read and write capabilities. After the configuration is completed, the second configuration device sends read instructions and write instructions to the first PCIe device and the second PCIe device, so that the first PCIe device and the second PCIe device perform active read operations or active write operations based on the read instructions and the write instructions through the PCIe switch. The present application realizes active read and write by pre-configuring the PCIe device, thereby avoiding the use of high-cost PCIe devices with DMA functions, saving material costs, and does not require software development engineers to participate in development, saving labor costs.

[0046] When the first configuration device and the second configuration device complete the configuration of the PCIe device, the second configuration module can send a read instruction and a write instruction to the PCIe device through the configuration interface, so that the PCIe receiving the read instruction or the write instruction performs an active read operation or an active write operation. Next, the process of the second configuration module sending a read instruction and a write instruction to the first PCIe device so that the first PCIe device and the second PCIe device perform data transmission, thereby performing an active read operation or an active write operation is introduced as an example.

[0047] As an optional implementation manner, the read instruction includes: a read burst length and a read address identifier.

[0048] The read burst length refers to the amount of data continuously transmitted in one transmission operation during a read operation. Exemplarily, the read burst length may be 4KB. The read address identifier includes a read source address and a read destination address.

[0049] Optionally, the read instruction is used to instruct the PCIe device to start a read operation.

[0050] Next, refer to Figure 2The specific functions of the first PCIe device are introduced. Figure 2 It is a flowchart of a first PCIe device performing a read operation provided in an embodiment of the present application.

[0051] S201: Receive a read instruction sent by a second configuration device.

[0052] As an optional implementation, the read instruction sent by the second configuration device is received through a configuration interface. The configuration interface may be, for example, a USB interface.

[0053] Optionally, the PCIe device indicated by the destination address is determined according to the read address identifier in the read instruction sent by the second configuration device. This embodiment is described by taking the case where the read instruction indicates that the read destination address is the second PCIe device as an example.

[0054] S202: Send a read request to the second PCIe device through the PCIe switch according to the read instruction, where the read request includes a read burst length and a read address identifier.

[0055] Specifically, the first PCIe device encodes according to the read instruction to generate a read request, and sends the read request to the PCIe switch through the PCIe core module (PCIe core) of the first PCIe device, and the PCIe switch sends the read request to the second PCIe device.

[0056] When the second PCIe device receives the read request from the first PCIe device, it decodes it and performs identity authentication based on the decoded data to determine whether the read instruction is sent to the device. If so, it prepares to send response data, where the response data is the first target data.

[0057] S203: Receive the first target data sent by the second PCIe device through the PCIe switch, and write the first target data into the static random access memory of the first PCIe device.

[0058] Optionally, after the second PCIe device sends the first target data to the PCIe core of the first PCIe device according to the read burst length, the first PCIe device decodes the first target data and writes it into the static random access memory.

[0059] In this embodiment, the first PCIe device receives a read instruction sent by the second configuration device, then sends a read request to the second PCIe device through the PCIe switch, and receives the first target data sent by the second PCIe device through the PCIe switch and writes it into the static random access memory, thereby realizing the active read operation of the PCIe device.

[0060] As an optional implementation, the specific steps of receiving the first target data sent by the second PCIe device through the PCIe switch in the above step S203 performed by the first PCIe device and writing it into the static random access memory of the first PCIe device are as follows: Optionally, the received first target data is stored in a PCIe register.

[0061] Optionally, this step may convert parallel data transmitted by the PCIe switch into serial data.

[0062] Optionally, the first target data is read from a PCIe register in the first PCIe device according to the address conversion parameter and written into an AXI bridge register, and the first target data in the AXI bridge register is written into a static random access memory.

[0063] Optionally, based on the address conversion parameter and the address of the data stored in the PCIe register, determine the address in the AXI bridge register corresponding to the address of the data stored in the PCIe register, and then write the first target data into the corresponding address in the AXI bridge register according to the read burst length.

[0064] Optionally, in the process of writing the first target data in the AXI bridge register into the static random access memory, the capacity of each transmission data packet is the same as the read burst length, for example, may be 4 KB.

[0065] In this embodiment, the first PCIe device stores the received first target data in a PCIe register, reads the first target data from the PCIe register in the first PCIe device according to the address conversion parameter and writes it into the AXI bridge register, and writes the first target data in the AXI bridge register into a static random access memory, thereby realizing an active read operation and saving the P2P driver software development cost.

[0066] It should be understood that this embodiment only describes the process when the first PCIe device performs an active read operation. If the second configuration device sends a read instruction to the second PCIe device, the second PCIe can also perform an active read operation according to the above steps, so it will not be repeated here.

[0067] Next, the active write operation is introduced. Optionally, the write instruction includes a write burst length and a write address identifier.

[0068] The write burst length refers to the amount of data continuously transmitted in one transmission operation during a write operation. Exemplarily, the write burst length may be 4KB. The write address identifier includes a write source address and a write destination address.

[0069] Optionally, the write instruction is used to instruct the PCIe device to start a write operation.

[0070] Next, refer to Figure 3 The process of performing an active write operation on the first PCIe device is introduced. Figure 3 It is a flowchart of a first PCIe device performing an active write operation provided in an embodiment of the present application.

[0071] S301: Receive a write instruction sent by a second configuration device.

[0072] S302: Read the second target data in the static random access memory according to the write address identifier in the write instruction, and write the second target data into the AXI bridge register.

[0073] Optionally, the write address identifier may also include a data storage address. In an application scenario where data transmission is performed, the first PCIe device determines the second target data to be sent according to the data storage address in the write address identifier in the write instruction, and writes the second target data into the AXI bridge register.

[0074] Optionally, in an application environment where hardware testing is performed, random test data is generated by a PRBS, and the random test data is written into an AXI bridge register as second target data.

[0075] S303: Read the second target data in the AXI bridge register in the first PCIe device according to the address conversion parameter, write the second target data into the PCIe register, and send the data through the PCIe switch.

[0076] Specifically, according to the address conversion parameter and the address of the second target data in the AXI bridge register, an address in the PCIe register corresponding to the address of the second target data in the AXI bridge register is determined, and then the second target data is written into the PCIe register.

[0077] Optionally, the second target data is sent to the second PCIe device through the PCIe core according to the write burst length.

[0078] Optionally, after receiving the second target data, the second PCIe device writes the second target data into the static random access memory according to the address conversion parameter corresponding to the second PCIe device.

[0079] In this embodiment, after the first PCIe device receives the write instruction, it reads the second target data in the static random access memory according to the write address identifier in the write execution and writes it into the AXI bridge register, reads the second target data in the AXI bridge register in the first PCIe device according to the address conversion parameter, and writes it into the PCIe register, and sends the data through the PCIe switch, thereby realizing active write operations and saving R&D costs.

[0080] As an optional implementation, if the application scenario is a hardware test environment, the write instruction includes a write burst length and a write address identifier, wherein the write address identifier includes a write destination address. The first PCIe device is specifically used to: receive a write instruction sent by the second configuration device, generate test data using a pseudo-random binary sequence generator (PRBS), write the test data into an AXI bridge register, read the test data in the AXI bridge register in the first PCIe device according to the address conversion parameter, write the test data into the PCIe register, and send the data through the PCIe switch so that the second PCIe device receives the test data.

[0081] It should be understood that this embodiment only describes the process when the first PCIe device performs an active write operation. If the second configuration device sends a write instruction to the second PCIe device, the second PCIe can also perform an active write operation according to the above steps, so it will not be repeated here.

[0082] As an optional implementation, before configuring the first PCIe device and the second PCIe device to enable the bus master and disable the model control service, the first configuration device is also used to enumerate at least one PCIe device connected to the PCIe switch, determine the hardware test environment status of each PCIe device according to the enumeration result, and configure the bus master enable and disable the model control service for at least one PCIe device according to the hardware test environment status of each PCIe device.

[0083] Specifically, the process of enumerating PCIe devices by the first configuration device is as follows: first perform initialization, that is, perform a hardware reset operation to ensure that the PCIe device is in a known state, and then initialize the root complex. After the initialization is completed, access the configuration space register of each PCIe device, which stores various information of the device, such as manufacturer identification, device identification and class code, and detect whether each information meets the requirements, and then scan the lower-level PCIe switches of the root complex and the PCIe devices connected thereto layer by layer according to recursive traversal. After scanning each PCIe device, allocate resources to it. In the above steps, if there is a PCIe device that cannot meet the requirements, it means that the hardware test status of the PCIe device does not meet the requirements and the data transmission in this application cannot be performed.

[0084] In this embodiment, taking the hardware test environment status of the first PCIe device and the second PCIe device meeting the requirements as an example, bus master enabling and disabling control services are configured for them.

[0085] In this embodiment, before configuring the bus master enable and disabling the template control service, each PCIe device connected to the PCIe switch is enumerated, and the hardware test environment status of each PCIe device is determined according to the enumeration result, thereby ensuring that each PCIe device can operate normally.

[0086] Next, the functions of the PCIe device are introduced by taking the first PCIe device as an example.

[0087] Optionally, the first PCIe device is further configured to perform traffic statistics on data stored in the static random access memory, and send the traffic statistics result to the second configuration device.

[0088] Optionally, the traffic statistics result may be sent to the second configuration device through the configuration interface.

[0089] Optionally, the traffic statistics result may reflect the transmission performance of the data transmission system.

[0090] Optionally, the first PCIe device is further configured to perform bit error statistics on the data stored in the static random access memory, and send the bit error statistics result to the second configuration device.

[0091] Optionally, the bit error statistics result may be sent to the second configuration device through the configuration interface.

[0092] Optionally, the bit error statistics result may reflect the transmission performance of the data transmission system.

[0093] Optionally, since the PCIe device bus operates at a GEN3 rate and there is a PCIe switch between the first configuration device and the FPGA, the data transmission environment needs to be kept in a good state. Therefore, as an optional implementation, the second configuration device is also used to determine whether the data transmission environment of the first PCIe device is normal based on the bit error statistics and the bit error rate threshold.

[0094] As another optional implementation, the second configuration device is further used to determine whether the data transmission environment of the first PCIe device is normal according to the traffic statistics result and the bit error statistics result.

[0095] Specifically, if the traffic statistics result per unit time is less than the traffic threshold, and the bit error statistics result is less than the bit error rate threshold, the data transmission environment of the first PCIe device is abnormal, and the data transmission environment can be repaired by adjusting parameters such as burst length.

[0096] In this embodiment, by performing flow statistics and bit error statistics on the stored data, and judging whether the data transmission environment is normal based on the statistical results by the second configuration device, the reliability of the data transmission system is determined, the accuracy of data transmission is improved, and the system performance is improved.

[0097] As an optional implementation, Figure 4 This is a schematic diagram of a configuration process of a second configuration device provided in an embodiment of the present application. Taking the first PCIe device as an example, specifically, the second configuration device communicates with the first PCIe device via a USB bus and an IIC bus, and the first PCIe device further includes: an IIC protocol to AXI protocol module.

[0098] The second configuration device is specifically used to send the address conversion parameters to the first PCIe device through the USB bus and the IIC bus, and the first PCIe device is used to perform protocol conversion on the address conversion parameters through the IIC protocol to AXI protocol module and store them in the AXI bridge register in the first PCIe device.

[0099] Optionally, the second configuration device sends address conversion parameters in sequence through the USB bus, and sends data to the first PCIe device through the IIC bus. In the first PCIe device, the address conversion parameters under the IIC protocol are converted to the AXI protocol through the IIC protocol to AXI protocol module, and the address conversion parameters after protocol conversion are written into the AXI bridge register.

[0100] In this embodiment, the second configuration device sends the address conversion parameters to the first PCIe device through the USB bus and the IIC bus, so that the first PCIe device writes the address conversion parameters into the AXI bridge register through the IIC protocol to AXI protocol module, thereby quickly configuring the PCIe device.

[0101] An embodiment of the present application also provides a PCIe device, which is the first PCIe device or the second PCIe device as described above, the PCIe device is connected to the first configuration device via a PCIe switch, and the PCIe device is connected to the second configuration device via a USB bus.

[0102] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A data transmission system, characterized in that: The data transmission system includes a first configuration device, a second configuration device, a PCIe switch, a first PCIe device and a second PCIe device, wherein the first PCIe device and the second PCIe device are FPGAs respectively; The first configuration device is used to configure bus master enable and disable model control service for the first PCIe device and the second PCIe device, wherein the bus master enable is used to enable the first PCIe device and the second PCIe device to have the ability to actively initiate read and write operations, and the disable model control service is used to enable the data transmission of the first PCIe device and the second PCIe device to be free from access control restrictions; The second configuration device is used to configure address conversion parameters for the first PCIe device and the second PCIe device, and the address conversion parameters are used to indicate an address conversion relationship between an AXI address and a PCIe address; The second configuration device is further used to issue a read instruction and a write instruction to the first PCIe device and the second PCIe device, wherein the read instruction is used to instruct the first PCIe device and the second PCIe device to read data through the PCIe switch, and the write instruction is used to instruct the first PCIe device and the second PCIe device to output data through the PCIe switch; The first PCIe device and the second PCIe device are used to perform an active read operation or an active write operation through a PCIe switch based on the read instruction and the write instruction.

2. The data transmission system according to claim 1, characterized in that: The read instruction includes: a read burst length and a read address identifier; The first PCIe device is specifically used for: receiving the read instruction sent by the second configuration device; Sending a read request to the second PCIe device through the PCIe switch according to the read instruction, wherein the read request includes the read burst length and the read address identifier; The first target data sent by the second PCIe device is received through the PCIe switch, and written into the static random access memory of the first PCIe device.

3. The data transmission system according to claim 2, characterized in that: The first PCIe device is specifically used for: storing the received first target data in a PCIe register; The first target data is read from the PCIe register in the first PCIe device according to the address conversion parameter and written into the AXI bridge register, and the first target data in the AXI bridge register is written into a static random access memory.

4. The data transmission system according to claim 1, characterized in that: The write instruction includes a write burst length and a write address identifier; The first PCIe device is specifically used for: receiving the write instruction sent by the second configuration device; Read the second target data in the static random access memory according to the write address identifier in the write instruction, and write the second target data into the AXI bridge register; The second target data in the AXI bridge register in the first PCIe device is read according to the address conversion parameter, and is written into the PCIe register, and the data is sent through the PCIe switch.

5. The data transmission system according to claim 1, characterized in that: The first configuration device is also used for: Before configuring the bus master enable and disable model control services for the first PCIe device and the second PCIe device, at least one PCIe device connected to the PCIe switch is enumerated, and the hardware test environment status of each PCIe device is determined according to the enumeration result, so as to configure the bus master enable and disable model control services for at least one PCIe device according to the hardware test environment status of each PCIe device.

6. The data transmission system according to claim 1, characterized in that: The first PCIe device is further configured to: Perform traffic statistics on the data stored in the static random access memory, and send the traffic statistics result to the second configuration device.

7. The data transmission system according to claim 1, characterized in that: The first PCIe device is further configured to: Perform bit error statistics on the data stored in the static random access memory, and send the bit error statistics result to the second configuration device.

8. The data transmission system according to claim 7, characterized in that: The second configuration device is further configured to: According to the bit error statistics result and the bit error rate threshold, it is determined whether the data transmission environment of the first PCIe device is normal.

9. The data transmission system according to claim 1, characterized in that: The second configuration device communicates with the first PCIe device via a USB bus and an IIC bus, and the first PCIe device further includes: an IIC protocol to AXI protocol conversion module; The second configuration device is specifically used to send the address conversion parameter to the first PCIe device through the USB bus and the IIC bus; The first PCIe device is used to send the address conversion parameter to the AXI bridge register in the first PCIe device through the IIC protocol to AXI protocol module.

10. A PCIe device, characterized in that: The PCIe device is the first PCIe device or the second PCIe device as described in any one of claims 1 to 9, the PCIe device is connected to the first configuration device via a PCIe switch, and the PCIe device is connected to the second configuration device via a USB bus.

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