An IO interface expansion control circuit

Abstract

The present invention discloses an IO interface expansion control circuit, which belongs to the field of integrated circuit input and output interface expansion, and includes two groups of serial bus communication control units, two groups of interface expansion output units, or logic output units, wherein the serial bus communication control unit is provided with a chip selection signal interface, a first serial clock interface, an answer signal feedback interface, a first serial data input interface, a serial data output interface, a write pulse output interface, a read pulse output interface, and a first power supply interface, and the interface expansion output unit is provided with a second serial data input interface, a second serial clock interface, a third serial clock interface, a parallel data output interface, a first interrupt feedback interface, an enable interface, and a second power supply interface, or the logic output unit performs or logic processing on the data of the two groups of parallel data output interfaces. The present invention realizes a cold backup function through the cooperation of two groups of serial bus communication control units, two groups of interface expansion output units, or logic output units.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit input and output interface expansion, and in particular to an IO interface expansion control circuit. Background Art

[0002] The IO interface (Input / Output Interface) of an integrated circuit (such as CPU, MCU, DSP, FPGA and other control chips) is a bridge for information transmission between it and peripherals or other information processing units. These IO interfaces can use serial or parallel communication protocols for data transmission.

[0003] With the development of technology, integrated circuits need to connect to more and more external devices or other information processing units for communication, such as sensors, actuators, storage devices, etc. However, the number of IO interfaces of a monolithic integrated circuit itself is limited and cannot meet the needs of a large number of external connections. It is often necessary to expand the IO interface. The common expansion method is to use serial interface expansion chips for parallel expansion, such as expanding to 8, 16, or 32 IOs through serial interface expansion chips.

[0004] However, when the serial interface expansion chip itself fails, the expansion function will fail and cannot be used in some scenarios with high reliability requirements. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an IO interface expansion control circuit, which aims to achieve cold backup of the expanded IO interface to adapt to different circuit failure scenarios.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] An IO interface expansion control circuit comprises two groups of serial bus communication control units, two groups of interface expansion output units, or logic output units, wherein the serial bus communication control unit is provided with a chip selection signal interface, a first serial clock interface, an answer signal feedback interface, a first serial data input interface, a serial data output interface, a write pulse output interface, a read pulse output interface and a first power supply interface, wherein the chip selection signal interface, the first serial clock interface, the answer signal feedback interface and the first serial data input interface are used to connect the IO interface corresponding to the control chip; the interface expansion output unit is provided with a second serial data input interface, a second serial clock interface, a third serial clock interface, a parallel data output interface, a first interrupt feedback interface, an enable interface and a second power supply interface, wherein the second serial data input interface is connected to the serial data output interface, and the The second serial clock interface is connected to the write pulse output interface, the third serial clock interface is connected to the read pulse output interface, the first interrupt feedback interface and the enable interface are used to connect to the IO interface corresponding to the control chip; the OR logic output unit is used to perform OR logic processing on the data of the two groups of parallel data output interfaces and output them in parallel; wherein, the first power supply interface and the second power supply interface are both used to connect to the first power supply, and when the response signal feedback interface does not generate a response signal and the enable interface is in a disabled state, the parallel data output interface is reset to zero; when the data of one group of the second serial data input interface is not equal to the data of the parallel data output interface, the corresponding first interrupt feedback interface triggers an interrupt feedback signal, and the control chip does not send an enable signal to the corresponding enable interface according to the interrupt feedback signal.

[0008] Further, the interface expansion output unit includes a multi-bit shift register, a multi-bit latch register, and a comparator module, wherein the input end of the shift register is connected to the serial data output interface, the clock end of the shift register is connected to the write pulse output interface, the number of bits of the latch register is the same as that of the shift register, the input end of the latch register is connected to the output end of the shift register, and the clock end of the latch register is connected to the read pulse output interface, wherein the output end of the latch register is connected in series with the enable interface, and the input end of the comparator module is respectively connected to the output end of the shift register and the output end of the latch register; wherein, when at least one bit of data in the output end of the shift register and the output end of the latch register are not equal, the output end of the comparator module outputs the interrupt feedback signal, and the control chip disables the enable interface according to the interrupt feedback signal.

[0009] Furthermore, the comparator module includes multiple one-bit comparators and an OR gate module, the number of the one-bit comparators is the same as the number of bits of the shift register, the one-bit comparator has two input terminals and one output terminal, the OR gate module has input terminals and an output terminal which are the same in number as the output terminals of the one-bit comparator, the output terminal of the one-bit comparator is used to connect to the IO interface corresponding to the control chip, and the output terminal of the one-bit comparator is connected to the input terminal of the OR gate module; wherein, when the logic values ​​of the two input terminals of the one-bit comparator are the same, its output terminal outputs a logic value of zero, and when the logic values ​​of the two input terminals of the one-bit comparator are different, its output terminal outputs a logic value of one.

[0010] Furthermore, the one-bit comparator includes an XOR gate module and an inverter, the XOR gate module has two input ports and one output port, the input port of the inverter is connected to the output port of the XOR gate module, and the output port of the inverter is connected to the input end of the XOR gate module.

[0011] Furthermore, the IO interface expansion control circuit also includes an optocoupler isolation unit, an input end of the optocoupler isolation unit is connected to the IO interface corresponding to the control chip, and an output end of the optocoupler isolation unit is connected to the first serial data input interface.

[0012] Furthermore, the optocoupler isolation unit includes a switching current module and an optocoupler, the input end of the switching current module is connected to the IO interface corresponding to the control chip, the input end of the optocoupler is connected to the output end of the switching current module, and the output end of the optocoupler is connected to the first serial data input interface.

[0013] Furthermore, the switching current module includes an NPN transistor, a diode, a first current limiting resistor, a second current limiting resistor, and a bias resistor. The collector of the NPN transistor is connected to the emitter of the photodetector of the optocoupler, the collector of the photodetector of the optocoupler is used to connect to a second power supply, the emitter of the NPN transistor is grounded, the diode is connected in series between the base of the NPN transistor and the IO interface corresponding to the control chip, the first current limiting resistor is connected in series between the base of the NPN transistor and the diode, the second current limiting resistor is connected in series between the collector of the photodetector of the optocoupler and the first power supply, and the bias resistor is connected in series between the base of the NPN transistor and the ground.

[0014] Furthermore, a second inverter with an enable terminal is provided between the input terminal of one group of the optical coupling isolation units and the IO interface corresponding to the control chip, and the enable terminal of the second inverter is connected to the IO interface corresponding to the control chip.

[0015] Furthermore, an overcurrent protection unit is connected in series between the first power supply and the first power interface and the second power interface.

[0016] Furthermore, the overcurrent protection unit includes a blown fuse.

[0017] The present invention has the following beneficial effects: through the cooperation of two groups of serial bus communication control units, two groups of interface expansion output units, or logic output units, the expansion of serial port to parallel port is realized through serial bus communication, the number of IO interfaces of the control chip is increased, and at the same time, the data of the two groups of parallel data output interfaces are processed by the OR logic output unit. When a circuit combination of one group of serial bus communication control units, interface expansion output units, or logic output units fails, such as synchronous serial communication failure, output state is always low, and output state is always high, cold switching can be performed to another group of serial bus communication control units, interface expansion output units, and OR logic output unit circuit combination, thereby improving the reliability of the entire control circuit.

[0018] In addition to the above-described purposes, features and advantages, the present invention has other purposes, features and advantages. The present invention will be further described in detail below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 1 is a circuit framework diagram of an IO interface expansion control circuit in one embodiment of the present invention;

[0021] Figure 2 is a circuit framework diagram of an interface expansion output unit in one embodiment of the present invention;

[0022] Figure 3 is a circuit framework diagram of an interface expansion output unit in another embodiment of the present invention;

[0023] Figure 4 is a circuit framework diagram of a comparator module in an embodiment of the present invention;

[0024] Figure 5 FIG. 4 is a circuit framework diagram of an optocoupler isolation unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0028] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0029] refer to Figures 1 to 5 , is an IO interface expansion control circuit of an embodiment of the present invention, including two groups of serial bus communication control units U1, two groups of interface expansion output units U2, or logic output units U3.

[0030] Specifically, each group of serial bus communication control units U1 is provided with a chip select signal interface CS, a first serial clock interface CLK1, a response signal feedback interface RES, a first serial data input interface SI1, a serial data output interface SO, a write pulse output interface WPO, a read pulse output interface RPO and a first power supply interface VCC1.

[0031] When the circuit is connected, the first power interface VCC1 is connected to an external DC power supply, and the voltage of the DC power supply is set according to the actual situation, such as 3.3V, 5V, 12V, and 5V. In addition, the DC power supply can be obtained by converting AC power, for example, it can be converted by an AC-DC conversion chip. The chip select signal interface CS is connected to the GPIO port corresponding to the control chip, and the communication address of the serial bus communication control unit U1 is determined by outputting the corresponding level to prepare for subsequent synchronous serial communication; the control chip sends a synchronous clock signal to the first serial clock interface CLK to input data to the first serial data input interface SI bit by bit. In the case of synchronous serial communication failure, the response signal feedback interface RES cannot send a response signal to the GPIO port corresponding to the control chip. After the control chip fails to detect the corresponding response signal, it is determined that the synchronous serial communication has failed. It should be noted that the control chip can be a control chip such as a CPU, MCU, DSP, or FPGA.

[0032] Each group of interface expansion output units U2 is provided with a second serial data input interface SI2, a second serial clock interface CLK2, a third serial clock interface CLK3, a parallel data output interface Q1 (Q1-1, Q1-2, ...), a first interrupt feedback interface INT, an enable interface EN and a second power supply interface VCC2.

[0033] When the circuit is connected, the second power interface VCC2 is connected to an external DC power supply, and the voltage of the DC power supply is set according to the actual situation, such as 3.3V, 5V, 12V, 5V. In addition, the DC power supply can be obtained by converting AC power, for example, it can be converted by an AC-DC conversion chip. The second serial data input interface SI2 is connected to the serial data output interface SO, the second serial clock interface CLK2 is connected to the write pulse output interface WPO, and the third serial clock interface CLK3 is connected to the read pulse output interface RPO. Under the action of the synchronous clock signal sent by the write pulse output interface WPO, the input data received by the first serial data input interface SI is input one by one from the second serial data input interface SI2, and then under the action of the synchronous clock signal sent by the read pulse output interface RPO, the interface expansion output unit U2 obtains the complete multi-bit data output by the control chip, and then the multi-bit data is synchronously output to the load through the parallel data output interface Q1, such as synchronously output to the LED matrix, or output to the LCD liquid crystal screen.

[0034] Among them, in the currently working interface expansion output unit U2, if the data of the second serial data input interface SI2 is not equal to the data of the parallel data output interface Q1, the currently working interface expansion output unit U2 triggers an interrupt feedback signal to the control chip through the first interrupt feedback interface INT. After the control chip receives the interrupt feedback signal, it does not send an enable signal to the enable interface EN. At this time, the enable interface EN is in a disabled state, and the parallel data output interface Q1 is set to zero.

[0035] In addition, in this embodiment, after the control chip fails to detect the corresponding response signal, the control chip does not send an enable signal to the enable interface EN, and the enable interface EN is in a disabled state, and the parallel data output interface Q1 is set to zero. At the same time, when the first power interface VCC1 fails, the synchronous serial communication between the control chip and the serial bus communication control unit U1 is also in a failed state, and the enable interface EN is in a disabled state, and the parallel data output interface Q1 is set to zero. When the second power interface VCC2 fails, the interface expansion output unit U2 cannot work normally because it is in a power-off state. At this time, another group of serial bus communication control unit U1, interface expansion output unit U2 and logic output unit U3 can be used to transmit data. At the same time, in order to prevent the parallel data output interface Q1 of the failed interface expansion output unit U2 from being in an uncertain level state, a device that can be turned on and off can be set at the interface expansion output unit U2, such as a transistor, a transistor with a collector connected to the power supply and an emitter connected to the ground, and when the transistor is turned on, the output level of the interface expansion output unit U2 is zero.

[0036] In some optional embodiments, such as Figure 2 As shown, the interface expansion output unit U2 includes a multi-bit shift register U21, a multi-bit latch register U22, and a comparator module U23. Specifically, the shift register U21 includes a plurality of cascaded D flip-flops U211, the number of which is consistent with the number of bits of the parallel data output interface Q1, the input end of the first D flip-flop U211 is connected to the serial data output interface SO, and the clock ends of all D flip-flops U211 are connected to the write pulse output interface WPO. Optionally, the D flip-flop U211 can select a rising edge triggered D flip-flop or a falling edge triggered D flip-flop. In addition, in order to facilitate reset, a D flip-flop with reset can also be selected.

[0037] Exemplarily, taking a rising edge triggered D flip-flop as an example, when working, the write pulse output interface WPO outputs a clock signal, and at the rising edge of the clock, each D flip-flop U211 latches the corresponding bit in the data input by the serial data output interface SO.

[0038] The latch register U22 also includes multiple D flip-flops U221. The number of D flip-flops U221 is consistent with the number of bits of the parallel data output interface Q1. The input end of each D flip-flop U221 is respectively connected to the output end of each D flip-flop U211. The clock ends of all D flip-flops U221 are connected to the read pulse output interface RPO. Optionally, the D flip-flop U221 can select a rising edge triggered D flip-flop or a falling edge triggered D flip-flop. In addition, in order to facilitate resetting, a D flip-flop with reset can be selected.

[0039] For example, taking the rising edge triggered D flip-flop as an example, when each D flip-flop U221 latches the complete data input by the serial data output interface SO, the read pulse output interface RPO starts to output the clock signal, and at the rising edge of the clock, each D flip-flop U221 latches the complete data input by the serial data output interface SO.

[0040] In addition, in order to realize the enable function, the output end of each D flip-flop U212 is connected in series with an enable interface EN. Optionally, the enable interface EN can select an inverter Y0 with an enable end. When the enable end of the inverter Y0 is valid, the inverter Y0 works normally and inverts the input signal; when the enable end of the inverter Y0 is invalid, the output end of the inverter Y0 is set to a fixed level of zero.

[0041] The input end of the comparator module U23 is connected to the output end of the D flip-flop U211 and the D flip-flop U221 respectively, and the output end of the comparator module U23 is connected to the interrupt interface of the control chip. During operation, when the output value of any D flip-flop U211 is not equal to the output data of the corresponding D flip-flop U221, the output end of the comparator module U23 outputs an interrupt feedback signal, and the control chip disables the enable interface EN after receiving the interrupt feedback signal, thereby setting the output end of the inverter Y0 to a fixed level of zero. At this time, another group of serial bus communication control unit U1, interface expansion output unit U2 and OR logic output unit U3 can be used to transmit data, so as to achieve the role of cold backup.

[0042] In some optional embodiments, such as Figure 3As shown, the comparator module U23 includes a plurality of one-bit comparators U231 and an OR gate module U232. Specifically, the number of one-bit comparators U231 is consistent with the number of bits of the parallel data output interface Q1, and the one-bit comparator U231 has two input terminals and one output terminal, and the OR gate module U232 has the same number of input terminals and one output terminal as the output terminals of the one-bit comparator. When the circuit is connected, the two input terminals of each one-bit comparator U231 are respectively connected to the output terminal of a corresponding D flip-flop U211 and the output terminal of a corresponding D flip-flop U221, and the output terminal of the one-bit comparator U231 is connected to a corresponding input terminal of the OR gate module. When working, when the logic values ​​of the two input terminals of the one-bit comparator U231 are the same, its output terminal Y2 outputs a logic value of one, and when the logic values ​​of the two input terminals of the one-bit comparator U231 are different, its output terminal Y2 outputs a logic value of zero, and at this time, the output terminal of the OR gate module U232 triggers the interrupt function of the control chip.

[0043] Optionally, in order to prevent the comparator module U23 in a power-off state or the interface expansion output unit U2 in a power-off state from being in an uncertain level state, the one-bit comparator U231 can select a one-bit comparator with an enable end. When the enable end of the one-bit comparator is valid, the one-bit comparator works normally. When the enable end of the one-bit comparator is invalid, the output end of the one-bit comparator is set to a fixed level of zero.

[0044] In some optional embodiments, such as Figure 4 As shown, a one-bit comparator U231 includes an XOR gate module U2311 and an inverter U2312. The XOR gate module U2311 has two input ports and one output port. The input port of the inverter U2312 is connected to the output port of the XOR gate module U2311, and the output port of the inverter U2312 is connected to the input end of the OR gate module U232. When working, when the logic values ​​of the two input ends of the XOR gate module U2311 are the same, its output end outputs a logic value of zero, which is inverted by the inverter U2312 and becomes a logic value of one. Similarly, when the logic values ​​of the two input ends of the XOR gate module U2311 are different, its output end outputs a logic value of one, which is inverted by the inverter U2312 and becomes a logic value of zero, which triggers the interrupt of the control chip.

[0045] In some optional embodiments, such as Figure 1 and Figure 5 As shown, the IO interface expansion control circuit also includes an optical coupling isolation unit U4, the input end of the optical coupling isolation unit U4 is connected to the IO interface corresponding to the control chip, and the output end of the optical coupling isolation unit U4 is connected to the first serial data input SI interface. During operation, when the IO interface corresponding to the control chip outputs a high or low level, the output end of the optical coupling isolation unit U4 also synchronously outputs the corresponding high or low level.

[0046] In some optional embodiments, such as Figure 5 As shown, the optocoupler isolation unit U4 includes a switching current module U41 and an optocoupler U42. Specifically, the four interfaces of the optocoupler U4 are pin 1 (LED anode), pin 2 (LED cathode), pin 3 (collector of the photodetector) and pin 4 (emitter of the photodetector). When the circuit is connected, pin 1 of the optocoupler isolation unit U4 is connected to a power supply, such as a 15V power supply, pin 1 of the optocoupler isolation unit U4 is connected to an IO interface corresponding to the control chip, pin 3 of the optocoupler isolation unit U4 is connected to a power supply, such as a 5V power supply, and pin 4 of the optocoupler isolation unit U4 is connected to the first serial data input interface SI1.

[0047] In this embodiment, by setting the optical coupler U42, since the optical coupler U42 is a low-resistance element working in the current mode, it has a strong common-mode suppression capability, so the optical coupler U42 is used as a terminal isolation element in the signal transmission information, which can greatly improve the signal-to-noise ratio of the electronic system and improve the reliability of the work. Specifically in this circuit, since there is no direct electrical relationship between the control chip and the serial bus communication control unit U1, the radio frequency radiation or conducted radiation between the two cannot interfere with each other, thereby achieving the purpose of anti-interference and improving the reliability of the IO interface expansion control circuit.

[0048] In some optional embodiments, in order to prevent the IO interface corresponding to the control chip from being damaged by a large current, such as Figure 5 As shown, the switch current module U41 includes an NPN transistor U411, a diode U412, a first current limiting resistor U413, a second current limiting resistor U414, and a bias resistor U415. When the circuit is connected, the collector of the NPN transistor U411 is connected to the emitter of the photodetector of the optocoupler U42, the collector of the photodetector of the optocoupler U42 is connected to the power supply, the emitter of the NPN transistor U411 is grounded, the diode U412 is connected in series between the base of the NPN transistor U411 and the IO interface corresponding to the control chip, the first current limiting resistor U413 is connected in series between the base of the NPN transistor U411 and the diode U412, the second current limiting resistor U414 is connected in series between the collector of the photodetector of the optocoupler U42 and the power supply, and the bias resistor U415 is connected in series between the base of the NPN transistor U411 and the ground.

[0049] In this embodiment, when the IO interface corresponding to the control chip outputs a low level, the NPN transistor U411 is turned off, the light emitting diode of the optical coupler U42 is not turned on and does not emit light, and the photosensitive transistor of the optical coupler U42 is not turned on. When the IO interface corresponding to the control chip outputs a high level, the NPN transistor U411 is turned on, the light emitting diode of the optical coupler U42 is turned on and emits light, and the photosensitive transistor of the optical coupler U42 is turned on. Since the base current of the NPN transistor U411 is small, the current flowing through the IO interface corresponding to the control chip can be well controlled.

[0050] In some optional embodiments, when a combination of a group of serial bus communication control units U1, interface expansion output units U2, or logic output units U3 and optocoupler isolation units U4 performs data transmission, a second inverter Y1 (not shown in the drawings) with an enable end is provided between the input end of another group of corresponding optocoupler isolation units U4 and the IO interface corresponding to the control chip, and the enable end of the second inverter Y1 is connected to the IO interface corresponding to the control chip.

[0051] During operation, when one group of the serial bus communication control unit U1, the interface expansion output unit U2, or the combination of the logic output unit U3 and the optocoupler isolation unit U4 is transmitting data, the other group of corresponding optocoupler isolation units U4 needs to be in a non-operating state. At this time, the control chip controls the enable end of the second inverter Y1 to be in a disabled state, and the output end of the second inverter Y1 is set to zero. At this time, the corresponding optocoupler isolation unit U4 is in a non-operating state. When backup switching is required, the control chip controls the enable end of the second inverter Y1 to be in an enabled state.

[0052] In some optional embodiments, in order to avoid damage to electronic components when overcurrent occurs, an overcurrent protection unit FU (not shown in the drawings) is connected in series between the first power interface VCC1 and the power supply connected thereto, and an overcurrent protection unit FU (not shown in the drawings) is also connected in series between the second power interface VCC2 and the power supply connected thereto. Optionally, the overcurrent protection unit FU includes a fusible fuse. A fusible fuse is a safety device used to protect a circuit from overload and short circuit. It is usually composed of a conductor with an appropriate melting point. When the current in the circuit exceeds the rated current of the fuse, the conductor will melt due to excessive heat generated, thereby cutting off the circuit, preventing the current from continuing to flow, and protecting other components in the circuit from damage.

[0053] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An IO interface expansion control circuit, characterized in that: The IO interface expansion control circuit comprises: Two groups of serial bus communication control units are each provided with a chip select signal interface, a first serial clock interface, a response signal feedback interface, a first serial data input interface, a serial data output interface, a write pulse output interface, a read pulse output interface and a first power supply interface, wherein the chip select signal interface, the first serial clock interface, the response signal feedback interface and the first serial data input interface are used to connect to the IO interface corresponding to the control chip; Two groups of interface extension output units are each provided with a second serial data input interface, a second serial clock interface, a third serial clock interface, a parallel data output interface, a first interrupt feedback interface, an enable interface and a second power supply interface, wherein the second serial data input interface is connected to the serial data output interface, the second serial clock interface is connected to the write pulse output interface, the third serial clock interface is connected to the read pulse output interface, and the first interrupt feedback interface and the enable interface are used to connect to the IO interface corresponding to the control chip; An OR logic output unit, used for performing OR logic processing on the data of the two groups of parallel data output interfaces and outputting them in parallel; Among them, the first power interface and the second power interface are both used to connect to the first power supply, and when the response signal feedback interface does not generate a response signal and the enable interface is in a disabled state, the parallel data output interface is reset to zero; when the data of one group of the second serial data input interfaces is not equal to the data of the parallel data output interface, the corresponding first interrupt feedback interface triggers an interrupt feedback signal, and the control chip does not send an enable signal to the corresponding enable interface according to the interrupt feedback signal.

2. The IO interface expansion control circuit according to claim 1, characterized in that: The interface expansion output unit comprises: A multi-bit shift register, wherein an input end of the shift register is connected to the serial data output interface, and a clock end of the shift register is connected to the write pulse output interface; A multi-bit latch register, the number of bits is the same as that of the shift register, the input end of the latch register is connected to the output end of the shift register, the clock end of the latch register is connected to the read pulse output interface, wherein the output end of the latch register is connected in series with the enable interface; A comparator module, whose input end is respectively connected to the output end of the shift register and the output end of the latch register; When at least one bit of data at the output end of the shift register and the output end of the latch register are not equal, the output end of the comparator module outputs the interrupt feedback signal, and the control chip disables the enable interface according to the interrupt feedback signal.

3. The IO interface expansion control circuit according to claim 2, characterized in that: The comparator module includes a plurality of one-bit comparators and an OR gate module, wherein the number of the one-bit comparators is the same as the number of bits of the shift register, the one-bit comparator has two input terminals and one output terminal, the OR gate module has the same number of input terminals and one output terminal as the output terminals of the one-bit comparator, and the output terminal of the one-bit comparator is connected to the input terminal of the OR gate module; When the logic values ​​of the two input terminals of the one-bit comparator are the same, the output terminal thereof outputs a logic value of one; when the logic values ​​of the two input terminals of the one-bit comparator are different, the output terminal thereof outputs a logic value of zero.

4. The IO interface expansion control circuit according to claim 3, characterized in that: The one-bit comparator includes an XOR gate module and a first inverter, the XOR gate module has two input ports and one output port, the input port of the first inverter is connected to the output port of the XOR gate module, and the output port of the first inverter is connected to the input end of the XOR gate module.

5. The IO interface expansion control circuit according to claim 1, characterized in that: The IO interface expansion control circuit also includes an optocoupler isolation unit, an input end of the optocoupler isolation unit is connected to the IO interface corresponding to the control chip, and an output end of the optocoupler isolation unit is connected to the first serial data input interface.

6. The IO interface expansion control circuit according to claim 5, characterized in that: The optical coupling isolation unit comprises: A switch current module, the input end of which is connected to the IO interface corresponding to the control chip; An optical coupler, wherein an input end is connected to an output end of the switching current module, and an output end is connected to the first serial data input interface.

7. The IO interface expansion control circuit according to claim 6, characterized in that: The switching current module comprises: An NPN transistor, wherein the collector of the NPN transistor is connected to the emitter of the photodetector of the optical coupler, the collector of the photodetector of the optical coupler is used to connect to a second power supply, and the emitter of the NPN transistor is grounded; A diode is connected in series between the base of the NPN transistor and the IO interface corresponding to the control chip; A first current limiting resistor is connected in series between the base of the NPN transistor and the diode; a second current limiting resistor connected in series between the collector of the photodetector of the optical coupler and the first power supply; The bias resistor is connected in series between the base of the NPN transistor and the ground.

8. The IO interface expansion control circuit according to any one of claims 5 to 7, characterized in that: A second inverter with an enable terminal is provided between the input terminal of one group of the optical coupling isolation units and the IO interface corresponding to the control chip, and the enable terminal of the second inverter is connected to the IO interface corresponding to the control chip.

9. The IO interface expansion control circuit according to claim 1, characterized in that: An overcurrent protection unit is connected in series between the first power supply and the first power interface and the second power interface.

10. The IO interface expansion control circuit according to claim 9, characterized in that: The overcurrent protection unit includes a blown fuse.

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