Process mapping method of multiplexer logic, electronic equipment and medium

Abstract

The invention relates to the technical field of integrated circuits, in particular to a process mapping method of multiplexer logic, electronic equipment and a medium, and the process mapping method comprises the following steps: A1, decomposing a multiplexer to be mapped into a multiplexer tree; a2, obtaining all possible process mapping structures of each leaf node of the Lth level, and setting l = L-1; a3, obtaining all possible process mapping structures of each node of the first level, and obtaining an optimal combination structure of each node of the first level and a corresponding child node combination; and A4, if l is equal to 1, selecting an optimal target combination structure from the optimal combination structures corresponding to each possible process mapping structure of the nodes of the current lth level, determining a target process mapping structure of each node based on the optimal target combination structure, and if l is greater than 1, setting l to be equal to l-1, and returning to the step A3. According to the method, a reasonable process mapping mode can be selected, and the overall area and time delay of the FPGA are reduced as much as possible.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a process mapping method, electronic equipment and medium for multiplexer logic. Background Art

[0002] Multiplexers (Mux) are common components in digital systems, but they have high logic resource overhead. Field-programmable gate arrays (FPGAs) provide a variety of dedicated modules on-chip to narrow the performance gap between them and application-specific integrated circuits, such as dedicated multiplexers integrated with look-up tables (LUTs). If the multiplexers can be reasonably mapped to the FPGA, it will help reduce the overall area and latency. However, there are many types of resources on FPGAs, and some multiplexers have large structures. Therefore, there are many process mapping methods to map the multiplexers to the FPGA. It can be seen that how to choose a reasonable process mapping method to minimize the overall area and latency of the FPGA has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a process mapping method, electronic device and medium for multiplexer logic, which can select a reasonable process mapping method and reduce the overall area and delay of FPGA as much as possible.

[0004] According to a first aspect of the present invention, a process mapping method for a multiplexer logic is provided, comprising:

[0005] Step A1, decomposing the multiplexer to be mapped to generate a multiplexer tree, each node of the multiplexer tree corresponds to a multiplexer, and the multiplexer tree includes L levels;

[0006] Step A2, obtaining all possible process mapping structures of each leaf node of the Lth level, setting l=L-1, and executing step A3, wherein the process mapping structure is an implementation structure of the multiplexer corresponding to the node on the FPGA;

[0007] Step A3, obtaining all possible process mapping structures of each node at the lth level, and obtaining the optimal combination structure of each node at the lth level and the corresponding sub-node based on all possible process mapping structures of the sub-nodes corresponding to each node at the lth level, and recording the structure of the sub-node on which the optimal combination structure corresponding to each possible process mapping structure of each node at the lth level depends;

[0008] Step A4, determine whether l is equal to 1. If l is equal to 1, select the optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the node at the current l-th level, determine the target process mapping structure of each node based on the optimal target combination structure, and end the process. If l is greater than 1, set l=l-1 and return to step A3.

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the process mapping method, electronic device and medium of the multiplexer logic provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The present invention first decomposes the multiplexer to generate a multiplexer tree, and then obtains the process mapping structure of each leaf node from the bottom up, as well as the optimal combination of each process mapping structure of each non-leaf node and the corresponding child node, and finally selects the optimal target combination structure from the optimal combination of each process mapping structure of the root node. It is possible to select a reasonable process mapping method to minimize the overall area and delay of the FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a process mapping method for multiplexer logic provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a process mapping method for multiplexer logic, such as Figure 1 As shown, including:

[0017] Step A1: Decompose the multiplexer to be mapped to generate a multiplexer tree, each node of the multiplexer tree corresponds to a multiplexer, and the multiplexer tree includes L levels.

[0018] It should be noted that due to the limitation of hardware resources on FPAG, many large-scale multiplexers are difficult to map directly to FPGA. At one time, the multiplexer to be mapped can be decomposed to generate a multiplexer tree. Each node corresponds to a multiplexer with a smaller scale, which is convenient for mapping on FPGA. In the process of decomposing the multiplexer to be mapped to generate a multiplexer, the multiplexer can also be optimized.

[0019] Step A2, obtain all possible process mapping structures of each leaf node of the Lth level, set l=L-1, and execute step A3, wherein the process mapping structure is the implementation structure of the multiplexer corresponding to the node on the FPGA.

[0020] Among them, the multiplexer corresponding to each leaf node may have one or more process mapping structures on the FPGA. The present invention needs to retain all possible process mapping structures of each leaf node for subsequent selection of combination structures. All possible process mapping structures are structures that meet the hardware setting constraints.

[0021] Step A3, obtain all possible process mapping structures of each node at the lth level, and obtain the optimal combination structure of each node at the lth level and the corresponding sub-node based on all possible process mapping structures of the sub-nodes corresponding to each node at the lth level, and record the structure of the sub-node on which the optimal combination structure corresponding to each possible process mapping structure of each node at the lth level depends.

[0022] It should be noted that in step A3, each node of the first level may be a root node or a non-leaf node that is not a root node. The embodiment of the present invention adopts a bottom-up approach to obtain all possible process mapping structures of the multiplexer corresponding to each node layer by layer, and obtains the optimal combination of each non-leaf node in the combination structure with the corresponding child node under each industrial mapping structure, so as to facilitate the subsequent selection of the final optimal target combination structure.

[0023] Step A4, determine whether l is equal to 1. If l is equal to 1, select the optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the node at the current l-th level, determine the target process mapping structure of each node based on the optimal target combination structure, and end the process. If l is greater than 1, set l=l-1 and return to step A3.

[0024] It can be understood that when l=1, it means that the root node has been traversed. At this time, the optimal target combination structure is selected from the optimal combination structure corresponding to each possible process mapping structure of the root node. It can be understood that the optimal combination structure corresponding to each process mapping structure of the node at each level records the structure of the corresponding child node. Therefore, the target process mapping structure of each node can be directly determined based on the optimal target combination structure.

[0025] As an embodiment, the FPGA includes a plurality of configurable logic blocks (CLBs), and the hardware resources of each configurable logic block include 8 look-up tables (LUTs), 4 multiplexers F7, 2 multiplexers F8, and one multiplexer F9, wherein the maximum number of inputs of the look-up table is 6; it should be noted that multiplexers F7, multiplexers F8, and multiplexers F9 are dedicated modules in the FPGA, and the specific structures are not repeated here. A programmable logic block can directly implement a 1-to-1 selector, a 2-to-1 selector, a 4-to-1 selector, an 8-to-1 selector, a 16-to-1 selector, and a 32-to-1 selector. Specifically, the 1-to-1 selector can be implemented using a 1-input look-up table. A 2-to-1 selector can be implemented using a 3-input look-up table. A 4-to-1 selector can be implemented using a 6-input look-up table. An 8-to-1 selector can be implemented using two 6-input look-up tables and a multiplexer F7. The 16-to-1 selector can be implemented using four 6-input lookup tables, two multiplexers F7, and one multiplexer F8. The 32-to-1 selector can be implemented using eight 6-input lookup tables, four multiplexers F7, two multiplexers F8, and one multiplexer F9.

[0026] As an embodiment, the multiplexer tree satisfies: each non-leaf node corresponds to a 2-to-1 selector, the input of the 2-to-1 selector corresponding to the non-leaf node is the output of the multiplexer corresponding to the two child nodes of the non-leaf node, and all leaf nodes are first-class leaf nodes, second-class leaf nodes or third-class leaf nodes, wherein the first-class leaf node is a buffer leaf node, and the input and output of the multiplexer corresponding to the buffer leaf node are the same, and the second-class leaf node is a regular leaf node, and the multiplexer corresponding to the regular leaf node does not have any pair of optimizable data, nor does it exist in an indeterminate state (Don't Care), that is, there is no optimization space, so there is no need to further decompose the regular leaf node. The third-class leaf node is a constant leaf node, and the input of the multiplexer corresponding to the constant leaf node is all constant. It should be noted that there is optimization space when there are constants, indeterminate states and the same input signals. It should be noted that in the process of decomposing the multiplexer to be mapped to generate the above-mentioned multiplexer tree, the same data signal, constant signal and indeterminate state signal have been optimized, and the logic of the multiplexer has been simplified as much as possible.

[0027] Specifically, the step A1 specifically includes:

[0028] Step A11: Obtain the selection signal set corresponding to the multiplexer to be mapped {S 1 ,S 2 ,…,S n ,…,S N},S n is the nth selection signal, the value range of n is 1 to N, and N is the total number of selection signals.

[0029] Step A12: traverse each S n , if S n If the selection signal needs to be directly connected to the ground or the power supply, then S n Connect directly to ground or power supply, and connect S n Delete from the selection signal set, update N=N-1, and execute step A13 after the traversal is completed.

[0030] Step A13: Obtain the data signal set corresponding to the multiplexer to be mapped {D 1 ,D 2 ,…,D m ,…,D M}, D m is the mth data signal, the value range of m is 1 to M, M is the number of data signals, M = 2 N .

[0031] Step A14: If all Dm All data signals are driven by constants, or all data signals are indeterminate signals, or all D m If both are connected to the same signal source, the logic optimization process ends; otherwise, execute step A15.

[0032] Step A15: Decompose the multiplexer to be mapped to generate a multiplexer tree.

[0033] Step A16: Generate an optimized multiplexer based on the multiplexer tree.

[0034] As an embodiment, the step A15 includes:

[0035] Step A151: Set the multiplexer to be mapped as a multiplexer to be decomposed, the number of data signals of the multiplexer to be decomposed is X=M, and {D 1 ,D 2 ,…,D m ,…,D M} is set as the currently selected signal set and executes step A152.

[0036] Step A152: Select a decomposed selection signal S from the current selection signal set. k , S k Delete from the current selection signal set, the value of k ranges from 1 to N.

[0037] Step A153: Decompose the multiplexer to be mapped into two X / 2 selectors P 1 k and P 2 k , P 1 k and P 2 k Share the selection signal in the current selection signal set, P 1 k The data signal is the S of the multiplexer to be mapped. k When it is 0, the selected data signal, P 2 k The data signal is the S of the multiplexer to be mapped. k When 1, the data signal is selected.

[0038] Step A154: If P 1 k and P 2 k If one of the X / 2 selector inputs is an indeterminate signal, then return the other X / 2 selector, otherwise, return two X / 2 selectors;

[0039] Step A155, determine whether the returned X / 2 selectors are leaf nodes. If all are, generate a multiplexer tree. Otherwise, set each X / 2 selector as a multiplexer to be decomposed, update X=X / 2, and return to step A152.

[0040] In the process of decomposing the multiplexer to be optimized to generate a multiplexer tree, only when the signals assigned to the same multiplexer meet the optimization conditions, that is, a pair of data are the same signal or are both constants or are both indeterminate states, can the optimization space be created. Therefore, in this process, how to choose to decompose the selection signal to obtain a larger optimization space as much as possible is particularly important. As an embodiment, the step A152 includes:

[0041] Step A1521, obtain S-based k Decomposition P 1 k The data signal set is {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k}, P 2 k The data signal set is {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k}, where Q i k P 1 k The i-th data signal in the data signal set, R i k P 2 k The i-th data signal in the data signal set, i ranges from 1 to X / 2, Q i k and R i k The corresponding selection signals are the same.

[0042] Step A1522, traverse {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} and {R1 k , R 2 k ,…,R i k ,…,R X / 2 k}, if Q i k and R i k Satisfy Q i k =R i k or Q i k , R i k All are indeterminate or Q i k , R i k are all constants, then (Q i k ,R i k ) is determined as an optimizable data pair, and {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k} can optimize the data pair (Q i k ,R i k ) k .

[0043] Step A1523: E k The S corresponding to the smallest k value k Determine the decomposition selection signal S k .

[0044] Among them, E k The smaller the value, the more k The smaller the optimization space destroyed by the decomposition.

[0045] As an embodiment, in step A1523, if E k There are multiple minimum k values, then for E kThe smallest value {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k}implement:

[0046] Step A15231, traverse {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k}, if Q i k , Q j k Satisfy Q i k =Q j k or Q i k , Q j k All are indeterminate or Q i k , R i k are all constants, then (Q i k ,Q j k ) is determined as an optimizable data pair, where Q j k For {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k} the jth data signal in .

[0047] Traverse {R 1 k , R 2 k ,…,R i k ,…,R X / 2k If R i k , R j k Satisfy R i k =R j k or R i k , R j k All are indeterminate or R i k , R i k are all constants, then (R i k ,R j k ) is determined as an optimizable data pair, where R j k For {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k} the jth data signal in .

[0048] The value range of j is 1 to X / 2, i≠j.

[0049] Step A15232, obtain {Q 1 k , Q 2 k ,…,Q i k ,…,Q X / 2 k The number of optimizable data pairs in QE k , and {R 1 k , R 2 k ,…,R i k ,…,R X / 2 k The number of optimizable data pairs RE in} k .

[0050] Step A15233, obtain each group of QE k and RE k The absolute value of the difference between QE k and RE k The k value with the largest absolute value of the difference between k Determine the decomposition selection signal S k.

[0051] Among them, QE k and RE k The larger the absolute value of the difference, the larger the optimization space of the multiplexer obtained after decomposition is on the basis of destroying the same optimization space.

[0052] If in step A15233, QE k and RE k If there are multiple k values ​​with the largest absolute value of the difference, then QE k and RE k The S with the largest absolute value of the difference or the largest k value among the smallest k k Determine the decomposition selection signal S k .

[0053] As an embodiment, the step A2 includes:

[0054] Step A21: If the leaf node is a first-type leaf node, the process mapping structure of the leaf node is set to a net or a 1-input lookup table.

[0055] Step A22: If the leaf node is a second-type leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 5. If so, directly generate the process mapping structure of the leaf node based on a programmable logic block. Otherwise, execute step A23.

[0056] Step A23, decompose F into F = 5 × g + b, where g is the number of layers of 32-to-1 selectors, b is the number of selection signals of the last layer of selectors, b is less than 5, and the leaf node is mapped to the g-layer 32-to-1 selector connected to a layer of 2 b The selectors for 1 are arranged in a pyramid structure, 2 b Each input of the selector that selects 1 corresponds to the output of a selector that selects 32 from 1. b The selector that selects 1 corresponds to a programmable logic block.

[0057] Step A24: If the leaf node is a third-type leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 6. If so, directly map it to a lookup table of F input; otherwise, execute step A25.

[0058] Step A25, set H = F-4, and the multiplexer corresponding to the leaf node is equivalent to 2 H Select 1, select 2 H The structure of the selector that selects 1 is determined as the mapping structure corresponding to the leaf node.

[0059] It should be noted that for a regular leaf node, that is, a second-class leaf node, if it is implemented in a tree structure, the bottom is all set to a 6-input lookup table. When implementing a constant leaf node, that is, a third-class leaf node, if F≤6, a 6-input lookup table can be directly used to implement it. When F>6, a 6-input lookup table is not enough to implement it, so it can be implemented in a form similar to a regular leaf node, which is also a tree structure. When used on a regular node, the 6-input lookup table at the bottom implements 2 2 Option 1: When used on a constant leaf node, the 6-input lookup table at the bottom implements 2 6 Option 1: If the regular leaf node and the constant leaf node have the same structure, then except for the 6-input lookup table at the bottom, the mapping structure of the other parts is the same. Therefore, the difference between the two is that the 6-input lookup table at the bottom represents 2 2 Choose 1 and 2 6 Choose 1, the difference between the two is 2 4 Therefore, in step A25, H=F-4 is set, and the multiplexer corresponding to the leaf node is equivalent to 2 H A selector that chooses 1.

[0060] As an embodiment, in step A23, if b≠0, jump to step B23: decompose F into F=5×(g-1)+c+d, where g-1 is the number of levels of the 32-to-1 selector, d is the number of selection signals of the second-to-last layer selector, d is the number of selection signals from the last layer, c is less than 5, d is less than 5, and the leaf node is mapped to a (g-1) layer 32-to-1 selector connected to a layer 2 c Select the selector 1, and then connect a layer 2 d Selector 1, each 32 selector 1, 2 c Selector 1, 2 d Each selector that selects 1 corresponds to a programmable logic block, and then step A24 is executed. It should be noted that the mapping structure corresponding to F=5×(g-1)+c+d will make the subsequent combination structure have more possible mapping schemes compared to the structure of F=5×g+b, making the mapping structure corresponding to the entire tree more balanced and not introducing additional delay.

[0061] In step A3, all non-leaf nodes are processed. All non-leaf nodes are 2-choose-one selectors, and the input always comes from the output of another node. Due to hardware limitations, some mapping structures have dependencies on the mapping structure of the input node. As an embodiment, in step A3, all possible process mapping structures of each node at the lth level are obtained, including:

[0062] Step A31: Set the process mapping structure of the lth level node to a three-input lookup table. The lookup table structure has no requirements for the mapping structure of the input nodes.

[0063] Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a lookup table, the process mapping structure of the node is set to the multiplexer F7.

[0064] Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is the multiplexer F7, the process mapping structure of the node is set to the multiplexer F8.

[0065] Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is the multiplexer F8, the process mapping structure of the node is set to the multiplexer F9.

[0066] When the last component of a mapping structure of an input node corresponding to the l-th level node is a 2-to-1 selector, the node and the corresponding last component are merged into a 5-input lookup table.

[0067] When the last components of the mapping structure of the two input nodes corresponding to the l-th level node are both 2-to-1 selectors, and the selection signals of the two 2-to-1 selectors are the same, the l-th level node and the two 2-to-1 selectors are merged into a 6-input lookup table.

[0068] As an embodiment, in step A2 and step A3, if the top of the mapping structure corresponding to the current node is multiplexer F7, it is allowed to replace the top multiplexer F7 with a 3-input lookup table; if the top of the mapping structure corresponding to the current node is multiplexer F8 or F9, it is allowed to replace the top multiplexer F8 or F9 with a 6-input lookup table. The above replacement schemes can provide more possibilities for subsequent combination structures and can reduce the overall delay to a greater extent.

[0069] As an embodiment, in step A3 and step A4, when selecting the optimal combination structure from multiple candidate combination structures, the following steps are performed:

[0070] Step A10: Obtain the number of lookup tables on the critical path of each candidate combination structure. The number of lookup tables on the critical path is proportional to the delay.

[0071] Among them, the critical path is the path containing the largest number of lookup tables in the candidate combination structure.

[0072] Step A20, determine whether there is only one candidate combination structure with the smallest number of lookup tables for the critical path. If so, determine the candidate combination structure with the smallest number of lookup tables for the critical path as the optimal candidate combination structure. Otherwise, only retain the candidate combination structure with the smallest number of current lookup tables and execute step A30.

[0073] Step A30: Obtain the total number of lookup tables for each candidate combination structure, where the total number of lookup tables is proportional to the area.

[0074] Step A40, determine whether there is only one candidate combination structure with the smallest total number of lookup tables. If so, determine the candidate combination structure with the smallest total number of lookup tables as the optimal candidate combination structure. Otherwise, only retain the candidate combination structure with the smallest total number of current lookup tables and execute step A50.

[0075] Step A50, obtaining the total number of dedicated multiplexers of each candidate combination structure, wherein the dedicated multiplexers include multiplexer F7, multiplexer F8 and multiplexer F9, and the total number of multiplexers is proportional to the area.

[0076] Step A60, determine whether there is only one candidate combination structure with the smallest total number of multiplexers. If so, determine the candidate combination structure with the smallest total number of dedicated multiplexers as the optimal candidate combination structure. Otherwise, determine the first or last generated candidate combination structure among the candidate combination structures with the smallest total number of multiplexers as the optimal candidate combination structure.

[0077] It should be noted that in step A3, for each possible process mapping structure of each node at the first level, steps A10 to A60 need to be executed to obtain the corresponding optimal combination structure, and the candidate combination structure is specifically all possible combination structures constructed by each possible process mapping structure of each node and the corresponding child node. The optimal candidate combination structure is the optimal combination structure of each possible process mapping structure of each node at the first level and the corresponding child node. In step A4, the candidate combination structure is the optimal combination structure corresponding to all possible process mapping structures of the root node, and the optimal candidate combination structure is the optimal target combination structure.

[0078] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0079] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0080] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0081] The embodiment of the present invention first decomposes the multiplexer to generate a multiplexer tree, and then obtains the process mapping structure of each leaf node from the bottom up, as well as the optimal combination of each process mapping structure of each non-leaf node and the corresponding child node, and finally selects the optimal target combination structure from the optimal combination of each process mapping structure of the root node. It is possible to select a reasonable process mapping method to minimize the overall area and latency of the FPGA.

[0082] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A process mapping method for multiplexer logic, characterized in that: include: Step A1, decomposing the multiplexer to be mapped to generate a multiplexer tree, each node of the multiplexer tree corresponds to a multiplexer, and the multiplexer tree includes L levels; Step A2, obtaining all possible process mapping structures of each leaf node of the Lth level, setting l=L-1, and executing step A3, wherein the process mapping structure is an implementation structure of the multiplexer corresponding to the node on the FPGA; Step A3, obtaining all possible process mapping structures of each node at the lth level, and obtaining the optimal combination structure of each node at the lth level and the corresponding sub-node based on all possible process mapping structures of the sub-nodes corresponding to each node at the lth level, and recording the structure of the sub-node on which the optimal combination structure corresponding to each possible process mapping structure of each node at the lth level depends; Step A4, determine whether l is equal to 1. If l is equal to 1, select the optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the node at the current l-th level, determine the target process mapping structure of each node based on the optimal target combination structure, and end the process. If l is greater than 1, set l=l-1 and return to step A3.

2. The method according to claim 1, characterized in that The FPGA includes multiple programmable logic blocks, and the hardware resources of each programmable logic block include 8 lookup tables, 4 multiplexers F7, 2 multiplexers F8 and one multiplexer F9, wherein the maximum number of inputs of the lookup table is 6; one programmable logic block can directly implement a 1-to-1 selector, a 2-to-1 selector, a 4-to-1 selector, an 8-to-1 selector, a 16-to-1 selector and a 32-to-1 selector.

3. The method according to claim 2, characterized in that The multiplexer tree satisfies the following conditions: each non-leaf node corresponds to a 2-to-1 selector, the input of the 2-to-1 selector corresponding to the non-leaf node is the output of the multiplexers corresponding to the two child nodes of the non-leaf node, and all leaf nodes are first-class leaf nodes, second-class leaf nodes, or third-class leaf nodes, wherein the input and output of the multiplexers corresponding to the first-class leaf nodes are the same, there is no optimization space for the multiplexers corresponding to the second-class leaf nodes, and the inputs of the multiplexers corresponding to the third-class leaf nodes are all constants.

4. The method according to claim 3, characterized in that The step A2 comprises: Step A21: if the leaf node is a first-type leaf node, the process mapping structure of the leaf node is set to a lookup table with a line or 1 input; Step A22: if the leaf node is a second type leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 5. If so, directly generate a process mapping structure of the leaf node based on a programmable logic block. Otherwise, execute step A23. Step A23, decompose F into F = 5 × g + b, where g is the number of layers of 32-to-1 selectors, b is the number of selection signals of the last layer of selectors, b is less than 5, and the leaf node is mapped to the g-layer 32-to-1 selector connected to a layer of 2 b Selector 1, each 32 selector 1, 2 b The selector that selects 1 corresponds to a programmable logic block; Step A24: if the leaf node is a third type leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 6. If so, directly map it to a lookup table input by F. Otherwise, execute step A25. Step A25, set H = F-4, and the multiplexer corresponding to the leaf node is equivalent to 2 H Select 1, and 2 H The structure of the selector that selects 1 is determined as the mapping structure corresponding to the leaf node.

5. The method according to claim 4, characterized in that In step A23, if b≠0, jump to step B23: decompose F into F=5×(g-1)+c+d, where g-1 is the number of levels of the 32-to-1 selector, d is the number of selection signals of the second-to-last selector, and d is the number of selection signals from the last layer. If c is less than 5 and d is less than 5, the leaf node is mapped to a (g-1)-layer 32-to-1 selector connected to a layer of 2 c Select the selector 1, and then connect a layer 2 d Selector 1, each 32 selector 1, 2 c Selector 1, 2 d Each selector that selects 1 corresponds to a programmable logic block, and then step A24 is executed.

6. The method according to claim 3, characterized in that In step A3, all possible process mapping structures of each node at level l are obtained, including: Step A31, setting the process mapping structure of the l-th level node to a 3-input lookup table; Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the node of the first level is a lookup table, the process mapping structure of the node is set to a multiplexer F7; Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the node of the first level is the multiplexer F7, the process mapping structure of the node is set to the multiplexer F8; Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the node of the first level is the multiplexer F8, the process mapping structure of the node is set to the multiplexer F9; When the last component of the mapping structure of an input node corresponding to the node of the first level is a 2-to-1 selector, the node and the corresponding last component are combined into a 5-input lookup table; When the last components of the mapping structure of the two input nodes corresponding to the l-th level node are both 2-to-1 selectors, and the selection signals of the two 2-to-1 selectors are the same, the l-th level node and the two 2-to-1 selectors are merged into a 6-input lookup table.

7. The method according to claim 4 or 6, characterized in that: In step A2 and step A3, if the top of the mapping structure corresponding to the current node is multiplexer F7, it is allowed to replace the top multiplexer F7 with a 3-input lookup table; if the top of the mapping structure corresponding to the current node is multiplexer F8 or F9, it is allowed to replace the top multiplexer F8 or F9 with a 6-input lookup table.

8. The method according to claim 1, characterized in that: In step A3 and step A4, when selecting the optimal combination structure from multiple candidate combination structures, the following steps are performed: Step A10, obtaining the number of lookup tables on the critical path of each candidate combination structure, where the number of lookup tables on the critical path is proportional to the delay; Step A20, determining whether there is only one candidate combination structure with the smallest number of lookup tables for the critical path; if so, determining the candidate combination structure with the smallest number of lookup tables for the critical path as the optimal candidate combination structure; otherwise, retaining only the candidate combination structure with the smallest number of current lookup tables, and executing step A30; Step A30, obtaining the total number of lookup tables for each candidate combination structure, where the total number of lookup tables is proportional to the area; Step A40, determining whether there is only one candidate combination structure with the smallest total number of lookup tables, if so, determining the candidate combination structure with the smallest total number of lookup tables as the optimal candidate combination structure, otherwise, only retaining the candidate combination structure with the smallest total number of current lookup tables, and executing step A50; Step A50, obtaining the total number of dedicated multiplexers of each candidate combination structure, wherein the dedicated multiplexers include multiplexers F7, multiplexers F8 and multiplexers F9, and the total number of multiplexers is proportional to the area; Step A60, determine whether there is only one candidate combination structure with the smallest total number of multiplexers. If so, determine the candidate combination structure with the smallest total number of dedicated multiplexers as the optimal candidate combination structure. Otherwise, determine the first or last generated candidate combination structure among the candidate combination structures with the smallest total number of multiplexers as the optimal candidate combination structure.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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