Modeling method for radiation-proof square gate-all-around MOSFET semiconductor device

Abstract

A modeling method for an anti-radiation square gate-all-around MOSFET semiconductor device belongs to the field of microelectronic device modeling, and comprises the following steps: (1) extracting key process parameters of a straight gate MOSFET semiconductor device through a factory PDK library; (2) establishing a physical model of the trapezoidal gate MOSFET semiconductor device according to the process parameters; (3) determining a geometric structure and an equivalent sub-circuit topology of the radiation-proof square gate-all-around MOSFET semiconductor device; (4) according to the physical model and the circuit topology, extracting part of important structure topology characteristic parameters of the model in a back-stepping manner; and (5) establishing a complete set of complete BSIM3V3.2 model in combination with other model process parameters. According to the modeling method, the ID-VG characteristic error of N-type MOSFET simulation and TCAD numerical calculation comparison is smaller than 5%, the performance of the anti-radiation semiconductor device can be accurately reflected, the delay between semiconductor device simulation and a semiconductor process is overcome, and a reliable research basis is provided for early circuit design and technical development based on the anti-radiation semiconductor device.

Description

Technical Field

[0001] The invention belongs to the field of semi-microelectronic device modeling, in particular to a radiation-resistant square-ring gate MOSFET semiconductor device modeling method, and in particular to a SPICE modeling method for radiation-resistant semiconductor devices. Background Art

[0002] Integrated circuits are very important in the fields of aerospace and nuclear physics. They are often exposed to various radiations that may negatively affect the performance and reliability of integrated circuits. In these environments, we need to adopt radiation-hardened design techniques to ensure the high precision and reliability of integrated circuits. The application of integrated circuits in the fields of aerospace and nuclear physics faces the challenges of various radiations, which may change the electrical properties of semiconductor materials in integrated circuits, causing logical operation errors or permanent damage. For example, the threshold voltage of a MOSFET may change due to the accumulation of charge caused by radiation, thus affecting the current characteristics within the device. In addition to the direct effects of radiation, integrated circuits also need to resist the effects of electromagnetic fields caused by radiation. These electromagnetic fields may generate noise in the circuit and cause output signal errors. In order to reduce the effects of radiation, researchers have developed various radiation-hardened integrated circuit design techniques, including the use of radiation-stable materials, and designing circuits with redundancy, or using error-correcting codes and radiation-tolerant memories to reduce radiation-induced errors. These techniques ensure that integrated circuits can still work properly under high levels of radiation. The development of radiation-hardened integrated circuits is a very fast-paced field, with new research and development to improve their radiation resistance and overall performance. As the demand for integrated circuits in aerospace and nuclear physics applications continues to increase, the demand for radiation-hardened designs is also increasing. In summary, the role of integrated circuits in the fields of aerospace and nuclear physics is very important, and their radiation resistance is a major issue. By developing radiation-resistant integrated circuit designs, researchers can ensure that integrated circuits can still work properly in the harshest environments. Continued research and development will help promote the development of technology to ensure that integrated circuits continue to play a key role in aerospace and nuclear physics applications. In order to ensure the reliability of integrated circuits in the aerospace field, radiation-resistant design is necessary. Researching radiation-resistant technology is crucial to meet the needs of space environment applications. This can effectively alleviate the impact of radiation on the function of integrated circuits. Therefore, the importance of radiation-resistant square ring gate MOSFET semiconductor devices in the above integrated circuits is self-evident.

[0003] The existing modeling methods usually include physical effect parameters, process parameters, general parameters, simulation parameters obtained by testing, and other fitting parameters used for calculation, etc. However, most of the existing modeling methods and parameter extraction methods are aimed at improving and perfecting the prepared radiation-resistant square-ring gate MOSFET semiconductor devices. There are few model building and extraction methods for radiation-resistant square-ring gate MOSFET semiconductor devices that have not yet been mass-produced. The modeling and process feature extraction methods that combine TCAD numerical simulation verification and layout design rules are even more scarce. Therefore, most of the existing modeling methods have a certain process delay, making it difficult to predict the performance of radiation-resistant square-ring gate MOSFET semiconductor devices, and cannot play an auxiliary guiding role in the early research and development of radiation-resistant integrated circuit design. Summary of the invention

[0004] The purpose of the present invention is to provide a modeling method for radiation-resistant square-ring-gate MOSFET semiconductor devices. The method is based on the BSIM3V3.2 device model and is used for simulation of radiation-resistant square-ring-gate semiconductor devices. The method can predict the performance of radiation-resistant square-ring-gate MOSFET semiconductor devices before the process is implemented, and provide a research basis and auxiliary guidance for early circuit design and technology development based on radiation-resistant square-ring-gate MOSFET semiconductor devices.

[0005] The technical solution adopted by the present invention to achieve the above-mentioned purpose is:

[0006] A radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method includes the following steps:

[0007] 1) Obtain key process parameters of direct-gate MOSFET semiconductor devices;

[0008] 2) Establishing an equivalent physical model of a trapezoidal gate semiconductor device based on key process parameters;

[0009] 3) Based on the trapezoidal gate semiconductor device, construct the geometric structure and equivalent sub-circuit topology of the radiation-resistant square-ring gate MOSFET semiconductor device;

[0010] 4) Based on the equivalent physical model and equivalent subcircuit topology, extract the important structural topological characteristic parameters of the radiation-resistant square-ring gate MOSFET semiconductor device model;

[0011] 5) Extract other model process parameters of the square-ring gate MOSFET semiconductor device, and use important structural topological characteristic parameters for simulation to obtain a radiation-resistant square-ring gate MOSFET semiconductor device model.

[0012] The key process parameters include: the gate length L of the straight-gate device and the active area width W of the drain of the straight-gate device.

[0013] In the step 2), the equivalent physical model is determined by the following formula:

[0014]

[0015] Among them, W trapezoid is the equivalent active area width of the trapezoidal gate, α is the bottom angle of the trapezoidal gate, L is the gate length of the straight gate device, and W is the active area width of the drain of the straight gate device.

[0016] The step 3) is specifically as follows:

[0017] The ring-gate semiconductor device is equivalent to four sub-devices with the same electrical performance and indicators which are equally divided along the diagonal line. Each trapezoidal gate semiconductor device is used as a sub-device, and they are connected in parallel to construct an equivalent sub-circuit topology of a radiation-resistant square ring-gate MOSFET semiconductor device.

[0018] In step 4), the important structural topological characteristic parameters include: the trapezoidal gate width W eq , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, number of parallel tubes m, where:

[0019]

[0020] PD=W eff

[0021] PS=2·W eff +4·L eff +2·L S

[0022]

[0023]

[0024]

[0025] Among them, L eff is the effective channel length of the straight-gate device, W eff is the effective active area width of the drain of the straight-gate device, L S It is the length of the source active region in the channel direction of each sub-device component.

[0026] The L eff and W eff Specifically:

[0027]

[0028]

[0029] Where, L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and L INT is the straight gate channel length offset fitting parameter, L L is the channel length correlation coefficient of the straight gate channel length offset, L W is the channel width correlation coefficient of the straight gate channel length offset, L WL is the length-width cross-term coefficient of the straight gate channel length offset, L LN is the channel length-dependent power of the straight gate channel length offset, L WN is the power of the channel width related to the offset of the straight gate channel length, W INT is the straight gate channel width offset fitting parameter, W L is the channel length correlation coefficient of the straight gate channel width offset, W W is the channel width correlation coefficient of the straight gate channel width offset, W WL is the length-width cross-term coefficient of the straight gate channel width offset, W LN is the channel length-dependent power of the straight gate channel width offset, W WN is the channel width-dependent power of the straight gate channel width offset.

[0030] In the step 5), other model process parameters are extracted using a BSIM3V3.2-specific extraction algorithm.

[0031] The present invention has the following beneficial effects and advantages:

[0032] The present invention can accurately simulate the performance of radiation-resistant semiconductor devices based on physical models, and compares the performance of N-type MOSFET simulation with TCAD numerical calculation. D -V G The characteristic error can be less than 5%, which can accurately reflect the performance of radiation-resistant semiconductor devices, overcome the delay between semiconductor device simulation and semiconductor process, and provide a reliable research basis and effective auxiliary guidance for early circuit design and technology development based on radiation-resistant semiconductor devices. It can improve the simulation verification of circuit design and provide support for chip design; at the same time, it can meet the needs of efficient circuit design and development and provide direction for the development of radiation-resistant semiconductor processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of an implementation method of the radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method of the present invention.

[0034] Figure 2 It is a schematic diagram of the planar structure of a radiation-resistant square-gate-all-around MOSFET semiconductor device in the prior art.

[0035] Figure 3It is a schematic diagram of the equivalent sub-circuit topology structure of the radiation-resistant square-gate-ring MOSFET semiconductor device of the present invention.

[0036] Figure 4 The present invention is a flowchart of the steps of a specific embodiment of the method for modeling a radiation-resistant square-gate-ring MOSFET semiconductor device.

[0037] Figure 5 It is a schematic diagram of the EDA layout structure of the radiation-resistant square-ring-gate MOSFET semiconductor device of the present invention.

[0038] Figure 6 It is a schematic diagram of the TCAD model structure of the radiation-resistant square-ring-gate MOSFET semiconductor device of the present invention.

[0039] Figure 7 The semiconductor device modeling method provided in the specific embodiment of the present invention is used to simulate the I / V characteristic curve of a 0.35 μm radiation-resistant square-gate-all-around NMOSFET semiconductor device.

[0040] Among them: 2. Radiation-resistant square-gate-all-around MOSFET semiconductor device, 21. Drain region of n-type implanted active region of radiation-resistant square-gate-all-around MOSFET semiconductor device, 22. Gate oxide region of radiation-resistant square-gate-all-around MOSFET semiconductor device, 23. Source region of n-type implanted active region of radiation-resistant square-gate-all-around MOSFET semiconductor device, 24. Peripheral field oxide region of radiation-resistant square-gate-all-around MOSFET semiconductor device, 5. EDA layout of radiation-resistant square-gate-all-around MOSFET semiconductor device, 51. Drain region of n-type implanted active region of radiation-resistant square-gate-all-around MOSFET semiconductor device layout, 52. Gate oxide region of radiation-resistant square-gate-all-around MOSFET semiconductor device layout Layer region, 53. Source region of the n-type implanted active region of the radiation-resistant square-ring-gate MOSFET semiconductor device layout, 54. NBL layer region of the radiation-resistant square-ring-gate MOSFET semiconductor device layout, 55. Source region of the p-type implanted active region of the radiation-resistant square-ring-gate MOSFET semiconductor device layout, 6. TCAD model of the radiation-resistant square-ring-gate MOSFET semiconductor device, 61. Drain region of the radiation-resistant square-ring-gate MOSFET semiconductor device, 62. Channel region of the radiation-resistant square-ring-gate MOSFET semiconductor device, 63. Source region of the radiation-resistant square-ring-gate MOSFET semiconductor device, 64. Substrate region of the radiation-resistant square-ring-gate MOSFET semiconductor device. DETAILED DESCRIPTION

[0041] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0042] The radiation-resistant square-ring-gate MOSFET semiconductor device modeling method provided in this specific embodiment is based on the BSIM3V3.2 device model and is used for simulation of radiation-resistant semiconductor devices.

[0043] Figure 1 A flow chart of the steps of the radiation-resistant square-gate-ring MOSFET semiconductor device modeling method provided by the present invention.

[0044] like Figure 1 to Figure 3 As shown, the radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method provided in this specific embodiment includes the following steps:

[0045] Step S1: extract key process parameters of a direct-gate MOSFET semiconductor device through a foundry PDK library.

[0046] In this step, the key process parameters extracted from the foundry PDK library are physical parameters, which are pre-set according to the characteristic dimensions of the direct-gate MOSFET semiconductor device, including the transistor gate length L, the active area width W of the drain, and the physical gate oxide layer thickness T. ox , Source / Drain Junction Depth X j wait.

[0047] Step S2: establishing a physical model of a trapezoidal gate semiconductor device according to the process parameters.

[0048] In this step, according to the direct gate design corresponding to the standard CMOS process of the foundry PDK library involved and the extraction of relevant process parameters, an equivalent physical model of the trapezoidal gate MOSFET semiconductor device can be established.

[0049]

[0050] Determine, where: W trapezoid is the equivalent active area width of the trapezoidal gate, α is the bottom angle of the trapezoidal gate, when considering the square ring gate structure, α is 45°, the gate length of the straight gate device is L, and the active area width of the drain of the straight gate device is W.

[0051] Step S3: clarify the geometric structure and equivalent sub-circuit topology of the radiation-resistant square-gate-all-around MOSFET semiconductor device.

[0052] In this step, based on the geometric structure of the device and the equivalent sub-circuit topology, the square device is divided equally along the diagonal into four sub-device components with the same electrical performance and indicators. The ring-gate device can be equivalent to four trapezoidal gate semiconductor devices, and the sub-circuit structure of the radiation-resistant square ring-gate MOSFET semiconductor device can be constructed in parallel.

[0053] Step S4: Based on the physical model and circuit topology, reversely extract some important structural topological characteristic parameters of the model.

[0054] In this step, the physical model is used to determine important equivalent parameters, including the trapezoidal gate width W eq , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, number of parallel tubes m.

[0055] In this step, the equivalent trapezoidal gate width W eq By formula

[0056]

[0057] Determine, where: L eff is the effective channel length of the straight-gate device, W eff is the effective active area width of the drain of a straight-gate device.

[0058] In this step, the effective channel length L of the straight gate device eff By formula

[0059]

[0060] Determine, where: To improve the calculation accuracy of the model, L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and L INT is the straight gate channel length offset fitting parameter extracted from the foundry process PDK library, L L is the channel length correlation coefficient of the straight gate channel length offset, L W is the channel width correlation coefficient of the straight gate channel length offset, L WL is the length-width cross-term coefficient of the straight gate channel length offset, L LN is the channel length-dependent power of the straight gate channel length offset, L WN is the channel width-dependent power of the straight gate channel length offset.

[0061] In this step, the effective channel width W of the straight gate device eff By formula

[0062]

[0063] Determine, where: L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and W INT is the straight gate channel width offset fitting parameter extracted from the foundry process PDK library, W L is the channel length correlation coefficient of the straight gate channel width offset, W W is the channel width correlation coefficient of the straight gate channel width offset, W WLis the length-width cross-term coefficient of the straight gate channel width offset, W LN is the channel length-dependent power of the straight gate channel width offset, W WN is the channel width-dependent power of the straight gate channel width offset.

[0064] In this step, the equivalent drain n injection active area perimeter PD, the equivalent source n injection active area perimeter PS, the equivalent drain n injection active area AD, the equivalent source n injection active area AS, and the equivalent number of parallel tubes m are calculated by the formula

[0065] PD=W eff

[0066] and formula

[0067] PS=2·W eff +4·L eff +2·L S

[0068] and formula

[0069]

[0070] and formula

[0071]

[0072] and formula

[0073]

[0074] Determine, where L S It is the length of the source active region in the channel direction of each sub-device component.

[0075] Step S5: Combine other model process parameters to establish a complete BSIM3V3.2 model.

[0076] In this step, the extraction of other model parameters is based on the empirical data of the prior art, and is extracted using the extraction algorithm dedicated to BSIM3V3.2. The radiation-resistant square-ring gate MOSFET simulation model only considers the simulation model of the metal oxide semiconductor field effect transistor with an N-type square-ring gate structure, and the device description script is a .scs / .lib suffix file applied to SPECTRE / SPICE.

[0077] This specific implementation also provides an example, taking the 0.35μm radiation-resistant square-ring gate MOSFET semiconductor device as the existing technology, the semiconductor device modeling method provided in this specific implementation is used to build a model for the 0.35μm radiation-resistant square-ring gate MOSFET semiconductor device and perform simulation.

[0078] Figure 4A flowchart of the steps of a specific embodiment of the radiation-resistant square-gate-ring MOSFET semiconductor device modeling method provided by the present invention.

[0079] like Figure 4 As shown, the radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method provided in this specific embodiment includes the following steps:

[0080] Step a: Extract the important process parameters of the direct-gate MOSFET semiconductor device from the foundry PDK library file to obtain the gate length L, drain active area gate width W, drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, P substrate doping concentration, P well doping concentration, n injection doping concentration and source / drain junction depth X. j etc. parameter values.

[0081] Step b: Extract the parameters of the direct-gate MOSFET device according to step a, use the script code to model the three-dimensional device through the TCAD device editor and perform numerical simulation calculations. In the TCAD numerical calculation, it is necessary to apply the LOMBARDICVT physical model and the Shockley-Read-Hall composite carrier model to calculate the current characteristics in the device.

[0082] Step c: Based on the straight gate design corresponding to the standard CMOS process in the foundry PDK library involved in step a and extracting relevant process parameters, an equivalent physical model of the trapezoidal gate MOSFET semiconductor device can be established.

[0083]

[0084] Determine, where: W trapezoid is the equivalent active area width of the trapezoidal gate, α is the bottom angle of the trapezoidal gate, when the square ring gate structure is considered, α is 45°, L is the gate length of the straight gate device, and W is the active area width of the drain of the straight gate device.

[0085] Step d: Based on the current characteristics of the device obtained by numerical calculation in step b, the current characteristics obtained by direct-gate MOSFET circuit simulation are compared and fitted, and the corresponding process parameters in the TCAD three-dimensional model application can be reversed, including P substrate doping concentration, P well doping concentration, n injection doping concentration and source / drain junction depth X j etc. parameter values.

[0086] Step e: Based on the geometric structure and equivalent sub-circuit topology of the device, the square device is divided equally into four sub-device components along the diagonal with the same electrical performance and indicators. The ring-gate device can be equivalent to four trapezoidal-gate semiconductor devices, and a sub-circuit structure of a radiation-resistant square ring-gate MOSFET semiconductor device can be constructed in parallel.

[0087] Step f: Using the layout design rules of the PDK provided by the foundry, the radiation-resistant square-ring gate MOSFET semiconductor device can be laid out for layout implementation according to the circuit performance design index requirements.

[0088] In this step, the process parameters related to the device size are calculated according to the layout planning requirements and design rule restrictions, including: device gate length L, device drain gate width W D , the gate width W of the device source S1 and the active area width W at the source end of the device S2 .

[0089] In this step, the gate width W of the device drain is D By formula

[0090]

[0091] Determine, where: W CT is the width of the square polycrystalline layer contact hole, N CT is the number of contact holes in the polycrystalline layer, l CT is the distance between contact holes in the polycrystalline layer, is the distance between the polycrystalline layer contact hole and the 1st metal layer. In this step, the gate width W of the device drain end S1 By formula

[0092] W S1 =W D +2·L

[0093] Sure.

[0094] In this step, the active area width W of the device source end S2 By formula

[0095] W S2 =W S1 +2·l G +2·l I

[0096] Determine, where l G is the distance from the center of the polycrystalline layer contact hole in the source active area to the gate edge, l I It is the distance from the center of the polycrystalline layer contact hole in the active area of ​​the source end to the isolation edge.

[0097] In this step, the layout design involved in this embodiment is intended to be based on the minimum device size requirement (N CT =1) Calculate the gate length L of the device and the gate width W of the device drain D , the gate width W of the device source S1 and the active area width W at the source end of the device S2 .

[0098] Step g: According to step f, important process parameters related to device size can be extracted, including: gate length L eff , Gate width W eff , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, etc.

[0099] In this step, the equivalent trapezoidal gate width W eff By formula

[0100]

[0101] Determine, where: L eff is the effective channel length of the straight-gate device, W eff is the effective active area width of the drain of a straight-gate device.

[0102] In this step, the effective channel length L of the straight gate device eff By formula

[0103]

[0104] Determine, where: To improve the calculation accuracy of the model, L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and L INT is the straight gate channel length offset fitting parameter extracted from the foundry process PDK library, L L is the channel length correlation coefficient of the straight gate channel length offset, L W is the channel width correlation coefficient of the straight gate channel length offset, L WL is the length-width cross-term coefficient of the straight gate channel length offset, L LN is the channel length-dependent power of the straight gate channel length offset, L WN is the channel width-dependent power of the straight gate channel length offset.

[0105] In this step, the effective channel width W of the straight gate device eff By formula

[0106]

[0107] Determine, where: L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and W INT is the straight gate channel width offset fitting parameter extracted from the foundry process PDK library, W L is the channel length correlation coefficient of the straight gate channel width offset, W W is the channel width correlation coefficient of the straight gate channel width offset, W WL is the length-width cross-term coefficient of the straight gate channel width offset, W LNis the channel length-dependent power of the straight gate channel width offset, W WN is the channel width-dependent power of the straight gate channel width offset.

[0108] In this step, the equivalent drain n injection active area perimeter PD, the equivalent source n injection active area perimeter PS, the equivalent drain n injection active area AD, the equivalent source n injection active area AS, and the equivalent number of parallel tubes m are calculated by the formula

[0109] PD=W eff

[0110] and formula

[0111] PS=2·W eff +4·L eff +2·L S

[0112] and formula

[0113]

[0114] and formula

[0115]

[0116] and formula

[0117]

[0118] Determine, where L S It is the length of the source active region in the channel direction of each sub-device component.

[0119] Step h: Based on the equivalent subcircuit obtained in step e and the important process parameters related to the size obtained in step g, the SPECTRE netlist of the radiation-resistant square-ring gate MOSFET semiconductor device constructed by the ladder-gate MOSFET semiconductor device can be extracted.

[0120] Step i: Based on the corresponding process parameters in the TCAD three-dimensional model application obtained in step d, and according to the important process parameters related to the device size extracted in steps f and g, a three-dimensional simulation calculation model of the radiation-resistant square ring gate MOSFET semiconductor device is proposed, and the current characteristics in the device are obtained by numerical calculation.

[0121] Step j: According to step g, extract the important equivalent parameters of the radiation-resistant square-ring gate MOSFET semiconductor device, establish a complete BSIM3V3.2 model, and realize the simulation of the radiation-resistant semiconductor device.

[0122] Step k: comparing the current characteristics in the device obtained in step i with the current characteristics obtained by circuit simulation of the square-ring gate MOSFET semiconductor device.

[0123] Step 1: Based on the complete BSIM3V3.2 model of the radiation-resistant square-ring gate MOSFET semiconductor device established in step j and the SPECTRE netlist of the radiation-resistant square-ring gate MOSFET semiconductor device obtained in step h, SPECTRE simulation can be performed.

[0124] In steps d to i, some parameters are fine-tuned to achieve the target device electrical indicators determined according to the design standards and specifications.

[0125] Figure 5 This is the EDA layout structure of the radiation-resistant square-ring-gate MOSFET semiconductor device, which corresponds to steps f to g of the specific embodiment of the modeling method of the radiation-resistant square-ring-gate MOSFET semiconductor device described above. Using the layout design rules, the radiation-resistant square-ring-gate NMOSFET semiconductor device can be designed according to the chip area of ​​the minimum device. Then, important process parameters related to the device size can be extracted, including: the straight gate effective channel length L eff , straight gate effective channel width W eff , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, etc.

[0126] Figure 6 It is the TCAD model structure of the radiation-resistant square-ring-gate MOSFET semiconductor device, corresponding to the three-dimensional simulation calculation model of the radiation-resistant square-ring-gate MOSFET semiconductor device and the cross-sectional schematic diagram at the position z=1.9μm proposed in step i of the specific embodiment step flow chart of the above-mentioned radiation-resistant square-ring-gate MOSFET semiconductor device modeling method.

[0127] Figure 7 According to the modeling method and parameter setting provided in this embodiment, the BSIM3V3 model and the 0.35μm radiation-resistant square-ring gate MOSFET semiconductor device are combined according to the SPECTRE simulation simulation of the 0.35μm radiation-resistant square-ring gate NMOSFET semiconductor device I / V characteristics and the NMOSFET radiation-resistant square-ring gate MOSFET semiconductor device I / V characteristics calculated by TCAD three-dimensional numerical simulation. D -V G The comparison curve of the characteristics shows that in the above simulation results, the maximum error is less than 5%.

[0128] It can be seen from the above simulation results that the radiation-resistant square-ring-gate NMOSFET semiconductor device modeling method provided in this specific implementation manner and the example is based on the existing BSIM3V3.2, and adopts a standard set of models. By extracting the key process parameters of the straight-gate MOSFET semiconductor device from the foundry PDK library, and establishing a physical model of the trapezoidal-gate MOSFET semiconductor device according to the process parameters, the geometric structure and equivalent sub-circuit topology of the radiation-resistant square-ring-gate MOSFET semiconductor device are clarified, and based on the physical model and circuit topology, some important structural topological characteristic parameters of the model are extracted by reverse deduction. Combined with other model process parameters, a complete set of BSIM3V3.2 models is established to realize the simulation of radiation-resistant semiconductor devices.

[0129] In the radiation-resistant square-ring-gate NMOSFET semiconductor device modeling method, there are about 194 BSIM3V3.2 model parameters involved, and only 6 of them are modified. The modified model parameters are: trapezoidal gate equivalent width W eq W eff , equivalent perimeter of drain active area PD, equivalent perimeter of source active area PS, equivalent area of ​​drain active area AD, equivalent area of ​​source active area AS, equivalent number of parallel tubes m. Other parameters remain unchanged, which can be widely and effectively applied in the industry. It can obtain high-precision parameters of conventional device physical phenomena such as body effect, short channel effect, long channel effect, DIBL, etc. based on physical models, accurately simulate the performance of radiation-resistant semiconductor devices, and simulate I for NMOSFET. D -V G The current characteristic error is basically maintained below 5%, which can accurately reflect the performance of the radiation-resistant square-ring gate NMOSFET semiconductor device, overcome the delay between the simulation of the radiation-resistant square-ring gate NMOSFET semiconductor device and the semiconductor process, and can provide a reliable research basis and effective auxiliary guidance for the early circuit design and technology development based on the radiation-resistant square-ring gate NMOSFET semiconductor device.

[0130] The radiation-resistant square-ring-gate NMOSFET semiconductor device modeling method provided by the present invention adopts a standard set of models on the basis of the existing BSIM3V3.2, extracts the key process parameters of the straight-gate MOSFET semiconductor device from the foundry PDK library, establishes the physical model of the trapezoidal-gate MOSFET semiconductor device according to the process parameters, clarifies the geometric structure and equivalent subcircuit topology of the radiation-resistant square-ring-gate MOSFET semiconductor device, extracts some important structural topological characteristic parameters of the model according to the physical model and circuit topology, and establishes a complete set of BSIM3V3.2 models in combination with other model process parameters to achieve simulation of radiation-resistant semiconductor devices. In the semiconductor device modeling method provided by the present invention, there are about 194 BSIM3V3.2 model parameters involved, only 6 of which are modified, and the other parameters remain unchanged, which can be widely and effectively applied in the industry.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method, characterized in that: The following steps are involved: 1) Obtain key process parameters of direct-gate MOSFET semiconductor devices; 2) Establishing an equivalent physical model of a trapezoidal gate semiconductor device based on key process parameters; 3) Based on the trapezoidal gate semiconductor device, construct the geometric structure and equivalent sub-circuit topology of the radiation-resistant square-ring gate MOSFET semiconductor device; 4) Based on the equivalent physical model and equivalent subcircuit topology, extract the important structural topological characteristic parameters of the radiation-resistant square-ring gate MOSFET semiconductor device model; 5) Extract other model process parameters of the square-ring gate MOSFET semiconductor device, and use important structural topological characteristic parameters for simulation to obtain a radiation-resistant square-ring gate MOSFET semiconductor device model.

2. The radiation-resistant square-ring gate MOSFET semiconductor device modeling method according to claim 1, characterized in that: The key process parameters include: the gate length L of the straight-gate device and the active area width W of the drain of the straight-gate device.

3. The radiation-resistant square-ring gate MOSFET semiconductor device modeling method according to claim 1, characterized in that: In the step 2), the equivalent physical model is determined by the following formula: Among them, W trapezoid is the equivalent active area width of the trapezoidal gate, α is the bottom angle of the trapezoidal gate, L is the gate length of the straight gate device, and W is the active area width of the drain of the straight gate device.

4. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: The step 3) is specifically as follows: The ring-gate semiconductor device is equivalent to four sub-devices with the same electrical performance and indicators which are equally divided along the diagonal line. Each trapezoidal gate semiconductor device is used as a sub-device, and they are connected in parallel to construct an equivalent sub-circuit topology of a radiation-resistant square ring-gate MOSFET semiconductor device.

5. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: In step 4), the important structural topological characteristic parameters include: the trapezoidal gate width W eq , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, number of parallel tubes m, where: PD=W eff PS=2·W eff +4·L eff +2·L S Among them, L eff is the effective channel length of the straight-gate device, W eff is the effective active area width of the drain of the straight-gate device, L S It is the length of the source active region in the channel direction of each sub-device component.

6. The radiation-resistant square-ring gate MOSFET semiconductor device modeling method according to claim 5, characterized in that: The L eff and W eff Specifically: Where, L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and L INT is the straight gate channel length offset fitting parameter, L L is the channel length correlation coefficient of the straight gate channel length offset, L W is the channel width correlation coefficient of the straight gate channel length offset, L WL is the length-width cross-term coefficient of the straight gate channel length offset, L LN is the channel length-dependent power of the straight gate channel length offset, L WN is the power of the channel width related to the offset of the straight gate channel length, W INT is the straight gate channel width offset fitting parameter, W L is the channel length correlation coefficient of the straight gate channel width offset, W W is the channel width correlation coefficient of the straight gate channel width offset, W WL is the length-width cross-term coefficient of the straight gate channel width offset, W LN is the channel length-dependent power of the straight gate channel width offset, W WN is the channel width-dependent power of the straight gate channel width offset.

7. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: In the step 5), other model process parameters are extracted using a BSIM3V3.2-specific extraction algorithm.

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