Method for modeling anti-radiation square ring-gate mosfet semiconductor device

Abstract

The application discloses a modeling method of an anti-radiation square ring gate MOSFET semiconductor device, and belongs to the field of microelectronic device modeling. D ‑V G The modeling method is used for simulating and comparing the I D ‑V G characteristic error of N-type MOSFET is less than 5%, and the anti-radiation semiconductor device performance can be accurately reflected, the time delay between the semiconductor device simulation and the semiconductor process is overcome, and a reliable research foundation is provided for early circuit design and technical development based on the anti-radiation semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semi-microelectronic device modeling, in particular to a kind of anti-radiation square ring gate MOSFET semiconductor device modeling method, and specifically relates to the SPICE modeling method for anti-radiation semiconductor device. BACKGROUND

[0002] Integrated circuits play a very important role in the field of aerospace and nuclear physics, and they often suffer from various radiation, which can have a negative impact on the performance and reliability of integrated circuits. In these environments, we need to use radiation-hardened design techniques to ensure the high precision and high reliability of integrated circuits. Integrated circuits in the field of aerospace and nuclear physics face various radiation challenges, which can change the electrical properties of semiconductor materials in integrated circuits, causing logic operation errors or permanent damage. For example, the threshold voltage of MOSFET may change due to radiation-induced charge accumulation, affecting the current characteristics within the device. In addition to the direct effects of radiation, integrated circuits also need to resist the effects of electromagnetic fields caused by radiation. These electromagnetic fields can generate noise in the circuit, causing output signal errors. To reduce the effects of radiation, researchers have developed various radiation-hardened integrated circuit design techniques, including the use of radiation-stable materials, and the design of circuits with redundancy, or the use of error correction codes and radiation-tolerant memory to reduce radiation-induced errors. These technologies can ensure that integrated circuits can still work normally under high levels of radiation. The development of radiation-hardened integrated circuits is a very fast field, with new research and development constantly being carried out to improve their radiation resistance and overall performance. As the demand for integrated circuits in aerospace and nuclear physics applications continues to increase, the demand for radiation-hardened designs also continues to increase. In summary, integrated circuits play a very important role in the field of aerospace and nuclear physics, and their anti-radiation performance is a major problem. By developing radiation-hardened integrated circuit designs, researchers can ensure that integrated circuits can still work normally in the most severe environments. Continued research and development will help drive technological development to ensure that integrated circuits continue to play a key role in aerospace and nuclear physics applications. To ensure the reliability of integrated circuits in the field of aerospace, radiation-hardened design must be carried out. Researching radiation-hardened technology is essential to meet the needs of space environment applications. This can effectively alleviate the impact of radiation on the function of integrated circuits. Therefore, the importance of anti-radiation square ring gate MOSFET semiconductor device in the above-mentioned integrated circuits is self-evident.

[0003] In the existing modeling method, generally includes physical effect parameters, process parameters, general parameters, simulation parameters obtained by testing and other fitting parameters for calculation. However, the existing modeling method and parameter extraction method are mostly improved and perfected for the prepared anti-radiation square ring gate MOSFET semiconductor device, and the model establishment and extraction method for the anti-radiation square ring gate MOSFET semiconductor device which has not yet been mass-produced is less, and the modeling and process feature extraction method combined with TCAD numerical simulation verification and layout design rule is more scarce, so the existing modeling method mostly has a certain process delay, it is difficult to predict the performance of the anti-radiation square ring gate MOSFET semiconductor device, and it is also unable to assist the early research and development of the anti-radiation integrated circuit design. SUMMARY

[0004] The purpose of the present application is to provide a modeling method for anti-radiation square ring gate MOSFET semiconductor device, based on BSIM3V3.2 device model, for simulation and simulation of anti-radiation square ring gate semiconductor device, which can predict the performance of anti-radiation square ring gate MOSFET semiconductor device before process implementation, and provide research basis and auxiliary guidance for early circuit design and technology development based on anti-radiation square ring gate MOSFET semiconductor device.

[0005] The technical scheme adopted by the present application to achieve the above-mentioned purpose is:

[0006] The anti-radiation square ring gate MOSFET semiconductor device modeling method comprises the following steps:

[0007] 1) Obtain the key process parameters of the straight gate MOSFET semiconductor device;

[0008] 2) Establish an equivalent physical model of the trapezoidal gate semiconductor device according to the key process parameters;

[0009] 3) Based on the trapezoidal gate semiconductor device, construct the geometric structure and equivalent subcircuit topology of the anti-radiation square ring gate MOSFET semiconductor device;

[0010] 4) According to the equivalent physical model and the equivalent subcircuit topology, extract the important structure topology characteristic parameters of the anti-radiation square ring gate MOSFET semiconductor device model;

[0011] 5) Extract other model process parameters of the square ring gate MOSFET semiconductor device, and use the important structure topology characteristic parameters for simulation to obtain the anti-radiation square ring gate MOSFET semiconductor device model.

[0012] The key process parameters include: the gate length L of the straight gate device, and the active area width W of the drain of the straight gate device.

[0013] In the step 2), the equivalent physical model is determined by the following formula:

[0014]

[0015] Wherein, W trapezoid is the equivalent active area width of the trapezoidal gate, a is the bottom angle of the trapezoidal gate, L is the gate length of the straight gate device, and W is the active area width of the drain of the straight gate device.

[0016] The step 3) is specifically:

[0017] The annular gate semiconductor device is equivalent to four sub-devices which are divided along the diagonal and have the same electrical performance and index, each trapezoidal gate semiconductor device is a sub-device, and the equivalent sub-circuit topology of the anti-radiation square ring gate MOSFET semiconductor device is constructed in parallel.

[0018] In the step 4), the important structure topology characteristic parameters include: trapezoidal gate width W eq , drain active area perimeter PD, source active area perimeter PS, drain active area AD, source active area AS, and parallel pipe number m, wherein:

[0019]

[0020] PD=W eff

[0021] PS=2·W eff +4·L eff +2·L S

[0022]

[0023]

[0024]

[0025] Wherein, L eff is the effective channel length of the straight gate device, W eff is the effective active area width of the drain of the straight gate device, and L S is the source active area channel direction length of each sub-device component.

[0026] The L eff and W eff are specifically:

[0027]

[0028]

[0029] Wherein, L is the gate length of the straight grid device, W is the active region width of the drain of the straight grid device, L INT is the fitting parameter of the straight grid channel length offset, L L is the channel length correlation coefficient of the straight grid channel length offset, L W is the channel width correlation coefficient of the straight grid channel length offset, L WL is the length-width cross term coefficient of the straight grid channel length offset, L LN is the channel length correlation power number of the straight grid channel length offset, L WN is the channel width correlation power number of the straight grid channel length offset, W INT is the fitting parameter of the straight grid channel width offset, W L is the channel length correlation coefficient of the straight grid channel width offset, W W is the channel width correlation coefficient of the straight grid channel width offset, W WL is the length-width cross term coefficient of the straight grid channel width offset, W LN is the channel length correlation power number of the straight grid channel width offset, W WN is the channel width correlation power number of the straight grid channel width offset.

[0030] In the step 5), other model process parameters are extracted by using the extraction algorithm special for BSIM3V3.2.

[0031] The present application has the following beneficial effects and advantages:

[0032] The present application can accurately simulate the performance of the anti-radiation semiconductor device based on the physical model, the I D -V G characteristic error can be less than 5%, the performance of the anti-radiation semiconductor device can be accurately reflected, the time delay between the semiconductor device simulation and the semiconductor process is overcome, reliable research foundation and effective auxiliary guidance can be provided for early circuit design and technical development based on the anti-radiation semiconductor device, and the simulation verification of improving the circuit design is realized, support is provided for chip design, the needs of efficient circuit design and development are met, and the direction of anti-radiation semiconductor process development is provided. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 It is a schematic diagram of one embodiment of the modeling method of the anti-radiation square ring gate MOSFET semiconductor device of the present application.

[0034] Figure 2 It is a schematic diagram of the planar structure of the anti-radiation square ring gate MOSFET semiconductor device in the prior art.

[0035] Figure 3Equivalent subcircuit topological structure diagram of the anti-radiation square ring gate MOSFET semiconductor device of the present application.

[0036] Figure 4 Step flow chart of the embodiment of the modeling method of the anti-radiation square ring gate MOSFET semiconductor device of the present application.

[0037] Figure 5 EDA layout structure diagram of the anti-radiation square ring gate MOSFET semiconductor device of the present application.

[0038] Figure 6 TCAD model structure diagram of the anti-radiation square ring gate MOSFET semiconductor device of the present application.

[0039] Figure 7 I / V characteristic curve diagram obtained by simulating the semiconductor device modeling method of the embodiment of the present application on the 0.35 mu m anti-radiation square ring gate NMOSFET semiconductor device.

[0040] Wherein: 2, the anti-radiation square ring gate MOSFET semiconductor device, 21, the drain region of the n-type injection active region of the anti-radiation square ring gate MOSFET semiconductor device, 22, the gate oxide layer region of the anti-radiation square ring gate MOSFET semiconductor device, 23, the source region of the n-type injection active region of the anti-radiation square ring gate MOSFET semiconductor device, 24, the peripheral field oxide region of the anti-radiation square ring gate MOSFET semiconductor device, 5, the EDA layout of the anti-radiation square ring gate MOSFET semiconductor device, 51, the drain region of the n-type injection active region of the anti-radiation square ring gate MOSFET semiconductor device layout, 52, the gate oxide layer region of the anti-radiation square ring gate MOSFET semiconductor device layout, 53, the source region of the n-type injection active region of the anti-radiation square ring gate MOSFET semiconductor device layout, 54, the NBL layer region of the anti-radiation square ring gate MOSFET semiconductor device layout, 55, the source region of the p-type injection active region of the anti-radiation square ring gate MOSFET semiconductor device layout, 6, the TCAD model of the anti-radiation square ring gate MOSFET semiconductor device, 61, the drain end region of the anti-radiation square ring gate MOSFET semiconductor device, 62, the channel region of the anti-radiation square ring gate MOSFET semiconductor device, 63, the source end region of the anti-radiation square ring gate MOSFET semiconductor device, 64, the substrate region of the anti-radiation square ring gate MOSFET semiconductor device. DETAILED DESCRIPTION

[0041] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0042] The anti-radiation square ring gate MOSFET semiconductor device modeling method provided in the specific embodiment is based on a BSIM3V3.2 device model and is used for simulation and simulation of anti-radiation semiconductor devices.

[0043] Figure 1 The anti-radiation square ring gate MOSFET semiconductor device modeling method provided in the specific embodiment is based on a BSIM3V3.2 device model and is used for simulation and simulation of anti-radiation semiconductor devices.

[0044] As shown in Figures 1 to 3 The anti-radiation square ring gate MOSFET semiconductor device modeling method provided in the specific embodiment includes the following steps:

[0045] Step S1: Extracting key process parameters of straight gate MOSFET semiconductor devices through foundry PDK library.

[0046] In this step, the key process parameters extracted by the foundry PDK library are physical parameters, which are all parameters preset according to the feature size of the straight gate MOSFET semiconductor device, including transistor gate length L, drain active area width W, physical gate oxide layer thickness T ox , source / drain junction depth X j , etc.

[0047] Step S2: Establishing a physical model of the trapezoidal gate semiconductor device according to the process parameters.

[0048] In this step, according to the straight gate design corresponding to the standard CMOS process of the foundry PDK library and the extraction of the related process parameters, an equivalent physical model of the trapezoidal gate MOSFET semiconductor device can be established, which is determined by the formula

[0049]

[0050] , wherein: W trapezoid is the equivalent active area width of the trapezoidal gate, and a is the bottom angle of the trapezoidal gate. When considering the square ring gate structure, a is 45°, and the gate length L of the straight gate device and the active area width W of the drain of the straight gate device.

[0051] Step S3: Defining the geometric structure and equivalent subcircuit topology of the anti-radiation square ring gate MOSFET semiconductor device.

[0052] In this step, based on the fact that the square device is divided into four sub-device components with the same electrical performance and indicators along the diagonal according to the geometric structure and equivalent subcircuit topology of the device, the ring gate device can be equivalent to four trapezoidal gate semiconductor devices, and the subcircuit structure of the anti-radiation square ring gate MOSFET semiconductor device is constructed in a parallel manner.

[0053] Step S4: According to the physical model and the circuit topology, the important structural topology characteristic parameters of the model are extracted by backstepping.

[0054] In this step, the important equivalent parameters are determined according to the physical model, including the trapezoidal gate width W eq , the drain active area perimeter PD, the source active area perimeter PS, the drain active area AD, the source active area AS, and the number of parallel tubes m.

[0055] In this step, the equivalent trapezoidal gate width W eq is determined by the formula

[0056]

[0057] , wherein: L eff is the effective channel length of the straight gate device, W eff is the effective active area width of the drain of the straight gate device.

[0058] In this step, the effective channel length L eff of the straight gate device is determined by the formula

[0059]

[0060] , wherein: L INT is the gate length of the straight gate device, W L is the active area width of the drain of the straight gate device, L W is the channel length related coefficient of the straight gate channel length offset, L WL is the channel width related coefficient of the straight gate channel length offset, L LN is the length-width cross term coefficient of the straight gate channel length offset, L WN is the channel length related power number of the straight gate channel length offset, and L eff is the channel width related power number of the straight gate channel length offset.

[0061] In this step, the effective channel width W INT of the straight gate device is determined by the formula

[0062]

[0063] , wherein: L L is the gate length of the straight gate device, W W is the active area width of the drain of the straight gate device, W WLW is a coefficient of the cross term of the length and the width of the straight grid channel width offset LN W is a coefficient of the cross term of the length and the width of the straight grid channel width offset WN W is a coefficient of the cross term of the length and the width of the straight grid channel width offset

[0064] In this step, the equivalent drain n injection active area perimeter PD, the equivalent source n injection active area perimeter PS, the equivalent drain n injection active area AD, the equivalent source n injection active area AS, and the equivalent parallel tube number m are determined by the formula

[0065] PD = W eff

[0066] and the formula

[0067] PS = 2 · W eff + 4 · L eff + 2 · L S

[0068] and the formula

[0069]

[0070] and the formula

[0071]

[0072] and the formula

[0073]

[0074] is determined, wherein L S is the source active area channel direction length of each sub-device component.

[0075] Step S5: Combine other model process parameters to establish a complete BSIM3V3.2 model.

[0076] In this step, the extraction of other model parameters is based on the existing technical experience data, and the BSIM3V3.2 dedicated extraction algorithm is used for extraction. The anti-radiation square ring gate MOSFET simulation model only considers the metal oxide semiconductor field effect transistor simulation model of the N-type square ring gate structure, and the device description script is the.scs / .lib suffix name file applied to SPECTRE / SPICE.

[0077] The specific embodiment also provides an embodiment taking a 0.35 μm anti-radiation square ring gate MOSFET semiconductor device as the prior art, and using the semiconductor device modeling method provided by the specific embodiment to establish a model for the 0.35 μm anti-radiation square ring gate MOSFET semiconductor device and perform simulation.

[0078] Figure 4The embodiment of the anti-radiation square ring gate MOSFET semiconductor device modeling method provided by the application comprises the following steps:

[0079] As Figure 4 shown, the anti-radiation square ring gate MOSFET semiconductor device modeling method provided by the embodiment comprises the following steps:

[0080] Step a: important process parameters of a straight gate MOSFET semiconductor device are extracted from a foundry PDK library file to obtain parameter values such as gate length L, drain active area gate width W, drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, P substrate doping concentration, P well doping concentration, n injection doping concentration, and source / drain junction depth X. j

[0081] Step b: according to the parameters of the straight gate MOSFET device extracted in step a, a three-dimensional device is modeled and numerical simulation calculation is performed by using a script code in a TCAD device editor. In the TCAD numerical calculation, a Lombardic VT physical model and a Shockley-Read-Hall recombination carrier model need to be applied to calculate the current characteristics in the device.

[0082] Step c: according to the straight gate design corresponding to a standard CMOS process and the related process parameters of the foundry PDK library involved in step a, an equivalent physical model of a trapezoidal gate MOSFET semiconductor device can be established, and is determined by the formula

[0083]

[0084] , wherein: W trapezoid is the equivalent active area width of the trapezoidal gate, α is the bottom angle of the trapezoidal gate, α is 45° when the square ring gate structure is considered, L is the gate length of the straight gate device, and W is the active area width of the drain of the straight gate device.

[0085] Step d: according to the current characteristics in the device obtained by the numerical calculation in step b, the current characteristics obtained by the simulation of the straight gate MOSFET circuit are compared and fitted, and the corresponding process parameters in the application of the TCAD three-dimensional model are inversely extracted, including the P substrate doping concentration, the P well doping concentration, the n injection doping concentration, and the source / drain junction depth X. j

[0086] Step e: based on the fact that the square device is equally divided into four sub-devices with the same electrical performance and indicators along the diagonal, the ring gate device can be equivalent to four trapezoidal gate semiconductor devices, and the sub-circuit structure of the anti-radiation square ring gate MOSFET semiconductor device is constructed in a parallel manner.​​

[0087] Step f: According to the layout design rules of the PDK provided by the foundry, the layout of the anti-radiation square ring gate MOSFET semiconductor device is realized according to the circuit performance design index requirement.

[0088] In this step, the process parameters related to the device size are calculated according to the layout planning requirements and design rule restrictions, including: device gate length L, device drain end gate width W D , device source end gate width W S1 , and device source end active area width W S2 .

[0089] In this step, the device drain end gate width W D is determined by the formula

[0090]

[0091] , where: W CT is the width of the square polycrystalline layer contact hole, N CT is the number of polycrystalline layer contact holes, l CT is the distance between the polycrystalline layer contact hole and the contact hole, is the distance between the polycrystalline layer contact hole and the 1st layer of metal. In this step, the device drain end gate width W S1 is determined by the formula

[0092] W S1 = W D + 2·L

[0093] .

[0094] In this step, the device source end active area width W S2 is determined by the formula

[0095] W S2 = W S1 + 2·l G + 2·l I

[0096] , where l G is the distance from the center of the polycrystalline layer contact hole in the source end active area to the edge of the gate, and l I is the distance from the center of the polycrystalline layer contact hole in the source end active area to the isolation edge.

[0097] In this step, according to the layout design of the present embodiment, the device gate length L, the device drain end gate width W D , the device source end gate width W S1 , and the device source end active area width W S2 are calculated according to the minimum device size requirement (N CT = 1).

[0098] Step g: According to step f, the device size related important process parameters can be further extracted, including: gate length L eff , gate width W eff , drain active area perimeter PD, source active area perimeter PS, drain active area AD, source active area AS, etc.

[0099] In this step, the equivalent trapezoidal gate width W eff is determined by the formula

[0100]

[0101] , wherein: L eff is the effective channel length of the straight gate device, W eff is the effective active area width of the drain of the straight gate device.

[0102] In this step, the effective channel length L eff of the straight gate device is determined by the formula

[0103]

[0104] , wherein: L is the gate length of the straight gate device, W is the active area width of the drain of the straight gate device, L INT is the straight gate channel length offset fitting parameter extracted from the foundry process PDK library, L L is the channel length related coefficient of the straight gate channel length offset, L W is the channel width related coefficient of the straight gate channel length offset, L WL is the length-width cross term coefficient of the straight gate channel length offset, L LN is the channel length related power number of the straight gate channel length offset, L WN is the channel width related power number of the straight gate channel length offset.

[0105] In this step, the effective channel width W eff of the straight gate device is determined by the formula

[0106]

[0107] , wherein: L is the gate length of the straight gate device, W is the active area width of the drain of the straight gate device, W INT is the straight gate channel width offset fitting parameter extracted from the foundry process PDK library, W L is the channel length related coefficient of the straight gate channel width offset, W W is the channel width related coefficient of the straight gate channel width offset, W WL is the length-width cross term coefficient of the straight gate channel width offset, W LNis the channel length-related power of the straight gate channel width offset, W WN is the channel width-related power of the straight gate channel width offset.

[0108] In this step, the equivalent drain n injection active area perimeter PD, the equivalent source n injection active area perimeter PS, the equivalent drain n injection active area area AD, the equivalent source n injection active area area AS, and the equivalent number of parallel tubes m are calculated by the formula

[0109] PD=W eff

[0110] and formula

[0111] PS = 2·W eff +4·L eff +2·L S

[0112] and formula

[0113]

[0114] and formula

[0115]

[0116] and formula

[0117]

[0118] Determine, where L S is the length of the source active region in the channel direction of each sub-device component.

[0119] Step h: Based on the equivalent subcircuit obtained in step e and the important process parameters related to the size obtained in step g, the SPECTRE netlist of the radiation-resistant square-ring gate MOSFET semiconductor device constructed by the trapezoidal gate MOSFET semiconductor device can be extracted.

[0120] Step i: Based on the process parameters corresponding to the TCAD three-dimensional model application obtained in step d, and according to the important process parameters related to the device size extracted in steps f and g, a three-dimensional simulation calculation model of the radiation-resistant square ring gate MOSFET semiconductor device is proposed, and the current characteristics in the device are obtained by numerical calculation.

[0121] Step j: According to step g, extract the radiation-resistant square-ring gate MOSFET semiconductor device to determine the important equivalent parameters, establish a complete BSIM3V3.2 model, and realize the simulation of the radiation-resistant semiconductor device.

[0122] Step k: comparing the device current characteristics obtained in step i with the current characteristics obtained by circuit simulation of a square-ring gate MOSFET semiconductor device.

[0123] Step 1: Based on the complete BSIM3V3.2 model of the radiation-hardened square-gate-all-around MOSFET semiconductor device established in step j and the SPECTRE netlist of the radiation-hardened square-gate-all-around MOSFET semiconductor device obtained in step h, a SPECTRE simulation can be performed.

[0124] In steps d to i, some parameters are fine-tuned to achieve target device electrical specifications based on design standards and specifications.

[0125] Figure 5 This is the EDA layout structure for a radiation-hardened square-gate-all-around MOSFET semiconductor device, corresponding to steps f-g in the flowchart of the specific embodiment of the radiation-hardened square-gate-all-around MOSFET semiconductor device modeling method described above. Using layout design rules, a radiation-hardened square-gate-all-around NMOSFET semiconductor device can be designed based on the minimum device chip area. Furthermore, important process parameters related to device size can be extracted, including: the straight gate effective channel length L eff , straight gate effective channel width W eff , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, etc.

[0126] Figure 6 It is the TCAD model structure of the radiation-resistant square-ring-gate MOSFET semiconductor device, corresponding to the three-dimensional simulation calculation model of the radiation-resistant square-ring-gate MOSFET semiconductor device and the cross-sectional schematic diagram at the position z=1.9μm proposed in step i of the specific embodiment step flow chart of the above-mentioned radiation-resistant square-ring-gate MOSFET semiconductor device modeling method.

[0127] Figure 7 According to the modeling method and parameter setting provided in this embodiment, the BSIM3V3 model and the 0.35μm radiation-resistant square-gate-all-around MOSFET semiconductor device are combined with the I / V characteristics of the 0.35μm radiation-resistant square-gate-all-around NMOSFET semiconductor device obtained by SPECTRE simulation and the NMOSFET radiation-resistant square-gate-all-around MOSFET semiconductor device I / V characteristics calculated by TCAD three-dimensional numerical simulation. D -V G The comparison curve of the characteristics shows that in the above simulation results, the maximum error is less than 5%.

[0128] From the simulation results, the anti-radiation square ring gate NMOSFET semiconductor device modeling method provided by the embodiment can extract the key process parameters of the straight gate MOSFET semiconductor device from the foundry PDK library, establish a physical model of the ladder gate MOSFET semiconductor device according to the process parameters, and determine the geometric structure and equivalent subcircuit topology of the anti-radiation square ring gate MOSFET semiconductor device. According to the physical model and the circuit topology, the important structural topology characteristic parameters of the model are extracted reversely, and the complete BSIM3V3.2 model is established by combining other model process parameters, so that the simulation and analysis of the anti-radiation semiconductor device are realized.

[0129] In the anti-radiation square ring gate NMOSFET semiconductor device modeling method, there are about 194 BSIM3V3.2 model parameters, and only 6 parameters are modified. The model parameters involved in the modification are: the ladder gate equivalent width W eq W eff , the equivalent perimeter of the drain active area PD, the equivalent perimeter of the source active area PS, the equivalent area of the drain active area AD, the equivalent area of the source active area AS, and the equivalent number of parallel tubes m. Other parameters remain unchanged, can be widely and effectively applied in the industry, and can obtain high-precision body effect, short channel effect, long channel effect, DIBL and other conventional device physical phenomenon parameters based on the physical model, accurately simulate the performance of the anti-radiation semiconductor device, and accurately simulate the I D -V G The current characteristic error is basically kept below 5%, which can accurately reflect the performance of the anti-radiation square ring gate NMOSFET semiconductor device, overcome the time delay between the simulation of the anti-radiation square ring gate NMOSFET semiconductor device and the semiconductor process, and provide a reliable research foundation and effective auxiliary guidance for early circuit design and technical development based on the anti-radiation square ring gate NMOSFET semiconductor device.

[0130] The anti-radiation square ring gate NMOSFET semiconductor device modeling method provided by the application is based on the existing BSIM3V3.2, adopts a standard complete model, extracts key process parameters of a straight gate MOSFET semiconductor device by aiming at a foundry PDK library, establishes a physical model of a ladder gate MOSFET semiconductor device according to the process parameters, clearly defines the geometric structure and equivalent sub-circuit topology of the anti-radiation square ring gate MOSFET semiconductor device, inversely extracts part of important structure topology characteristic parameters of the model according to the physical model and the circuit topology, combines other model process parameters, establishes a complete BSIM3V3.2 complete model, and realizes simulation and simulation of the anti-radiation semiconductor device. In the semiconductor device modeling method provided by the application, there are about 194 BSIM3V3.2 model parameters, only 6 parameters are modified, and other parameters remain unchanged, so the method can be widely and effectively applied in the industry.

[0131] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method, characterized in that: The following steps are involved: 1) Obtain key process parameters of direct-gate MOSFET semiconductor devices; 2) Establish an equivalent physical model of a trapezoidal gate semiconductor device based on key process parameters; 3) Based on the trapezoidal gate semiconductor device, construct the geometric structure and equivalent sub-circuit topology of the radiation-resistant square-gate-all-around MOSFET semiconductor device; 4) Extract the important structural topological characteristic parameters of the radiation-resistant square-gate-all-around MOSFET semiconductor device model based on the equivalent physical model and equivalent subcircuit topology; 5) Extracting other model process parameters of the square-ring gate MOSFET semiconductor device and using important structural topological characteristic parameters for simulation to obtain a radiation-resistant square-ring gate MOSFET semiconductor device model; In step 4), the important structural topological characteristic parameters include: the trapezoidal gate width W eq , drain active area perimeter PD, source active area perimeter PS, drain active area area AD, source active area area AS, number of parallel tubes m, where: PD=W eff PS=2·W eff +4·L eff +2·L S Among them, L eff is the effective channel length of the straight-gate device, W eff is the effective active area width of the drain of the straight-gate device, L S is the length of the source active region in the channel direction of each sub-device component; The L eff and W eff Specifically: Where L is the gate length of the straight-gate device, W is the active area width of the drain of the straight-gate device, and L INT is the straight gate channel length offset fitting parameter, L L is the channel length correlation coefficient of the straight gate channel length offset, L W is the channel width correlation coefficient of the straight gate channel length offset, L WL is the length-width cross-term coefficient of the straight gate channel length offset, L LN is the channel length-related power of the straight gate channel length offset, L WN is the power of the channel width related to the straight gate channel length offset, W INT is the straight gate channel width offset fitting parameter, W L is the channel length correlation coefficient of the straight gate channel width offset, W W is the channel width correlation coefficient of the straight gate channel width offset, W WL is the length-width cross-term coefficient of the straight gate channel width offset, W LN is the channel length-dependent power of the straight gate channel width offset, W WN is the channel width-related power of the straight gate channel width offset.

2. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: The key process parameters include: the gate length L of the straight-gate device and the active area width W of the drain of the straight-gate device.

3. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: In step 2), the equivalent physical model is determined by the following formula: Among them, W trapezoid is the equivalent active area width of the trapezoidal gate, α is the bottom angle of the trapezoidal gate, L is the gate length of the straight-gate device, and W is the active area width of the drain of the straight-gate device.

4. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: The step 3) is specifically as follows: The ring-gate semiconductor device is equivalent to four sub-devices with the same electrical performance and indicators divided equally along the diagonal line. Each trapezoidal gate semiconductor device is used as a sub-device, and they are connected in parallel to construct an equivalent sub-circuit topology of the radiation-resistant square ring-gate MOSFET semiconductor device.

5. The radiation-resistant square-gate-all-around MOSFET semiconductor device modeling method according to claim 1, characterized in that: In the step 5), other model process parameters are extracted using a BSIM3V3.2-specific extraction algorithm.

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