Double-pulse test platform optimization method and device

Abstract

The invention discloses a double-pulse test platform optimization method and device, and the method comprises the steps: building a double-pulse test platform simulation model according to the actual structure of each element in a test loop; elements in the test loop comprise an IGCT, a diode and a clamping capacitor. And taking the stray inductance value as a target function, and optimizing spatial layout parameters of each element in the double-pulse test platform simulation model by adopting a PSO algorithm to obtain an optimal double-pulse test platform spatial layout. According to the invention, the spatial layout of the platform can be effectively optimized, the stray inductance of a loop is reduced, the overvoltage borne by the IGCT at the turn-off moment in the dipulse test process is suppressed, and the problems of large voltage overshoot and easy damage of devices in the dipulse test are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of test platform optimization, and in particular to a double-pulse test platform optimization method and device. Background Art

[0002] In recent years, with the rapid development of power electronics technology, power devices have become crucial in many application scenarios. Integrated gate-commutated thyristors (IGCTs) are widely used in the field of large-capacity power electronic converters due to their strong current-carrying capacity, high reliability and low manufacturing cost. Dynamic characteristic tests based on double-pulse tests can reveal the switching characteristics of devices under different working conditions, so studying double-pulse tests is crucial for in-depth understanding and application of IGCTs. However, the stray inductance of the loop in the double-pulse test will generate an induced voltage at the moment the device is turned off, and the overvoltage generated by the superposition of the bus voltage on the IGCT will increase the electrical stress and turn-off loss of the device. In severe cases, it may exceed the safe operating range of the device and cause device failure. Summary of the invention

[0003] In response to the problems in the prior art, an embodiment of the present invention provides a dual-pulse test platform optimization method and device. The present invention can effectively optimize the platform spatial layout, reduce the loop stray inductance, and suppress the overvoltage that the IGCT is borne at the moment of shutdown during the dual-pulse test, thereby solving the problems of large voltage overshoot and easy damage to devices in the dual-pulse test.

[0004] An embodiment of the present invention provides a double pulse test platform optimization method, comprising:

[0005] According to the actual structure of each component in the test loop, a double pulse test platform simulation model is established; the components in the test loop include IGCT, diode, and clamping capacitor;

[0006] Taking the stray inductance value as the objective function, the PSO algorithm is used to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout.

[0007] In one embodiment, the spatial layout parameters of each component include the coordinate position of each component and the length of a busbar connecting each component.

[0008] In one embodiment, the coordinate position of each element is the center position of the bottom surface of each element.

[0009] In one embodiment, the bottom center position of the target element is set as the origin of the coordinate system, and the coordinate positions of other elements are obtained according to the relative positions of other elements and the target element.

[0010] In one embodiment, the IGCT and the diode are connected via a first busbar, the IGCT and the clamping capacitor are connected via a second busbar, and the diode and the clamping capacitor are connected via a third busbar.

[0011] In one embodiment, the method of taking the stray inductance value as the objective function and using the PSO algorithm to optimize the spatial layout parameters of each component in the dual pulse test platform simulation model to obtain the optimal dual pulse test platform spatial layout includes:

[0012] Taking the stray inductance value as the objective function, the first busbar length, the second busbar length, the third busbar length and the coordinate position of each component as the optimal particles in the PSO algorithm, the optimal first busbar length, the second busbar length, the third busbar length and the coordinate position of each component in the spatial layout of the double-pulse test platform are obtained through optimization iteration.

[0013] The embodiment of the present invention further provides a double pulse test platform optimization device, comprising:

[0014] A model building module is used to establish a double pulse test platform simulation model according to the actual structure of each component in the test loop; the components in the test loop include IGCT, diode, and clamping capacitor;

[0015] The optimization module is used to use the stray inductance value as the objective function and adopt the PSO algorithm to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout.

[0016] An embodiment of the present invention further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above methods when executing the computer program.

[0017] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0018] An embodiment of the present invention further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0019] The embodiment of the present invention provides a method and device for optimizing a dual pulse test platform. The present invention can effectively optimize the platform space layout, reduce the loop stray inductance, suppress the overvoltage borne by the IGCT at the moment of shutdown during the dual pulse test, and solve the problem of large voltage overshoot and easy damage to the device in the dual pulse test. The present invention can be applied to the fields of power device stray parameter control and experimental platform optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0021] Figure 1 A schematic diagram of IGCT turn-off overvoltage provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of an IGCT double pulse test circuit provided by an embodiment of the present invention;

[0023] Figure 3 Schematic diagram of the process flow of the double pulse test platform optimization method provided by the embodiment of the present invention

[0024] Figure 4 A schematic diagram of the optimization process using the PSO algorithm provided in an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of the change of stray inductance value during the optimization process provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of a bus voltage shutdown waveform during an optimization process provided by an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of the change in overvoltage amplitude before and after optimization provided by an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of the structure of a double pulse test platform optimization device provided by an embodiment of the present invention;

[0029] Fig. 9 A schematic diagram of a computer device entity structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0031] In order to facilitate understanding of the technical solution provided by this application, the research background of the technical solution of this application is briefly described below.

[0032] like Figure 1The figure shows the schematic diagram of IGCT turn-off overvoltage provided by an embodiment of the present invention. The stray inductance of the loop in the double pulse test will generate an induced voltage at the moment of device turn-off, which will be superimposed on the bus voltage to generate overvoltage on the IGCT, thereby increasing the electrical stress and turn-off loss of the device. In severe cases, it may exceed the safe operating range of the device and cause device failure.

[0033] like Figure 2 FIG. 1 is a schematic diagram of an IGCT double pulse test circuit provided by an embodiment of the present invention. In the IGCT double pulse test circuit, C DC It is the bus capacitor that provides the DC bus voltage. Before the experiment begins, C DC It is charged to the set value, and then uses its discharge process to provide energy for the test circuit. Load inductance L load It can control the current in the loop. When the IGCT is turned on, C DC To L load Discharge causes the current in the circuit to rise. When the current reaches the set value of the test, the IGCT is turned off, and the current flowing through L load The current is commutated by the anti-parallel diode FWD. The clamping capacitor C CL With freewheeling diode D CL , absorption capacitor R CL Together they form a clamping circuit that can suppress the inductance L at the moment of IGCT shutdown. i The voltage overshoot caused by L CL To test the equivalent stray inductance in the circuit, the test circuit includes IGCT, clamping capacitor C CL 、Diode D CL And FWD. The present invention is mainly aimed at optimizing the IGCT double pulse test circuit in the double pulse test platform. Therefore, the components in the test loop need to include IGCT, diode, and clamping capacitor. Among them, IGCT and diode are both crimping type devices, such as IGCT clamps and diode clamps, and the clamps are required to provide clamping force to ensure their normal operation. The capacitor can adopt a clamping capacitor. The clamping capacitor mainly plays the role of filtering, voltage stabilization and voltage limiting in the circuit. It can prevent the instability of the bias voltage of the input signal, block high-frequency noise, filter out interference signals in the output signal, and maintain the stability of the output signal.

[0034] like Figure 3 The figure is a schematic flow chart of a dual pulse test platform optimization method provided by an embodiment of the present invention. The embodiment of the present invention provides a dual pulse test platform optimization method, comprising:

[0035] S101: establishing a double pulse test platform simulation model according to the actual structure of each component in the test loop; the components in the test loop include IGCT, diode, and clamping capacitor;

[0036] S102: Taking the stray inductance value as the objective function, the PSO algorithm is used to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout.

[0037] Specifically, the present invention establishes a three-dimensional physical model of each component according to the actual size of the IGCT fixture, the diode fixture and the clamping capacitor, and can use Python to control the multi-physics field simulation software to simulate the stray inductance, and use Python scripts to interact with the multi-physics field simulation software. The present invention can realize simulation automation by writing an efficient Python script, and the specific steps include opening the model, adjusting parameters, running the simulation and extracting the inductance, etc., and the use of Python scripts effectively improves the work efficiency. The present invention uses Python scripts to input the parameter values ​​obtained by each round of optimization of the PSO algorithm into the multi-physics field simulation software to calculate the loop stray inductance at this time, and the result will be used as a reference for the next round of optimization, so as to iterate and obtain the optimal dual-pulse test platform spatial layout when the stray inductance is minimum. After the modeling is completed, the present invention uses the stray inductance value as the objective function, and uses the PSO algorithm (i.e., the particle swarm algorithm) to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout. The particle swarm algorithm designs a massless particle, and the particle has only two attributes: speed and position, the speed represents the speed of movement, and the position represents the direction of movement. Each particle searches for the optimal solution in the search space individually, records it as the current individual extreme value, and shares the individual extreme value with other particles in the entire particle group, finds the best individual extreme value as the current global optimal solution of the entire particle group, and all particles in the particle group adjust their speed and position according to the current individual extreme value they find and the current global optimal solution shared by the entire particle group. The present invention can effectively optimize the platform space layout, reduce the stray inductance of the loop, suppress the overvoltage that the IGCT bears at the moment of shutdown during the double pulse test, and solve the problem of large voltage overshoot and easy damage of the device in the double pulse test.

[0038] It is worth noting that according to the actual structure of each component in the test loop, the present invention can establish a dual-pulse test platform simulation model through a simulation platform, or use a third-party three-dimensional modeling software to establish a dual-pulse test platform simulation model and then import it into the simulation platform.

[0039] In one embodiment, the spatial layout parameters of each component include the coordinate position of each component and the length of a busbar connecting each component.

[0040] Specifically, since the stray inductance of the test loop changes with the spatial layout of the double-pulse test platform, the position of each component and the length of the busbar connecting the components are parameterized to obtain the coordinate position of each component and the length of the busbar connecting the components.

[0041] In one embodiment, the coordinate position of each element is the center position of the bottom surface of each element.

[0042] Specifically, the present invention places the IGCT, diode and clamping capacitor on the same horizontal plane by default. For the convenience of calculation, the bottom center position of the IGCT, diode and clamping capacitor is used as the coordinate position of each component. When calculating the bottom center position of each component, the area of ​​the fixture is not considered, and only the physical part of the IGCT, diode and clamping capacitor is considered.

[0043] In one embodiment, the bottom center position of the target element is set as the origin of the coordinate system, and the coordinate positions of other elements are obtained according to the relative positions of other elements and the target element.

[0044] Specifically, the IGCT is set as the target element, that is, the IGCT is selected as the reference object of the spatial layout, and the coordinates of the center position of the bottom surface of the IGCT are set to (0, 0, 0). On this basis, the coordinates of the center position of the bottom surface of the clamping capacitor are set to (X1, Y1, Z1), and the coordinates of the center position of the bottom surface of the diode are set to (X2, Y2, Z2). Of course, the present invention can also select the clamping capacitor as the reference object of the spatial layout, that is, the coordinates of the center position of the bottom surface of the clamping capacitor are set to (0, 0, 0), the coordinates of the center position of the bottom surface of the IGCT are set to (X1, Y1, Z1), and the coordinates of the center position of the bottom surface of the diode are set to (X2, Y2, Z2). Alternatively, the present invention can also select the diode as the reference object of the spatial layout, that is, the coordinates of the center position of the bottom surface of the diode are set to (0, 0, 0), the coordinates of the center position of the bottom surface of the IGCT are set to (X1, Y1, Z1), and the coordinates of the center position of the bottom surface of the clamping capacitor are set to (X2, Y2, Z2).

[0045] In one embodiment, the IGCT and the diode are connected via a first busbar, the IGCT and the clamping capacitor are connected via a second busbar, and the diode and the clamping capacitor are connected via a third busbar.

[0046] Specifically, the test circuit of the present invention needs to be connected using three busbars, wherein the IGCT is connected to the diode through the first busbar, the IGCT is connected to the clamping capacitor through the second busbar, and the diode is connected to the clamping capacitor through the third busbar. The lengths of the first busbar, the second busbar, and the third busbar are respectively L A , L B and LC In addition, the present invention also sets the width and thickness of the three busbars to 80 mm and 8 mm respectively, and sets the minimum insulation spacing between each component and the busbar to 10 mm. The value of each parameter is subject to the conditions such as the layout of each component, the connection sequence and the insulation spacing. Taking these factors into consideration, the value range of each parameter is determined as shown in Table 1.

[0047] Table 1

[0048]

[0049]

[0050] In one embodiment, the method of taking the stray inductance value as the objective function and using the PSO algorithm to optimize the spatial layout parameters of each component in the dual pulse test platform simulation model to obtain the optimal dual pulse test platform spatial layout includes:

[0051] Taking the stray inductance value as the objective function, the first busbar length, the second busbar length, the third busbar length and the coordinate position of each component as the optimal particles in the PSO algorithm, the optimal first busbar length, the second busbar length, the third busbar length and the coordinate position of each component in the spatial layout of the double-pulse test platform are obtained through optimization iteration.

[0052] Specifically, the PSO algorithm (also called particle swarm algorithm) is an evolutionary computing technology that originated from the study of the foraging behavior of bird flocks. The basic principle of the PSO algorithm is to find the optimal solution through collaboration and information sharing among individuals in the group. The PSO algorithm simulates a flock of birds by designing a massless particle swarm, and each particle has only two attributes: speed and position. Initially, each particle independently searches for the individual optimal solution in space, and then shares information with other particles to find the global optimal solution for the entire particle swarm. Finally, all particles adjust their speed and position according to the individual optimal solution and the global optimal solution. The particle speed update formula is as follows.

[0053] v k+1 =ω·v k +c1·r1·(x p,k -x k )+c2·r2·(x g,k -x k );

[0054] In the formula, v k+1 represents the velocity of the particle in the k+1th iteration; ω is the inertia weight, which affects the global search capability of the algorithm; v k is the velocity of the particle in the kth iteration; c1 and c2 are acceleration coefficients, which together affect the velocity update of the particle; r1 and r2 are random numbers in the interval [0,1], which can increase the randomness of the algorithm; xp,k represents the individual optimal position found by the particle before the kth iteration, and x g,k represents the global optimal position found by the particle swarm before the kth iteration; x k is the position of the particle in the kth iteration. The particle position update formula is as follows.

[0055] x k+1 =x k +v k+1 ;

[0056] In the formula, x k+1 represents the position of the particle in the k+1th iteration.

[0057] At the beginning, the PSO algorithm randomly assigns an initial speed and position to each particle. The initial position of each particle is first used as its individual optimal position, and the best initial position of the entire particle group is used as the global optimal position. Then, the speed of the particle in the next iteration is updated according to the individual optimal position, the global optimal position, and the current speed, and the position of the particle in the next iteration is updated using the speed and current position of the next iteration. Then, the objective function is used to evaluate the current position of each particle. If the current position is better than the individual optimal position of the particle, the individual optimal position of the particle is updated. If the current position is better than the global optimal position, the global optimal position is updated. Finally, if the number of calculations reaches the set maximum number of iterations or the change in the global optimal position is less than the set threshold, the algorithm is stopped.

[0058] like Figure 4 The figure shows a schematic diagram of an optimization process using a PSO algorithm provided by an embodiment of the present invention. The optimization method proposed in this patent uses a PSO algorithm to optimize the platform space layout to reduce the stray inductance in the loop. First, based on the value range of each parameter, the position and speed of each particle, that is, the parameter value and change trend, are initialized, and the maximum number of iterations is set to 50 times. The stray inductance value obtained by simulation is used as the objective function to evaluate the current position of each particle (that is, the current value of each parameter), and the position with the smallest stray inductance is selected as the optimal position, and the individual optimal position x obtained in each round of optimization is recorded. p,k and the global optimal position x g,k, and update the position and speed of the particle in the next round of optimization accordingly. Among them, the position of the particle is the value of the parameter, and the stray inductance is used as the objective function for evaluation. The value of the parameter that minimizes the stray inductance is the optimal value; the position of the particle that minimizes the stray inductance is the optimal position. Secondly, the three-dimensional model established according to the actual structure of each component in the test circuit is input into the multi-physics field simulation software, and on this basis, the conditions required for stray inductance simulation are set, including material parameters, boundary conditions, excitation position, mesh division, etc. Then, Python is used to control the simulation process, and the parameter values ​​obtained in each round of optimization are input into the multi-physics field simulation platform for stray inductance simulation calculation. Then, according to the obtained stray inductance value, that is, the objective function, the direction of the next round of optimization is adjusted, so as to iteratively obtain the optimal spatial layout of the dual-pulse test platform. Finally, the optimization results of the stray inductance and the best values ​​of each parameter are output.

[0059] like Figure 5 The figure shows the variation of stray inductance value during the optimization process provided by the embodiment of the present invention. The specific simulation steps of the present invention include opening the model, modifying parameters, running the simulation and extracting results. Fig. 9 This is the extraction result during the optimization process, which reflects the change of stray inductance. As can be seen from the figure, with the continuous optimization, the stray inductance value gradually decreases, and the stray inductance value remains basically unchanged after the 10th round. It can be considered that the particle swarm has basically found the optimal solution at this time.

[0060] It is worth noting that the present invention uses the stray inductance value as the objective function of the PSO algorithm in order to determine which of several solutions is the optimal solution. The smaller the stray inductance value, the better the spatial layout, that is, the better the values ​​of the parameters of the spatial layout of the dual-pulse test platform (the coordinate position of each component and the length of the busbar connecting each component). In the present invention, finding the optimal position of the particle in the PSO algorithm is to find the optimal solution of the parameters of the spatial layout of the dual-pulse test platform. In the simulation software, when the position of the particle is determined, that is, the coordinate position of each component and the length of each busbar are determined, the geometric structure of the entire connection loop is determined, and then the simulation platform can be used to calculate the size of the stray inductance. The parameter value is randomly selected based on the speed of the particle group, that is, the direction of parameter change, and the change direction determined by random selection is gradually approached to the optimal solution. The simulation calculation of stray inductance involves multiple physical equations, which are mainly used to simulate the distribution and behavior of electromagnetic fields in conductors and surrounding media. Maxwell's equations are the basis of electromagnetic field theory and are used to describe the relationship between electric and magnetic fields. The quasi-static form of Maxwell's equations is usually used in the calculation of stray inductance. The specific expression is as follows:

[0061]

[0062] In the formula, D is the electric displacement field, which reflects the relationship between the electric field and the polarization of the medium; ρ is the charge density, which indicates the amount of charge per unit volume; B is the magnetic induction intensity, which is used to describe the strength and direction of the magnetic field; E is the electric field intensity, which is used to describe the effect of the electric field on the charge; H is the magnetic field intensity, which indicates the reaction of the magnetic field to the current; J is the current density, which is used to describe the current intensity per unit area; The direct multiplication represents the gradient, the dot product represents the divergence, and the cross product represents the curl; t represents the optimization time.

[0063] The current continuity equation describes the conservation of charge, which states that the current flowing into a region is equal to the rate at which the charge in that region changes, as shown below.

[0064]

[0065] Further, Poisson's equation is shown as follows, which describes the potential distribution in a static electric field.

[0066]

[0067] Where φ is the electric potential and ε is the dielectric constant.

[0068] Poisson's equation is often used in the calculation process to solve the electric potential distribution and then calculate the electric field strength.

[0069] Furthermore, the simulation of stray inductance is based on the law of electromagnetic induction, using the following basic formulas for self-inductance and mutual inductance:

[0070]

[0071] Where L is self-inductance or mutual inductance. Self-inductance is the ratio of magnetic flux generated by current change in the same circuit to the current, while mutual inductance is the ratio of magnetic flux to current between different circuits. Ф is magnetic flux, which is used to measure the strength of the magnetic field passing through a surface. The simulation calculates the self-inductance and mutual inductance by solving the magnetic flux between each conductor. I represents current.

[0072] like Figure 6 The figure shows a schematic diagram of the bus voltage shutdown waveform during the optimization process provided by an embodiment of the present invention. In one embodiment, the initial voltage of the bus capacitor is set to 500V, 1000V, 1500V and 2000V respectively, and the stray inductance value after the first round of optimization is used as the input of "before optimization", and the stray inductance value after the 50th round of optimization is used as the input of "after optimization". When the bus voltage is 2000V, the overvoltage amplitude of the IGCT at the first shutdown moment before optimization is 1753V, and the overvoltage amplitude of the IGCT at the first shutdown moment after optimization is 1263V, and the overvoltage amplitude is reduced by 28%.

[0073] like Figure 7The diagram shows the change of overvoltage amplitude before and after optimization provided by an embodiment of the present invention. In one embodiment, under different voltage levels, the overvoltage amplitude of the optimized IGCT at the first shutdown moment is reduced by 28% compared with that before optimization, which shows that the proposed optimization method can effectively optimize the spatial layout of the double pulse test platform, reduce the stray inductance of the loop, and suppress the overvoltage amplitude generated during shutdown. The optimized parameter values ​​are shown in Table 2.

[0074] Table 2

[0075]

[0076]

[0077] like Figure 8 As shown, an embodiment of the present invention further provides a dual-pulse test platform optimization device, which includes a model building module and an optimization module.

[0078] The model building module is used to establish a double pulse test platform simulation model according to the actual structure of each component in the test loop; the components in the test loop include IGCT, diode, and clamping capacitor;

[0079] The optimization module is used to take the stray inductance value as the objective function and adopt the PSO algorithm to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout.

[0080] The embodiments of the apparatus provided in the embodiments of the present invention can be specifically used to execute the processing flow of the above-mentioned method embodiments, and its functions are not described in detail here, and reference can be made to the detailed description of the above-mentioned method embodiments.

[0081] like Fig. 9 As shown, an embodiment of the present invention further provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above methods when executing the computer program.

[0082] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0083] An embodiment of the present invention further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0084] In the embodiment of the present invention, compared with the technical solutions in the prior art, by first designing a dual-key phase synchronous sampling method, the key phase signals of the driving shaft and the driven shaft on both sides of the clutch are collected, measured and analyzed in real time, and an SSS clutch meshing position online measurement method is formulated to quantitatively correspond the vibration of the shaft system with the meshing position, and determine the optimal meshing position. Based on the characteristic that the measured angle difference is a periodic cyclic series with equal intervals when the speeds of the driving shaft and the driven shaft are constant (but not the same), the measured angle difference signal is connected to the speed control system, and the SSS clutch driving shaft speed increase rule is designed. According to this rule, the SSS clutch is controlled to engage at a fixed point, eliminating the adverse effects of the random meshing position of the SSS clutch on the vibration of the shaft system, and realizing the controllable vibration of the shaft system of the power system using the SSS clutch, thereby improving the safety and reliability of the equipment.

[0085] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0086] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0087] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0088] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0089] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A double pulse test platform optimization method, characterized in that: include: According to the actual structure of each component in the test loop, a double pulse test platform simulation model is established; the components in the test loop include IGCT, diode, and clamping capacitor; Taking the stray inductance value as the objective function, the PSO algorithm is used to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout.

2. The method according to claim 1, characterized in that: The spatial layout parameters of each component include the coordinate position of each component and the length of the busbar connecting the components.

3. The method according to claim 2, characterized in that: The coordinate position of each element is the center position of the bottom surface of each element.

4. The method according to claim 3, characterized in that: The bottom center position of the target component is set as the origin of the coordinate system, and the coordinate positions of other components are obtained according to the relative positions of other components and the target component.

5. The method according to claim 4, characterized in that: The IGCT and the diode are connected via a first busbar, the IGCT and the clamping capacitor are connected via a second busbar, and the diode and the clamping capacitor are connected via a third busbar.

6. The method according to claim 5, characterized in that The method of taking the stray inductance value as the objective function and using the PSO algorithm to optimize the spatial layout parameters of each component in the dual pulse test platform simulation model to obtain the optimal dual pulse test platform spatial layout includes: Taking the stray inductance value as the objective function, the first busbar length, the second busbar length, the third busbar length and the coordinate position of each component as the optimal particles in the PSO algorithm, the optimal first busbar length, the second busbar length, the third busbar length and the coordinate position of each component in the spatial layout of the double-pulse test platform are obtained through optimization iteration.

7. A double pulse test platform optimization device, characterized in that: include: A model building module is used to establish a double pulse test platform simulation model according to the actual structure of each component in the test loop; the components in the test loop include IGCT, diode, and clamping capacitor; The optimization module is used to use the stray inductance value as the objective function and adopt the PSO algorithm to optimize the spatial layout parameters of each component in the dual-pulse test platform simulation model to obtain the optimal dual-pulse test platform spatial layout.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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