A passive device layout structure

Abstract

The present application provides a passive device layout structure, including: a layout core area, including at least one resistor and / or at least one capacitor; a peripheral buffer area, which is a hollow rectangle and is arranged outside the layout core area, and the safety distance between the peripheral buffer area and the layout core area is greater than the safety distance threshold; wherein the peripheral buffer area includes an odd number of row buffer unit groups, the row buffer unit groups located in odd rows are arranged in a forward direction, and the row buffer unit groups located in even rows are arranged in a reverse direction, so that the peripheral buffer area has a power rail and a ground rail, and the boundary of the row buffer unit group forms a rectangular layout and routing boundary to be recognized by a layout and routing tool, which can solve the existing problem in the field of analog circuits, especially in the layout design of passive devices, that the layout design efficiency of passive devices is low due to reliance on manual design by engineers.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a passive device layout structure. Background Art

[0002] Integrated circuit layout design refers to mapping the circuit design circuit diagram or circuit description language to the physical description level, so that the designed circuit can be mapped to the wafer for production. Integrated circuits include analog circuits, digital circuits and hybrid circuits. At present, in the field of digital circuits, due to the design of its standard cell library and mature layout and routing tools, digital circuits have achieved highly efficient automated layout design. In the field of analog circuits, especially the layout design of passive devices, it usually relies on manual design by engineers, which makes the layout design efficiency of passive devices low. Summary of the invention

[0003] The embodiment of the present application provides a passive device layout structure, which can solve the problem that the layout design of passive devices in the field of analog circuits, especially in the field of passive device layout design, relies on manual design by engineers, resulting in low efficiency of passive device layout design.

[0004] In a first aspect, an embodiment of the present application provides a passive device layout structure, including: The core area of ​​the layout includes at least one resistor and / or at least one capacitor; The peripheral buffer area is in the form of a hollow rectangle, is arranged outside the core area of ​​the layout, and has a safety distance greater than a safety distance threshold from the core area of ​​the layout; Among them, the peripheral buffer area includes an odd number of row buffer unit groups, the row buffer unit groups located in odd rows are arranged in a forward direction, and the row buffer unit groups located in even rows are arranged in a reverse direction, so that the peripheral buffer area has power rails and ground rails, and the boundaries of the row buffer unit groups form a rectangular layout and routing boundary to be recognized by the layout and routing tools.

[0005] In some embodiments, the at least one resistor is a plurality of resistors, and the resistor is at least one of a polysilicon resistor, an N-well resistor, and a metal resistor.

[0006] In some embodiments, the layout structure of the polysilicon resistor includes: P-type implantation region; A polysilicon layer, located in the P-type implantation region; The metal layer is located in the polysilicon layer and is provided with a connecting through hole, wherein the connecting through hole connects the metal layer and the polysilicon layer.

[0007] In some embodiments, the at least one capacitor is a plurality of capacitors, and the capacitor is at least one of a finger capacitor, a plate capacitor, and a MOS tube capacitor.

[0008] In some embodiments, the layout structure of the inter-finger capacitor includes: A stacked metal layer positive electrode having positive electrode metal fingers disposed thereon; The stacked metal layer negative electrode is arranged opposite to the stacked metal layer positive electrode, and is provided with negative electrode metal fingers.

[0009] In some embodiments, a preset sub-spacing is set between a plurality of the resistors, between a plurality of the capacitors, or between the resistor and the capacitor, and the preset sub-spacing is greater than a sub-spacing threshold.

[0010] In some embodiments, the row buffer unit group includes a plurality of buffer units, the top of each buffer unit has a buffer power rail, and the bottom of each buffer unit has a buffer ground rail.

[0011] In some embodiments, the height of the buffer unit is equal to the digital ground spacing between the power rail and the ground rail in the digital standard cell, and the width of the buffer unit is equal to a positive integer multiple of the common polysilicon spacing.

[0012] In some embodiments, the buffer cell is a well contact cell and / or a filling cell.

[0013] In some embodiments, the number of rows of the peripheral buffer area is the smallest positive odd number greater than or equal to 3 that makes the safety distance greater than the safety distance threshold, and the number of columns of the peripheral buffer area is the smallest positive integer greater than or equal to 3 that makes the safety distance greater than the safety distance threshold.

[0014] Compared with the prior art, the passive device layout structure provided in the embodiment of the present application can set resistors and / or capacitors in the layout core area by setting the layout core area, and can avoid mutual influence between the layout core area and the peripheral buffer area by setting the peripheral buffer area outside the layout core area, the peripheral buffer area is rectangular, and the safety distance between the peripheral buffer area and the layout core area is greater than the safety distance threshold; by arranging the row buffer unit groups located in odd rows in the peripheral buffer area in a forward direction and the row buffer unit groups located in even rows in a reverse direction, the peripheral buffer area can have power rails and ground rails; by forming a rectangular layout and routing boundary through the boundary of the row buffer unit group, the passive device layout structure can be recognized by the layout and routing tools, thereby realizing the automated layout design of passive devices and improving the efficiency of passive device layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Hereinafter, the present invention will be described in more detail based on embodiments and with reference to the accompanying drawings.

[0016] Figure 1 is a schematic diagram of a passive device layout structure provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a polysilicon resistor layout structure provided by an embodiment of the present invention; Figure 3 is a schematic diagram of a layout structure of an inter-finger capacitor provided by an embodiment of the present invention; Figure 4 is a cross-sectional view of a layout structure of an inter-finger capacitor provided by an embodiment of the present invention; Figure 5 is a schematic diagram of a common polysilicon spacing provided by an embodiment of the present invention; Figure 6 is a schematic diagram of the arrangement of buffer units provided by an embodiment of the present invention; Figure 7 is a layout and routing boundary schematic diagram provided by an embodiment of the present invention; Figure 8 is a schematic diagram of buffer unit splicing provided by an embodiment of the present invention; Fig. 9 A schematic diagram of a passive device layout structure containing multiple resistors provided by an embodiment of the present invention Fig.10 It is a schematic diagram of a passive device layout structure including a single capacitor provided by an embodiment of the present invention; Fig.11 It is a schematic diagram of a passive device layout structure containing multiple capacitors provided by an embodiment of the present invention; Fig.12 It is a schematic diagram of the horizontal adjacency of a passive device layout structure provided by an embodiment of the present invention; Fig.13 It is a schematic diagram of the vertical adjacency of a passive device layout structure provided by an embodiment of the present invention; Fig.14 It is a flow chart of a method for using a passive device layout structure provided by an embodiment of the present invention.

[0017] Reference numerals: 10. Core area of ​​the territory; 110, resistor; 1101, P-type implantation region; 1102, polysilicon layer; 1103, metal layer; 1104, connecting through hole; 120, capacitor; 1201, positive electrode of stacked metal layer; 1202, positive electrode metal fork finger; 1203, negative electrode of stacked metal layer; 1204, negative electrode metal fork finger; 20. Peripheral buffer area; 210. Row buffer unit group; 2101. Buffer unit; 2101A. Buffer power rail; 2101B. Buffer ground rail; 2102. Layout and routing boundary. DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings.

[0019] Integrated circuit layout design refers to mapping the circuit design circuit diagram or circuit description language to the physical description level, so that the designed circuit can be mapped to the wafer for production. The layout is a graphic containing relevant physical information such as the device type, device size, relative position between devices, and connection relationship between each device of the integrated circuit. These graphics are composed of graphics located on different drawing layers.

[0020] Integrated circuits include analog and mixed-signal circuits, which have always been an important part of the electronics industry. The demand for analog and mixed circuits has been growing year by year with the development of emerging technologies such as the Internet of Things and autonomous driving. However, the layout design of analog circuits has relied on manual design by layout design engineers in the past few decades. This work consumes a lot of manpower and time. Engineers often need weeks or even months to do manual design. When analog circuits are designed using more advanced process nodes, the design rules corresponding to the process (abbreviated as DR, Design Rule) will also become more complicated, which further increases the cost of analog circuit layout design. In contrast, in the field of digital circuits, due to the design of standard cell libraries and mature layout and routing tools, digital circuits have achieved highly efficient automated layout design.

[0021] At present, the industry generally uses parameterized cells (PCELLs) to manually design the layout structure of passive devices. Although this method can realize the automated design of the internal layout structure of passive devices to a certain extent, when a circuit contains many passive devices or MOS tubes (Metal Oxide Semiconductor, field effect transistors), PCELLs cannot be directly spliced ​​together. Instead, a lot of manual adjustment and design are required, which is very labor-intensive and time-consuming.

[0022] First, as Figure 1 , Figure 6 , Figure 7 As shown, in order to solve the above technical problems, the embodiment of the present application provides a passive device layout structure, including: The layout core area 10 includes at least one resistor 110 and / or at least one capacitor 120; The peripheral buffer area 20 is in the form of a hollow rectangle, is arranged outside the core area 10 of the layout, and has a safety distance greater than a safety distance threshold between the peripheral buffer area 20 and the core area 10 of the layout; Among them, the peripheral buffer area 20 includes an odd number of row buffer unit groups 210, the row buffer unit groups 210 located in odd rows are arranged in a forward direction, and the row buffer unit groups 210 located in even rows are arranged in a reverse direction, so that the peripheral buffer area 20 has power rails and ground rails, and the boundaries of the row buffer unit groups 210 form a rectangular layout and routing boundary 2102 to be recognized by the layout and routing tools.

[0023] It should be noted that the peripheral buffer area 20 can be a hollow rectangle or a hollow square, and there is the safety distance between the inner side of the peripheral buffer area 20 and the core area 10 of the layout. By making the safety distance greater than the safety distance threshold, the core area 10 of the layout and the peripheral buffer area 20 can avoid mutual influence. The safety distance threshold is usually determined according to the design rule (abbreviated as DR, Design Rule). For example, the peripheral buffer area 20 will contain a metal layer, and the core area 10 of the layout also contains a metal layer. The design rule requires that the distance between the two metal layers should be greater than a certain value (that is, the safety distance threshold) so that the layout design will not violate the design rules. The specific value of the safety distance threshold can be set according to the actual situation, and the embodiment of the present application does not make specific limitations on this.

[0024] It should be noted that DR (design rule) is a series of physical design constraints and rules provided by semiconductor process providers to guide layout design when designing integrated circuit chips. These rules ensure that the design can be successfully manufactured under a specific manufacturing process and that the chip meets expectations in terms of function, reliability and performance, such as 1) minimum spacing, such as the minimum distance between polysilicon and polysilicon, and the minimum spacing between metal and metal; 2) minimum feature size, such as the minimum width of polysilicon and metal layers.

[0025] It should be noted that the layout and routing tool may be an EDA tool (Electronic Design Automation), but the EDA tool can only recognize regular graphics, and the EDA tool cannot recognize irregular graphics, and thus cannot perform layout and routing. By making the boundary of the row buffer unit group 210 form a rectangular layout and routing boundary 2102 (such as Figure 7 As shown), the height is an integer multiple of the power-ground track spacing, and the width is an integer multiple of the common polysilicon spacing, so that the passive device layout structure can be recognized by the EDA tool, thereby performing layout and routing.

[0026] In some embodiments, the at least one resistor 110 is a plurality of resistors 110 , and the resistor 110 is at least one of a polysilicon resistor, an N-well resistor, and a metal resistor.

[0027] In some embodiments, the layout structure of the polysilicon resistor includes: P-type implantation region 1101; A polysilicon layer 1102, located in the P-type implantation region 1101; The metal layer 1103 is located in the polysilicon layer 1102 and is provided with a connecting through hole 1104 . The connecting through hole 1104 connects the metal layer 1103 and the polysilicon layer 1102 .

[0028] It should be noted that the layout structure (or sub-layout structure) of the resistor 110 can be different resistor types of PCELL under the corresponding process, such as Fig. 9 As shown, the layout core area 10 may include a plurality of resistors 110, and the plurality of resistors 110 may be arranged along the height direction of the layout core area 10. The embodiment of the present application does not specifically limit the type of the resistor 110, wherein the layout structure of the resistor 110 may be generated by a parameterized cell (PCELL, Parametered Cell) (PCELL is a device layout generator that provides device layouts of different sizes and parameters for physical layout designers).

[0029] It should be noted that if Figure 2 As shown, two metal layers 1103 (or metal 1 layers) are usually provided, and the two metal layers 1103 are respectively located at the two ends (i.e., the left end and the right end) of the polysilicon layer 1102. The two metal layers 1103 serve as two pins of the resistor device corresponding to the layout structure of the resistor 110, wherein the polysilicon layer 1102 is the core layout structure of the resistor 110, which is used to provide resistance, and the P-type injection area 1101 serves to adjust and control the device parameters of the resistor 110.

[0030] In some embodiments, the at least one capacitor 120 is a plurality of capacitors 120 , and the capacitor 120 is at least one of a finger capacitor, a plate capacitor, and a MOS tube capacitor.

[0031] In some embodiments, Figure 3 , Figure 4 As shown, the layout structure of the inter-finger capacitor includes: A stacked metal layer positive electrode 1201, on which positive electrode metal fingers 1202 are provided; The stacked metal layer negative electrode 1203 is arranged opposite to the stacked metal layer positive electrode 1201, and a negative electrode metal fork 1204 is arranged thereon.

[0032] It should be noted that the layout structure (or sub-layout structure) of the capacitor 120 can be different capacitor types of PCELL under the corresponding process, such as Fig.10 , Fig.11 As shown, when a capacitor 120 is included in the core area 10 of the layout, the capacitor 120 is located at the center of the peripheral buffer area 20; two capacitors 120 are included in the core area 10 of the layout, and the two capacitors 120 can be arranged along the length direction of the core area 10 of the layout, wherein the interdigital capacitor is MOM, Metal-Oxide-Metal, Metal-Oxide-Metal capacitor, the plate capacitor is MIM, Metal-Insulator-Metal, Metal-Insulator-Metal capacitor, and the MOS tube capacitor is Metal-Oxide-Semiconductor, Metal-Oxide-Semiconductor capacitor. The application does not specifically limit the type of capacitor.

[0033] It should be noted that if Figure 3 , Figure 4 As shown, the top of the interdigital capacitor is the positive electrode 1201 of the stacked metal layer, and the bottom of the interdigital capacitor 120 is the negative electrode 1203 of the stacked metal layer. A plurality of positive metal fingers 1202 are provided below the positive electrode 1201 of the stacked metal layer, and a plurality of negative metal fingers 1204 are provided above the negative electrode 1203 of the stacked metal layer. The plurality of positive metal fingers 1202 and the plurality of negative metal fingers 1204 are arranged crosswise.

[0034] In some embodiments, a preset sub-spacing is set between the plurality of resistors 110 , between the plurality of capacitors 120 , or between the resistor 110 and the capacitor 120 , and the preset sub-spacing is greater than a sub-spacing threshold.

[0035] It should be noted that not only a safety distance is required between the core area 10 of the layout and the peripheral buffer area 20, but also when the core layout area includes multiple resistors 110, the distance between the multiple resistors 110 needs to be greater than the sub-spacing threshold; when the core layout area includes multiple capacitors 120, the distance between the multiple capacitors 120 needs to be greater than the sub-spacing threshold; when the core layout area includes resistors 110 and capacitors 120, the distance between the resistors 110 and the capacitors 120 needs to be greater than the sub-spacing threshold to avoid mutual influence, wherein the sub-spacing threshold can be determined according to design rules, such as, one sub-layout structure includes a metal layer, and another sub-layout structure also includes the same metal layer, and the design rules require that the spacing between such metal layers should be greater than a certain value (sub-spacing threshold), then the spacing between the two sub-layout structures should also be large enough so that the spacing between such metal layers does not violate the design rules.

[0036] In some embodiments, the row buffer unit group 210 includes a plurality of buffer units 2101 , wherein the top of each buffer unit 2101 has a buffer power rail 2101A, and the bottom of each buffer unit 2101 has a buffer ground rail 2101B.

[0037] In some embodiments, the height of the buffer unit 2101 is equal to the digital power-ground spacing between the power rail and the ground rail in the digital standard cell, and the width of the buffer unit 2101 is equal to a positive integer multiple of the common polysilicon spacing.

[0038] In some embodiments, the buffer unit 2101 is a well contact unit and / or a filling unit.

[0039] It should be noted that if Figure 5 , Figure 6 , Figure 8 As shown, the buffer units 2101 in the row buffer unit group 210 are adjacent to each other on the left and right. Usually, the number of buffer units 2101 in each row buffer unit group 210 may be different, such as Figure 6 In the figure, the row buffer unit group 210 of the first row and the fifth row includes seven left-right adjacent buffer units 2101, and the row buffer unit group 210 of the second row, the third row, and the fourth row includes two left-right non-adjacent buffer units 2101. The two non-adjacent buffer units 2101 in the second row, the third row, and the fourth row can be used to arrange the core area 10 of the layout.

[0040] It should be noted that the forward arrangement of the buffer unit 2101 (i.e., R0, the default orientation) is that the buffer power rail 2101A is at the top and the buffer ground rail 2101B is at the bottom, and the reverse arrangement of the buffer unit 2101 (i.e., MX, vertical flip) is that the buffer ground rail 2101B is at the top and the buffer power rail 2101A is at the bottom, wherein the row buffer unit group 210 located in the odd rows is arranged in the forward direction, that is, the buffer units 2101 in the odd rows are arranged in the forward direction; the row buffer unit group 210 located in the even rows is arranged in the reverse direction, that is, the buffer units 2101 in the even rows are arranged in the reverse direction, as shown in FIG. Figure 8As shown, when the two buffer units 2101 are adjacent to each other up and down, the buffer ground track 2101B of the upper buffer unit 2101 arranged in the forward direction is connected to the ground track of the lower buffer unit 2101 arranged in the reverse direction, and the buffer power track 2101A of the lower buffer unit 2101 arranged in the reverse direction is connected to the buffer power track 2101A of the buffer unit 2101 arranged in the forward direction below it, so that the upper and lower ends of the peripheral buffer area 20 are respectively the power track and the ground track (or the buffer power track 2101A and the buffer ground track 2101B), so as to facilitate the connection of the passive device layout structure with the external circuit.

[0041] It should be noted that, by making the buffer unit 2101 itself have a power rail and a ground rail (or buffer power rail 2101A, buffer ground rail 2101B), the peripheral buffer area 20 spliced ​​by the buffer unit 2101 also has a power rail and a ground rail. The width and position of the power rail and the ground rail of the buffer unit 2101 are consistent with the power rail and the ground rail of the digital standard unit under this process, so the width and position of the power rail and the ground rail of the peripheral buffer area 20 spliced ​​by it are also consistent with the power rail and the ground rail of the digital standard unit under this process.

[0042] It should be noted that if Figure 5 As shown, the common poly pitch (CPP) refers to the distance between the center lines of two adjacent polysilicon (Poly) gates in the integrated circuit design. By making the longitudinal height of the buffer unit 2101 equal to the spacing between the power-ground tracks in the digital integrated circuit under the process, the height of the layout and routing boundary 2102 of the passive device layout structure can be a positive integer multiple of the spacing between the power-ground tracks in the digital integrated circuit under the process; by making the lateral width of the buffer unit 2101 equal to a positive integer multiple of the CPP under the process, the width of the layout and routing boundary 2102 of the passive device layout structure can be a positive integer multiple of the CPP under the process, so that the layout and routing boundary 2102 of the passive device layout structure has a regular shape.

[0043] In some embodiments, the number of rows of the peripheral buffer area 20 is the smallest positive odd number greater than or equal to 3 that makes the safety spacing greater than the safety spacing threshold, and the number of columns of the peripheral buffer area 20 is the smallest positive integer greater than or equal to 3 that makes the safety spacing greater than the safety spacing threshold.

[0044] It should be noted that the number of rows of the peripheral buffer area 20 is the smallest positive odd number greater than or equal to 3 so that the safety spacing is greater than the safety spacing threshold, and the number of columns of the peripheral buffer area 20 is the smallest positive integer greater than or equal to 3 so that the safety spacing is greater than the safety spacing threshold, which can minimize the area of ​​the passive device layout structure.

[0045] It should be noted that if Fig.12 , Fig.13 As shown, when the passive device layout structure described in the embodiment of the present application is adjacent to another passive device layout structure (such as adjacent in the horizontal direction or vertical direction), they can be adjacent according to their respective layout and routing boundaries 2102, and due to the existence of the peripheral buffer area 20, the two adjacent passive device layout structures will not affect each other.

[0046] In summary, the passive device layout structure provided in the embodiment of the present application can set a resistor 110 and / or a capacitor 120 in the layout core area 10 by setting a layout core area 10, and can avoid mutual influence between the layout core area 10 and the peripheral buffer area 20 by setting the peripheral buffer area 20 outside the layout core area 10, the peripheral buffer area 20 is a hollow rectangle, and the safety distance between the peripheral buffer area 20 and the layout core area 10 is greater than the safety distance threshold; by arranging the row buffer unit group 210 located in odd rows in the peripheral buffer area 20 in a forward direction and the row buffer unit group 210 located in even rows in a reverse direction, the peripheral buffer area 20 can have a power rail and a ground rail; a rectangular layout and routing boundary 2102 is formed by the boundary of the row buffer unit group 210, so that the passive device layout structure can be recognized by the layout and routing tools, thereby realizing the automated layout design of passive devices and improving the efficiency of passive device layout design.

[0047] Second, as Fig.14 As shown, the embodiment of the present application provides a method for using a passive device layout structure, including: S101: setting device parameters of the passive device layout structure to obtain a standard unit device layout; It should be noted that the device parameters of the passive device layout structure usually depend on the requirements in the upstream circuit structure (or circuit diagram). For example, if the upstream circuit schematic diagram includes a resistor with a length of L and a width of W, then the device parameters corresponding to the resistor 110 in the sub-layout structure (or the layout core area 10) are also a resistor with a length of L and a width of W; similarly, if the upstream circuit diagram includes a MOM capacitor with a finger width of M1, a finger spacing of M2, a finger length of M3, a finger number of N, a lowest metal layer 1103 with an ordinal number of N1, and a highest metal layer 1103 with an ordinal number of N2, then the capacitor 120 in the sub-layout structure (or the layout core area 10) has the same device parameters as the capacitor in the upstream circuit diagram. After setting the device parameters of the passive device layout structure, the standard unit device layout can be obtained, and the standard unit device layout can be directly called during automatic layout and routing, thereby improving the layout and routing efficiency of passive devices.

[0048] S102: Using a GDS format file to describe the layout information of the standard unit device layout, to obtain a GDS layout file; It should be noted that the GDS format file is a binary format file that stores layout information. It is the standard format of the layout to be used when the chip is finally taped out. The GDS layout file mainly contains the following contents: 1) complete layout information, including the specific geometric shapes of all layers (metal layer, polysilicon layer, diffusion layer, mask layer, etc.); 2) the layer number and purpose of each layer. Each layer has a unique number and purpose definition, such as metal layer, contact hole, polysilicon, etc.

[0049] S103: Using an LEF format file to describe the location information of the standard cell device layout, to obtain an LEF layout file; It should be noted that the LEF format file is a text format file used to describe the physical layout information of the standard cell. The LEF layout file contains abstract information of the layout of the standard cell device layout, and provides basic information required for arrangement and routing. The LEF layout file is used to identify the location of the standard cell device layout during the layout and routing stage of the layout and routing tool. The LEF layout file contains the following contents: 1) layout information of the standard cell device layout, including the boundary, height, and width of the standard cell device layout; 2) pin information of the standard cell device layout, including the location, shape, direction, and purpose of the pin; 3) process design rules, including spacing rules between standard cell device layouts, contact hole spacing, etc.

[0050] S104: using Verilog language to describe the circuit schematic diagram and obtain a Verilog circuit file; S105: Input the GDS layout file, the LEF layout file and the Verilog circuit file into a layout and routing tool for automatic layout and routing.

[0051] It should be noted that the layout and routing tool can be an EDA tool (Electronic Design Automation). When performing layout and routing, the layout and routing tool first parses the Verilog circuit file to obtain the circuit schematic and identify which standard unit device layouts are used, and then performs layout and routing according to the information in the LEF layout file. Finally, the standard unit layout structure is generated according to the information in the GDS layout file, thereby automating layout and routing and improving the efficiency of passive device layout design.

[0052] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and / or computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0053] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0054] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0055] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A passive device layout structure, characterized in that: include: The core area of ​​the layout includes at least one resistor and / or at least one capacitor; The peripheral buffer area is in the form of a hollow rectangle, is arranged outside the core area of ​​the layout, and has a safety distance greater than a safety distance threshold from the core area of ​​the layout; Among them, the peripheral buffer area includes an odd number of row buffer unit groups, the row buffer unit groups located in odd rows are arranged in a forward direction, and the row buffer unit groups located in even rows are arranged in a reverse direction, so that the peripheral buffer area has power rails and ground rails, and the boundaries of the row buffer unit groups form a rectangular layout and routing boundary to be recognized by the layout and routing tools.

2. The passive device layout structure according to claim 1, characterized in that: The at least one resistor is a plurality of resistors, and the resistor is at least one of a polysilicon resistor, an N-well resistor, and a metal resistor.

3. The passive device layout structure according to claim 2, characterized in that: The layout structure of the polysilicon resistor includes: P-type implantation region; A polysilicon layer, located in the P-type implantation region; The metal layer is located in the polysilicon layer and is provided with a connecting through hole, wherein the connecting through hole connects the metal layer and the polysilicon layer.

4. The passive device layout structure according to claim 2, characterized in that: The at least one capacitor is a plurality of capacitors, and the capacitor is at least one of a finger capacitor, a plate capacitor, and a MOS tube capacitor.

5. The passive device layout structure according to claim 4, characterized in that: The layout structure of the inter-finger capacitor includes: A stacked metal layer positive electrode having positive electrode metal fingers disposed thereon; The stacked metal layer negative electrode is arranged opposite to the stacked metal layer positive electrode, and is provided with negative electrode metal fingers.

6. The passive device layout structure according to claim 5, characterized in that: A preset sub-spacing is set between the plurality of resistors, between the plurality of capacitors, or between the resistor and the capacitor, and the preset sub-spacing is greater than a sub-spacing threshold.

7. The passive device layout structure according to claim 1, characterized in that: The row buffer unit group includes a plurality of buffer units, the top of each buffer unit has a buffer power rail, and the bottom of each buffer unit has a buffer ground rail.

8. The passive device layout structure according to claim 7, characterized in that: The height of the buffer unit is equal to the digital power-ground spacing between the power rail and the ground rail in the digital standard unit, and the width of the buffer unit is equal to a positive integer multiple of the common polysilicon spacing.

9. The passive device layout structure according to claim 7, characterized in that: The buffer unit is a well contact unit and / or a filling unit.

10. The passive device layout structure according to any one of claims 1 to 9, characterized in that: The number of rows of the peripheral buffer area is the smallest positive odd number greater than or equal to 3 that makes the safety distance greater than the safety distance threshold, and the number of columns of the peripheral buffer area is the smallest positive integer greater than or equal to 3 that makes the safety distance greater than the safety distance threshold.

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