Device and system for superconducting quantum computing control, reading and feedback

Abstract

The invention relates to the technical field of quantum computing, in particular to a device and system for superconducting quantum computing control, reading and feedback, and the device comprises a clock module and one or more acquisition modules. The clock module provides a clock synchronization signal to each acquisition module to realize clock synchronization among the acquisition modules, so that delay among the acquisition modules can be reduced, and low-delay control of the quantum chip is realized; comparing a preset threshold value with a reading signal of each auxiliary quantum bit through each acquisition module to obtain a plurality of quantum measurement results; and then determining an error type of the data quantum bit according to a measurement result, determining a quantum error correction operation corresponding to the error type, outputting a driving signal according to the quantum error correction operation, and performing quantum error correction on the data quantum bit with an error. The device has high feedback control efficiency, the number of the acquisition modules can be set according to needs, and the device has high expansibility.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, and in particular to a device and system for superconducting quantum computing control, reading and feedback. Background Art

[0002] With the rapid development of superconducting quantum computing control, reading and feedback, the number of quantum bits on quantum chips has exceeded 50. The increase in the number of quantum bits has also put forward higher requirements for the measurement and control system of quantum chips. In the past, the measurement and control system of quantum chips was mainly composed of commercial arbitrary waveform generators (AWG) and data acquisition cards (DAQ-cards). As the number of bits increases, the scale of the measurement and control system also grows linearly. This brings more challenges to experiments in terms of cost, convenience and delay in real-time feedback. In addition, the existing superconducting quantum systems have errors caused by environmental noise, imperfect control mechanisms, etc. Quantum error correction is crucial to deal with these errors. Some Bose quantum bit error correction methods require the use of real-time feedback technology, which requires the control system to quickly process the readout data of the bits in real time, comprehensively analyze and immediately execute the corresponding control instructions. Summary of the invention

[0003] According to one aspect of the present disclosure, a device for superconducting quantum computing control, reading and feedback is provided, wherein the device for superconducting quantum computing control, reading and feedback comprises a clock module and one or more acquisition modules, wherein:

[0004] The clock module is used to provide a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules;

[0005] Each acquisition module is connected to the quantum chip and the clock module, and each acquisition module is used to:

[0006] Receiving a measurement signal output by the quantum chip, wherein the measurement signal includes a plurality of auxiliary quantum bit states;

[0007] Comparing the measurement signal with a preset threshold combination to obtain a plurality of quantum measurement results, wherein the preset threshold combination includes a plurality of preset thresholds, each preset threshold corresponding to each auxiliary quantum bit state;

[0008] Determining the error type of the data quantum bit in the quantum chip according to each quantum measurement result, and determining the quantum error correction operation corresponding to the error type;

[0009] A driving signal is output according to the quantum error correction operation to perform quantum error correction on the erroneous data quantum bit.

[0010] In a possible implementation manner, the using a preset threshold combination to compare with the measurement signal to obtain a plurality of quantum measurement results includes:

[0011] Comparing the measurement signals of each auxiliary quantum bit using a combination of any number of preset thresholds in the preset threshold combination to obtain a comparison result;

[0012] The comparison result is used to determine the state of each auxiliary quantum bit to obtain the quantum measurement result.

[0013] In a possible implementation, determining the error type of the data quantum bit in the quantum chip according to each quantum measurement result, and determining the quantum error correction operation corresponding to the error type, includes:

[0014] Processing the quantum measurement result using a preset coding logic to obtain a logic operation result;

[0015] The error type of the data quantum bit is determined according to the logic operation result.

[0016] In a possible implementation, the acquisition module includes a radio frequency signal output module, a radio frequency signal input module, a pulse signal output module, a pulse signal input module, a logic control module, and a timing synchronization module, wherein:

[0017] The output end of the radio frequency signal output module is connected to the input end of the quantum chip, and is used to output the driving signal;

[0018] The input end of the radio frequency signal input module is connected to the output end of the quantum chip, and is used to receive the measurement signal of the auxiliary quantum bit;

[0019] The pulse signal output module is used to generate an output pulse signal;

[0020] The pulse signal input module is used to receive an input pulse signal, wherein the input pulse signal includes the state of an auxiliary quantum bit;

[0021] The timing synchronization module is used to receive a clock synchronization signal to achieve clock synchronization with other acquisition modules;

[0022] The logic control module is connected to the RF signal output module, the RF signal input module, the pulse signal output module, the pulse signal input module, and the timing synchronization module. The logic control module is used to compare the preset threshold with the read signal of each auxiliary quantum bit to obtain multiple quantum measurement results, determine the error type of the data quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, and then generate digital driving information according to the quantum error correction operation, and the digital driving information is used to generate the driving signal.

[0023] In a possible implementation, the radio frequency signal output module includes a digital-to-analog converter, which is used to perform digital-to-analog conversion on the received digital driving information and obtain the driving signal;

[0024] The RF signal input module includes an analog-to-digital converter and a comparison circuit. The analog-to-digital converter is used to perform analog-to-digital conversion on the received measurement signal of the auxiliary quantum bit to obtain a target digital signal; the comparison circuit is used to perform a comparison operation between the target digital signal and a preset threshold to determine the state of the auxiliary quantum bit according to the comparison result.

[0025] In a possible implementation, the clock module includes an atomic clock signal input module, a clock synchronization signal output module, a trigger signal input module, and a trigger signal output module, wherein:

[0026] The clock signal input end of the atomic clock signal input module is used to receive the atomic clock signal and configure the clock signal for the clock module;

[0027] The clock synchronization signal output module is used to output the clock synchronization signal;

[0028] The trigger signal input module is connected to the host computer or the external trigger device, and is used to receive the first trigger signal sent by the host computer, or the second trigger signal sent by the external trigger device;

[0029] The trigger signal output module is used to output one or more third trigger signals.

[0030] In a possible implementation, the clock module further includes a rubidium atomic clock, the clock signal input end of the atomic clock signal input module is connected to the output end of the rubidium atomic clock, and the output end of the rubidium atomic clock is used to output the atomic clock signal.

[0031] In a possible implementation manner, sampling rates of the RF signal output module and the RF signal input module are both greater than 1 Gsps.

[0032] In a possible implementation, the acquisition module and the clock module are both implemented based on a field programmable gate array (FPGA).

[0033] According to one aspect of the present disclosure, a system for superconducting quantum computing control, reading and feedback is provided, wherein the system for superconducting quantum computing control, reading and feedback comprises one or more of the devices for superconducting quantum computing control, reading and feedback and a quantum chip.

[0034] The device for superconducting quantum computing control, reading and feedback of the disclosed embodiment includes a clock module, one or more acquisition modules, and the clock module provides a clock synchronization signal to each acquisition module to achieve clock synchronization between each acquisition module, which can reduce the delay between the acquisition modules, thereby realizing low-delay control of the quantum chip; the measurement signal output by the quantum chip is received by each acquisition module, and a preset threshold is used to compare with the measurement signal of each auxiliary quantum bit to obtain multiple quantum measurement results, and the preset threshold is for multiple auxiliary quantum bits; the error type of the data quantum bit is determined according to these measurement results, and the quantum error correction operation corresponding to the error type is determined, and then the driving signal is output according to the quantum error correction operation to perform quantum error correction on the data quantum bit with error. The device for superconducting quantum computing control, reading and feedback has high feedback control efficiency, and the number of acquisition modules can be set according to needs, and has high scalability.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0037] Figure 1 A block diagram of an apparatus for superconducting quantum computing control, reading and feedback according to an embodiment of the present disclosure is shown.

[0038] Figure 2 A schematic diagram of execution feedback logic of a collection module according to an embodiment of the present disclosure is shown.

[0039] Figure 3a , Figure 3b A feedback logic diagram of feedback error correction control according to an embodiment of the present disclosure is shown.

[0040] Figure 4A block diagram of a collection module in a device for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown.

[0041] Figure 5 A block diagram of a clock module in a device for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0042] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0043] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0044] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0045] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0046] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0047] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0048] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0049] See also Figure 1 , Figure 1 A block diagram of an apparatus for superconducting quantum computing control, reading and feedback according to an embodiment of the present disclosure is shown.

[0050] like Figure 1 As shown, the device for superconducting quantum computing control, reading and feedback includes a clock module 10 and one or more acquisition modules 20, wherein:

[0051] The clock module 10 is used to provide a clock synchronization signal to each acquisition module 20 to achieve clock synchronization between each acquisition module 20;

[0052] Each acquisition module 20 is connected to the quantum chip 30 and the clock module 10, and each acquisition module 20 is used for:

[0053] Receiving a measurement signal output by the quantum chip, wherein the measurement signal includes a plurality of auxiliary quantum bit states;

[0054] Comparing the measurement signal with a preset threshold combination to obtain a plurality of quantum measurement results, wherein the preset threshold combination includes a plurality of preset thresholds, each preset threshold corresponding to each auxiliary quantum bit state;

[0055] Determining the error type of the data quantum bit in the quantum chip according to each quantum measurement result, and determining the quantum error correction operation corresponding to the error type;

[0056] A driving signal is output according to the quantum error correction operation to perform quantum error correction on the erroneous data quantum bit.

[0057] The device for superconducting quantum computing control, reading and feedback of the disclosed embodiment includes a clock module 10, one or more acquisition modules 20, and the clock module 10 provides a clock synchronization signal to each acquisition module 20 to achieve clock synchronization between each acquisition module 20, which can reduce the delay between the acquisition modules 20, so as to realize low-delay control of the quantum chip 30 by using the acquisition module, and receive the measurement signal output by the quantum chip through each acquisition module 20, and compare it with the measurement signal of each auxiliary quantum bit by using a preset threshold to obtain multiple quantum measurement results, wherein the preset threshold is for multiple auxiliary quantum bits; according to these measurement results, the error type of the data quantum bit is determined, and the quantum error correction operation corresponding to the error type is determined, and then the driving signal is output according to the quantum error correction operation to perform quantum error correction on the data quantum bit with error. The device for superconducting quantum computing control, reading and feedback has high feedback control efficiency, and the number of acquisition modules can be set according to needs, and has high scalability.

[0058] The disclosed embodiments do not limit the type of quantum chip 30, the specific implementation of the clock module 10, and one or more acquisition modules 20. Those skilled in the art can set them according to actual conditions and needs. The quantum chip 30, the clock module 10, and one or more acquisition modules 20 can all be implemented through hardware circuits. The quantum chip is the core structure for realizing quantum computing. A large number of quantum bit structures are arranged on the quantum chip. Each quantum bit is composed of a specific hardware circuit arranged on the quantum chip. Each quantum bit has at least two distinguishable logical states. Based on the quantum algorithm, the logical state of the quantum bit can undergo controllable changes, thereby realizing quantum computing.

[0059] The device for superconducting quantum computing control, reading and feedback in the embodiment of the present disclosure may also include a device body, such as a square chassis, and each module is arranged in the device body. Of course, the shape of the device body may also be other, which is not limited to the embodiment of the present disclosure, and those skilled in the art may set it according to actual conditions and needs.

[0060] Exemplarily, the device for superconducting quantum computing control, reading and feedback of the disclosed embodiment can be connected to a quantum system, the core of which is a quantum chip 30 located in a refrigerator, which can realize quantum computing. The entire system includes external devices at room temperature and low temperature (below 4K). To control the quantum chip 30, a radio frequency electromagnetic drive signal needs to be provided. Exemplarily, an acquisition module 20 can emit a radio frequency signal of about 100 megahertz and some trigger signals (for example, which can be used to control other room temperature devices), and after a series of microwave devices, a channel of the quantum chip 30 can be controlled, wherein multiple acquisition cards can be used in combination to control the entire quantum chip 30.

[0061] It is worth mentioning that in quantum computing, for the sake of clarity, we can use the three terms logical bit, physical bit (or data qubit) and auxiliary bit. Physical bits are the bits that actually exist on the quantum chip and are subject to interference from various noises. Generally, qubits when discussing hardware and physical implementation refer to physical bits (in the context of this article). Logical bits are generally formed by encoding multiple physical bits. They have a certain redundancy for various errors. When an error occurs (here, an error occurs in the physical bit that encodes the logical bit), it will change from a logical state to a corresponding error state, and the stored information will not be lost. Logical bits are the core part that is actually used to perform quantum computing.

[0062] The purpose of quantum error correction in the disclosed embodiments is to protect logical bits from being interfered by environmental noise and thus causing errors.

[0063] Auxiliary bits are physical bits specifically used for error detection and correction. They do not carry actual computational information, but through interaction with logical bits, they can detect and identify errors on the physical bits that make up the logical bits, and then guide us to correct the errors on the logical bits. By measuring the auxiliary bits, we can know which physical bit that makes up the logical bit has what kind of error, and thus perform corresponding feedback error correction drive.

[0064] The embodiment of the present disclosure does not limit the specific implementation method of each step executed by the acquisition module 20, and those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs.

[0065] The embodiments of the present disclosure do not limit the preset thresholds in the preset threshold combination and the specific number and state of the auxiliary quantum bit states in the measurement signal. Those skilled in the art can set them according to actual conditions and needs, wherein the preset thresholds in the preset threshold combination can be obtained based on logical quantum bits, and the logical quantum bits can be obtained, for example, based on the calculation results of the quantum chip (such as the pre-calculation results), or based on an important intermediate parameter or other type of parameter maintained as needed, which is not limited by the embodiments of the present disclosure. In this case, the embodiments of the present disclosure can use the auxiliary quantum bit state to realize the error detection and error correction of the data quantum bit to maintain the quantum bit state of the data quantum bit, so that the quantum chip can normally complete the quantum computing operation.

[0066] Exemplarily, the using a preset threshold combination to compare with the measurement signal to obtain a plurality of quantum measurement results may include:

[0067] Comparing the measurement signals of each auxiliary quantum bit using a combination of any number of preset thresholds in the preset threshold combination to obtain a comparison result;

[0068] The comparison result is used to determine the state of each auxiliary quantum bit to obtain the quantum measurement result.

[0069] The embodiments of the present disclosure do not limit the specific implementation method of comparing the measurement signals of each auxiliary quantum bit using a combination of any number of preset thresholds in the preset threshold combination, and do not limit the method of setting the preset threshold value. Those skilled in the art can set it according to actual conditions and needs. For example, when the auxiliary quantum bit is at 1, the signal strength is large, and when it is at 0, the signal strength is small. In this case, the embodiments of the present disclosure can set the preset threshold at the signal strength corresponding to the intermediate value between 0 and 1, so as to automatically judge the state of the bit and obtain a comparison result.

[0070] Exemplarily, the measurement result may represent the state of the auxiliary quantum bit. After obtaining the measurement result, the error type of the data quantum bit in the quantum chip may be determined according to each quantum measurement result, and the quantum error correction operation corresponding to the error type may be determined, for example, including:

[0071] Determining the error type of the data quantum bit in the quantum chip according to each quantum measurement result, and determining the quantum error correction operation corresponding to the error type, including:

[0072] Processing the quantum measurement result using a preset coding logic to obtain a logic operation result;

[0073] The error type of the data quantum bit is determined according to the logic operation result.

[0074] Specifically, this may include:

[0075] Using a combination of qubits in a preset quantum signal to perform quantum logic gate processing on the state (measurement result) of each auxiliary qubit, the combination of qubits comprising a combination of any number of preset qubits;

[0076] Determining the quantum bit state of each auxiliary quantum bit to obtain the quantum measurement result;

[0077] Processing the quantum measurement result using a preset coding logic to obtain a logic operation result;

[0078] The error type of the data quantum bit is determined based on the result of the logical operation.

[0079] The embodiments of the present disclosure do not limit the type and implementation of the quantum logic gate. Those skilled in the art may set it according to actual conditions and needs. For example, the quantum logic gate may include at least one of a Pauli-X gate, an Hadamard gate, a Pauli-Y gate, a Pauli-Z gate, a swap gate, a phase shift gate, and a Toffoli gate.

[0080] The embodiments of the present disclosure do not limit the specific combination of quantum bit combinations in the preset quantum signal. Those skilled in the art can set it according to actual conditions and needs. For example, if the preset quantum signal includes M preset quantum bits, each quantum bit combination may include any s preset quantum bits, where 0<s<M and s and M are both integers.

[0081] The following is an exemplary introduction using an example in which a preset quantum signal includes three preset quantum bits and a measurement signal includes two auxiliary quantum bit states.

[0082] See also Figure 2 , Figure 2 A schematic diagram of execution feedback logic of a collection module according to an embodiment of the present disclosure is shown.

[0083] For example, Figure 2 As shown, the embodiment of the present disclosure may first prepare a preset quantum signal α|000>+β|111>. Of course, the preset quantum signal α|000>+β|111> may also be prepared in advance, which is not limited in the embodiment of the present disclosure.

[0084] Assuming that the logical quantum bit is α|0>+β|1>, and the preset quantum signal includes three preset quantum bits, the embodiment of the present disclosure can use the logical quantum bit α|0>+β|1> to prepare the preset quantum signal α|000>+β|111>. Of course, the embodiment of the present disclosure does not limit the specific implementation method of using the logical quantum bit to prepare the preset quantum signal. Those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs. For example, the embodiment of the present disclosure can apply a drive to a physical bit α|0>+β|1> to make it become a logical quantum bit α|0>+β|1>, and then apply CNOT gates to the second and third quantum bits to make them entangled with each other, thereby realizing the α|000>+β|111> state. Among them, the working principle of the CNOT gate is: assuming that the first quantum bit is used to perform a CNOT gate on the second quantum bit, when the first quantum bit is in the 0 state, the quantum state remains unchanged, and when the first quantum bit is in the 1 state, the quantum state of the second quantum bit is flipped, for example: CNOT|00>=|00>; CNOT|10>=|11>; CNOT(α|00>+β|11>=α|00>+β|10>; CNOT(α|0>+β|1>)|0>=α|00>+β|11>.

[0085] Then, the embodiment of the present disclosure can use the quantum bit combination in the preset quantum signal to perform quantum logic gate processing on each auxiliary quantum bit state corresponding to each measurement result, and the quantum bit combination includes a combination of any number of preset quantum bits, for example, using the first two quantum bits of the preset quantum signal α|000>+β|111> Perform CNOT gates on the first auxiliary bit in turn, and use the last two quantum bits of the preset quantum signal α|000>+β|111> The second auxiliary bits are sequentially subjected to CNOT gates to implement quantum logic gate processing of the states of the auxiliary quantum bits using the quantum bit combinations in the preset quantum signal.

[0086] For example, Figure 2 As shown, the disclosed embodiment can determine the quantum bit state of each auxiliary quantum bit according to the measurement result to obtain the quantum measurement result, determine the error type of the quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, output a driving signal according to the quantum error correction operation, and perform quantum error correction on the quantum bit in which the error occurs in the data quantum bit.

[0087] Of course, the embodiments of the present disclosure do not limit the specific implementation method of determining the quantum bit state of each auxiliary quantum bit. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs. For example, they can refer to the above introduction to use a comparison circuit to compare the state of each auxiliary quantum bit with a preset threshold (corresponding to a voltage signal). In this way, the quantum bit state of each auxiliary quantum bit can be determined, and the quantum bit state of each auxiliary quantum bit can be obtained by combining the quantum bit state of each auxiliary quantum bit. The embodiments of the present disclosure do not limit the specific implementation method of determining the error type of the quantum bit according to each quantum operation result, and determining the quantum error correction operation corresponding to the error type. For example, there can be a mapping relationship between the quantum operation result, the error type of the quantum bit and the quantum error correction operation. After the quantum operation result is determined, those skilled in the art can determine the quantum bit error type and quantum error correction operation corresponding to the quantum operation result according to the mapping relationship.

[0088] Exemplarily, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |00>, it means that no error occurs in the data quantum bit and no operation is performed;

[0089] Exemplarily, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |10>, indicating that an X error occurs in the first qubit in the data qubit, and an X gate is applied to the first qubit in the data qubit;

[0090] Exemplarily, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |01>, indicating that an X error occurs in the second qubit in the data qubit, and an X gate is applied to the first qubit in the data qubit;

[0091] Exemplarily, assuming that the first auxiliary bit and the second auxiliary bit are measured to obtain a measurement result |11>, indicating that an X error occurs in the third qubit in the data qubit, and an X gate is applied to the first qubit in the data qubit.

[0092] The embodiments of the present disclosure are described by taking an X error and applying an X gate as an example of a quantum error correction operation corresponding to the X error, but this should not be regarded as limiting the embodiments of the present disclosure. In other embodiments, other errors may also occur in each bit of the data quantum bit. For different error types, those skilled in the art may set corresponding quantum error correction operations (e.g., applying corresponding quantum logic gates) according to actual conditions and needs.

[0093] In the embodiment of the present disclosure, the quantum error correction operation can be implemented by the driving signal, that is, applying an X gate or other quantum logic gate to the corresponding quantum bit can generate a driving signal for the corresponding quantum bit to perform a quantum error correction operation on the corresponding quantum bit. Of course, those skilled in the art can use relevant technologies to generate corresponding driving signals to implement X gates or other quantum logic gates according to actual conditions and needs, and the embodiment of the present disclosure is not limited to this.

[0094] In the disclosed embodiment, the goal of error correction is to maintain the prepared quantum state α|000>+β|111>. In some scenarios, this quantum state may be obtained as a result of a previous operation, so it is necessary to protect it from being affected by errors as much as possible (it can be understood that in actual quantum computing, these three bits as a whole encode a logical bit α|0>+β|1>).

[0095] The error type of the qubit in the embodiment of the present disclosure may be caused by the interaction with the environment, and the error may refer to an X error occurring in a qubit in α|000>+β|111>. In the above example, the auxiliary bit in the embodiment of the present disclosure is used to measure whether X error occurs in these qubits.

[0096] When it is confirmed that an error has occurred, the embodiments of the present disclosure can determine the corresponding quantum error correction operation according to the error type to restore the qubit with an error in the data qubit to its original quantum state. For example, in the above example, if it is determined that an X error has occurred in a qubit in α|000>+β|111>, an X gate is applied to the qubit to restore the qubit with an error to its original quantum state.

[0097] The measurement method described above has the same result for any quantum state (α|> and β|>), so the quantum state (α|> and β|>) can be protected unchanged, that is, the logical bit in the preset quantum signal of the embodiment of the present disclosure can be protected unchanged. In addition, the error correction method of the embodiment of the present disclosure is summarized, and the total time of the error correction process is very short, and it can be repeated all the time, so from the overall point of view, this system can overcome the single-bit X error, thereby improving the life of the quantum bit.

[0098] Of course, the embodiments of the present disclosure are not limited to performing error correction once, and for the entire process of quantum computing, a continuous feedback error correction control method can be adopted.

[0099] See also Figure 3a , Figure 3b , Figure 3a , Figure 3b A feedback logic diagram of feedback error correction control according to an embodiment of the present disclosure is shown.

[0100] Among them, the feedback logic diagram refers to an abstract description of the logic of a quantum feedback experiment, which consists of feedback nodes and feedback edges. It mainly describes the read-feedback operation of the quantum chip, where the feedback node represents the current state of the quantum system, and the feedback edge represents the conditions for the system to jump between different feedback nodes. Feedback nodes are connected by feedback edges, which are directed edges. The feedback node can contain information such as the quantum bit drive and measurement instructions to be used in the current stage. The system chooses which feedback edge to pass through by comprehensively judging the state of the quantum system at the end of the feedback node. For example, the corresponding feedback edge can be selected according to the error type of the quantum bit determined after measuring the bit state or the measurement result to achieve a jump to the next feedback node. This abstract structure can generate arbitrary quantum feedback logic, including but not limited to multi-level feedback, cyclic feedback, etc.

[0101] For example, Figure 3a , Figure 3b The two feedback logic diagrams shown are Figure 3a The feedback logic diagram shown is a loop feedback. Figure 3b The feedback logic diagram shown is a multi-level feedback. Of course, Figure 3a , Figure 3b The two feedback logics shown are exemplary and should not be considered as limitations on the embodiments of the present disclosure. In other embodiments, multi-level feedback and loop feedback may include other feedback nodes and feedback edges.

[0102] For example, Figure 3aFor example, if the error type of the quantum bit is determined to be error type 1 at the node measuring bit state 1, the feedback edge of error type 1 is selected to execute the feedback node corresponding to feedback drive 1. Taking the above example, if error type 1 is that the first quantum bit in the preset quantum signal has an X error, the feedback drive 1 operation may include "applying an X gate to the first quantum bit in the preset quantum signal."

[0103] For example, Figure 3b For example, if the result of the quantum bit is determined to be result 1 at the node measuring the bit state, the feedback edge of result 1 is selected to execute feedback drive & the feedback node corresponding to measurement 1. Taking the above example, if result 1 is "measure the first auxiliary bit and the second auxiliary bit to obtain the measurement result |10>", the feedback drive 1 operation may include "applying an X gate to the first quantum bit in the preset quantum signal", and then determining the result of the quantum bit again. If it is result 3, the corresponding feedback edge is selected.

[0104] The following is an exemplary introduction to the preferred implementation of the acquisition module 20 and the clock module 10.

[0105] See also Figure 4 , Figure 4 A block diagram of the acquisition module 20 in the apparatus for superconducting quantum computing control, reading and feedback according to an embodiment of the present disclosure is shown.

[0106] In a possible implementation, Figure 4 As shown, the acquisition module 20 may include a radio frequency signal output module 220, a radio frequency signal input module 210, a pulse signal output module 230, a pulse signal input module 240, a logic control module 260, and a timing synchronization module 250, wherein:

[0107] The output end of the RF signal output module 220 is connected to the input end of the quantum chip 30 for outputting the driving signal;

[0108] The input end of the radio frequency signal input module 210 is connected to the output end of the quantum chip 30, and is used to receive the read signal (i.e., measurement signal) of the auxiliary quantum bit;

[0109] The pulse signal output module 230 is used to generate an output pulse signal;

[0110] The pulse signal input module 240 is used to receive an input pulse signal, wherein the input pulse signal includes the state of an auxiliary quantum bit;

[0111] The timing synchronization module 250 is used to receive a clock synchronization signal to achieve clock synchronization with other acquisition modules 20;

[0112] The logic control module 260 is connected to the RF signal output module 220, the RF signal input module 210, the pulse signal output module 230, the pulse signal input module 240, and the timing synchronization module 250. The logic control module 260 is used to compare the preset threshold with the read signal of each auxiliary quantum bit to obtain multiple quantum measurement results, determine the error type of the data quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, and then generate digital driving information according to the quantum error correction operation, and the digital driving information is used to generate the driving signal.

[0113] The embodiments of the present disclosure do not limit the specific implementation methods of the RF signal output module 220, the RF signal input module 210, the pulse signal output module 230, the pulse signal input module 240, the logic control module 260, and the timing synchronization module 250. Those skilled in the art can set them according to actual conditions and needs. By way of example, the RF signal output module 220, the RF signal input module 210, the pulse signal output module 230, and the pulse signal input module 240 all include hardware interfaces. The embodiments of the present disclosure do not limit the types of the hardware interfaces and the protocols used. Those skilled in the art can set them according to actual conditions and needs.

[0114] In a possible implementation, the RF signal output module 220 may include a digital-to-analog converter (DAC) for performing digital-to-analog conversion on the received digital driving information and obtaining the driving signal. The embodiment of the present disclosure does not limit the specific implementation method of the digital-to-analog converter, nor does it limit the specific parameters (such as accuracy) of the digital-to-analog converter. Those skilled in the art may adopt a suitable digital-to-analog converter according to actual conditions and needs.

[0115] Exemplarily, the RF signal output module 220 can output signals at a sampling rate of at least 1 Gsps, which can be used to drive the quantum chip in the quantum system, where Gsps (GigaSamples per Second) is the unit of sampling rate, indicating that the number of samples collected per second reaches billions.

[0116] In a possible implementation, the RF signal input module 210 may include an analog-to-digital converter (ADC) and a comparison circuit. The analog-to-digital converter is used to perform analog-to-digital conversion on the measurement signal of the auxiliary quantum bit received from the quantum chip to obtain a target digital signal; the comparison circuit is used to perform a comparison operation between the target digital signal and a preset threshold value to determine the state of the quantum bit according to the comparison result. The embodiment of the present disclosure does not limit the specific implementation method of the analog-to-digital converter and the comparison circuit, and does not limit the specific parameters (such as accuracy) of the analog-to-digital converter. Those skilled in the art may adopt a suitable analog-to-digital converter according to actual conditions and needs. As an example, the comparison circuit may include a comparator and related peripheral circuits. Those skilled in the art may refer to relevant technical implementations for their specific implementation methods.

[0117] Exemplarily, the RF signal input module 210 can collect RF input signals at a sampling rate of at least 1Gsps, which can be used to obtain information output by the quantum system. The RF signal input module 210 has a demodulation and analysis function, and can analyze the state of the quantum bit from the collected data. The ADC chip used by the RF signal input module 210 can convert the analog signal (the received analog auxiliary quantum bit state) into a digital signal (target digital signal). The RF signal input module 210 processes the obtained digital signal and compares it with the preset signal to determine the state of the quantum bit.

[0118] Exemplarily, the pulse signal output module 230 can output a pulse signal (such as a 0 / 2V signal), and the pulse signal input module 240 can input a pulse signal (such as a 0 / 2V signal), where 0V represents bit 0 and 2V represents bit 1. Of course, the output can also be performed according to other preset logics, which is not limited in the embodiments of the present disclosure. The logic control module 260 and the timing control module can be directly programmed on the FPGA. They both have dedicated logic circuits. Both the RF signal input and output and the pulse signal input and output have dedicated conversion chips.

[0119] Exemplarily, the pulse signal output module 230 can output a pulse signal of 0V or 2V. The pulse signal output module 230 outputs according to the logic preset by the experimenter (exemplarily, one acquisition module 20 can include multiple pulse signal output modules 230). This part of the logic can be output in time according to a preset instruction sequence (for example, 0V*20ns, 2V*100ns, 0V*40ns), or it can be the output of the logic control module 260. The pulse signal can be used to control other devices or send signals to other acquisition modules 20. When used to control other devices, it is mainly used as a trigger signal, similar to a switch. When sending related signals (such as bit status) to other acquisition modules 20, 0V can be used to represent bit 0, 2V can represent bit 1, or it can be output according to other preset logic.

[0120] The apparatus for superconducting quantum computing control, reading and feedback in the embodiment of the present disclosure may include multiple acquisition modules 20, wherein the auxiliary quantum bit state included in the measurement signal includes the measurement signal of the auxiliary quantum bit state directly received by the radio frequency signal input module 210 of the current acquisition module, and may also include the measurement signal of the auxiliary quantum bit state transmitted by other acquisition modules 20. For example, after receiving the measurement signal of the auxiliary quantum bit state through the radio frequency signal input module 210, the other acquisition modules 20 may send the measurement signal of the auxiliary quantum bit state to the current acquisition module 20 through the pulse signal output module 230, so that the current acquisition module 20 performs a quantum error correction operation according to the measurement signal of the auxiliary quantum bit state received by its own radio frequency signal input module 210 and the measurement signal of the auxiliary quantum bit state received by the pulse signal output module 230.

[0121] In a possible implementation, the logic control module 260 is used to:

[0122] The quantum bit state is converted into a pulse signal and outputted through the pulse signal output module 230 , for example, converted into a 0 / 2V signal as a pulse signal output.

[0123] Exemplarily, the pulse signal input module 240 is capable of receiving a pulse signal. Specifically, it can receive a signal output by a pulse signal output module 230 in other acquisition modules 20 and send the result to the logic control module 260. Other acquisition modules 20 can send the measurement signal of the quantum bit obtained by the RF signal input module 210 to the pulse signal input module 240 of this acquisition module 20 through the pulse signal output module 230, thereby transmitting the bit information of the quantum bit between the acquisition modules 20.

[0124] The embodiments of the present disclosure do not limit the specific implementation of the logic control module 260. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs. For example, the logic control module 260 may include a processing component. For example, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device. The processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0125] Preferably, the logic control module 260 of the embodiment of the present disclosure is implemented using FPGA, so that the processing capability of the quantum chip 30 with an increased number of quantum bits can be improved, and the scale of the measurement and control system can be increased. The technical solution of the embodiment of the present disclosure is applied to the FPGA-based system, which can solve the problems of high cost and cumbersome control of traditional measurement and control systems, and can achieve quantum real-time feedback at the level of hundreds of nanoseconds. In addition, the embodiment of the present disclosure can solve the problem of multi-chassis multi-nested real-time feedback.

[0126] In the disclosed embodiment, the logic control module 260 processes the quantum measurement result using a preset quantum signal to obtain a quantum operation result; the error type of the data quantum bit is determined according to the quantum operation result, and the quantum error correction operation corresponding to the error type is determined. The specific implementation method of generating digital drive information according to the quantum error correction operation is not limited, and those skilled in the art can set it according to actual conditions and needs.

[0127] Exemplarily, the digital driving information may correspond to a quantum error correction operation. For example, the digital driving information may be a driving parameter corresponding to a quantum logic gate. If the error type of the quantum bit is determined, the corresponding quantum logic gate may be determined according to the error type, thereby generating corresponding digital driving information to perform the quantum logic gate operation on the corresponding quantum bit. Of course, the specific implementation method of the logic control module 260 generating the corresponding digital driving information according to a specific quantum error correction operation is not limited in the embodiment of the present disclosure, and those skilled in the art may refer to the relevant technical implementation according to the actual situation and needs.

[0128] Exemplarily, the logic control module 260 can use the auxiliary quantum bit state received by the RF signal input module 210 and the pulse signal (including the auxiliary quantum bit state) received by the pulse signal input module 240 to determine the current state of the quantum system (the quantum bit state) and the next required operation, thereby controlling the output waveform of the driving signal of the RF signal output module 220 to control the quantum system, and send the result (generally transmitting the quantum bit information obtained by the RF signal input module 210) to other acquisition modules 20 and / or other devices through the pulse signal output module 230.

[0129] Exemplarily, the RF signal input module 210 can analyze the collected waveform (operation result) to obtain information about the auxiliary quantum bit state of the current acquisition module 20, and the pulse signal input module 240 can obtain information about the quantum bits controlled by other acquisition modules 20 (for example, there is another acquisition module 20, which obtains the measurement signal of the quantum bit through its own RF signal input module 210, analyzes and obtains the 01 state of the quantum bit, and then transmits it to the pulse signal input module 240 of the current acquisition module 20 through the pulse signal output module 230). The logic control module 260 can integrate the signals of the RF signal input module 210 and the pulse signal input module 240, and obtain the quantum bit state according to the preset logical operation. Of course, the embodiment of the present disclosure does not limit the specific type of the preset logical operation, and those skilled in the art can set it according to actual conditions and needs.

[0130] Exemplarily, the quantum bit state can be transmitted to other acquisition modules 20 by the pulse signal output module 230, so as to obtain the state of the entire quantum chip 30 and perform the next feedback operation.

[0131] Of course, the above introduction to the functions of the logic control module 260 is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure. Those skilled in the art can use the logic control module 260 to control other modules according to actual conditions and needs.

[0132] The embodiments of the present disclosure do not limit the specific implementation of the timing synchronization module 250. Those skilled in the art can set it according to actual conditions and needs. For example, the timing synchronization module 250 can cooperate with the subsequent control and trigger system to fine-tune the timing of the system. In order to improve the measurement and control accuracy of the quantum chip 30, the embodiments of the present disclosure can align the measurement and control signals of the embodiments of the present disclosure at the level of hundreds of ps. Due to factors such as line length, the signals emitted from the room temperature equipment are not naturally aligned when they reach the superconducting chip. Therefore, the embodiments of the present disclosure need to fine-tune the time when different acquisition modules 20 start running. The timing synchronization module 250 can adjust the trigger time of different acquisition modules 20 at the level of hundreds of ps, and ensure that they remain synchronized throughout the experiment, and the mutual delay remains unchanged, thereby improving the time accuracy of the experiment.

[0133] See also Figure 5 , Figure 5 A block diagram of a clock module 10 in a device for superconducting quantum computing control, reading, and feedback according to an embodiment of the present disclosure is shown.

[0134] In a possible implementation, Figure 5 As shown, the clock module 10 may include an atomic clock signal input module 110, a clock synchronization signal output module 120, a trigger signal input module 130, and a trigger signal output module 140, wherein:

[0135] The clock signal input terminal of the atomic clock signal input module 110 is used to receive the atomic clock signal and configure the clock signal for the clock module 10;

[0136] The clock synchronization signal output module 120 is used to output the clock synchronization signal to achieve synchronization and calibration of different acquisition modules 20. Exemplarily, the clock module 10 may also include a synchronization signal generating circuit. When the atomic clock signal input module 110 receives the atomic seed signal (such as a 10 MHz signal), the synchronization signal generating circuit may generate a plurality of mutually synchronized clock synchronization signals (such as a 125 MHz signal) according to the atomic clock signal, and output them from different clock synchronization signal output modules 120 (clock synchronization signal output ports) to each acquisition module 20. Since each clock synchronization signal is synchronized, synchronization and calibration of different acquisition modules 20 may be achieved.

[0137] The trigger signal input module 130 is connected to the host computer or the external trigger device, and is used to receive the first trigger signal sent by the host computer, or the second trigger signal sent by the external trigger device. In this way, the trigger signal input module 130 of the embodiment of the present disclosure can select internal trigger or external trigger function. Internal trigger means that the host computer program controls the triggering of the clock module 10 through the first trigger signal; external trigger means that the clock module 10 waits for the second trigger signal of the trigger input port, thereby triggering other devices;

[0138] The trigger signal output module 140 is used to output one or more third trigger signals. In this way, through the trigger signal output module 140, the embodiment of the present disclosure can simultaneously trigger multiple clock modules 10 or acquisition modules 20. The clock module 10 triggering the clock module 10 can achieve multi-level triggering. For example, if the current clock module 10 receives the second trigger signal from other clock modules 10 or the first trigger signal sent by the host computer, it can immediately generate and output one or more third trigger signals to trigger the acquisition module 20 and other connected clock modules 10. Of course, the trigger delay (the time between generating and outputting one or more third trigger signals after receiving the first trigger signal and the second start signal) can be adjusted (that is, it can be set to wait for a period of time (ns level) after receiving the trigger signal before triggering the next level). At the same time, which acquisition modules 20 and clock modules 10 are triggered can also be set, and this is not limited by the embodiment of the present disclosure.

[0139] The embodiments of the present disclosure do not limit the specific implementation methods of the atomic clock signal input module 110, the clock synchronization signal output module 120, the trigger signal input module 130, and the trigger signal output module 140, and those skilled in the art may configure them according to actual conditions and needs.

[0140] In a possible implementation, Figure 5 As shown, the clock module 10 may further include a rubidium atomic clock 100, the clock signal input end of the atomic clock signal input module 110 is connected to the output end of the rubidium atomic clock 100, and the output end of the rubidium atomic clock 100 is used to output the atomic clock signal.

[0141] The embodiment of the present disclosure can provide an accurate clock signal (the atomic clock signal) by setting the rubidium atomic clock 100, thereby improving the clock output accuracy of the clock module 10.

[0142] In a possible implementation manner, the sampling rates of the RF signal output module 220 and the RF signal input module 210 are both greater than 1 Gsps.

[0143] The apparatus for superconducting quantum computing control, reading and feedback of the embodiment of the present disclosure may also include other modules, which are not limited by the embodiment of the present disclosure, and those skilled in the art may set them according to actual conditions and needs. For example, the apparatus for superconducting quantum computing control, reading and feedback may also include a storage module for storing data, wherein, in one example, the storage module may include a computer-readable storage medium, which may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, - but not limited to - an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), programmable read-only memory (PROM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encoding device, such as punch cards or raised structures in grooves with instructions stored thereon, and any suitable combination of the above. Computer-readable storage media as used herein are not to be interpreted as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0144] In a possible implementation, the acquisition module 20 and the clock module 10 are both implemented based on a field programmable gate array FPGA.

[0145] The device for superconducting quantum computing control, reading and feedback of the disclosed embodiment solves the deficiencies in the prior art and provides an expandable multi-bit multi-level feedback system to solve the problems in the actual manipulation of quantum bits. The device for superconducting quantum computing control, reading and feedback of the disclosed embodiment uses a customized system based on FPGA, which can solve the problems of high cost and cumbersome control of traditional measurement and control systems, and can achieve real-time quantum feedback at the level of hundreds of nanoseconds. Compared with other systems using FPGA, the device for superconducting quantum computing control, reading and feedback of the disclosed embodiment solves the problem of multi-chassis multi-nested real-time feedback.

[0146] According to one aspect of the present disclosure, a system for superconducting quantum computing control, reading and feedback is provided, wherein the system for superconducting quantum computing control, reading and feedback comprises one or more of the devices for superconducting quantum computing control, reading and feedback and a quantum chip 30.

[0147] Compared with the prior art, the device for superconducting quantum computing control, reading and feedback in the disclosed embodiment has the following beneficial results:

[0148] 1. The disclosed embodiment realizes real-time feedback of multiple cards across chassis, has good scalability, and can be used to implement large-scale quantum bit feedback experiments.

[0149] 2. The disclosed embodiments implement a customized integrated system based on FPGA, which has significant improvements in cost, convenience and real-time feedback delay.

[0150] 3. The disclosed embodiment implements a feedback logic diagram method for quantum feedback experiments and implements a corresponding program. Compared with existing feedback control methods such as binary trees, it has higher control efficiency, more applicable scenarios and greater flexibility, and is easier for experimenters to understand.

[0151] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device for superconducting quantum computing control, reading and feedback, characterized in that: The device for superconducting quantum computing control, reading and feedback includes a clock module and one or more acquisition modules, wherein: The clock module is used to provide a clock synchronization signal to each acquisition module to achieve clock synchronization between the acquisition modules; Each acquisition module is connected to the quantum chip and the clock module, and each acquisition module is used to: Receiving a measurement signal output by the quantum chip, wherein the measurement signal includes a plurality of auxiliary quantum bit states; Comparing the measurement signal with a preset threshold combination to obtain a plurality of quantum measurement results, wherein the preset threshold combination includes a plurality of preset thresholds, each preset threshold corresponding to each auxiliary quantum bit state; Determining the error type of the data quantum bit in the quantum chip according to each quantum measurement result, and determining the quantum error correction operation corresponding to the error type; A driving signal is output according to the quantum error correction operation to perform quantum error correction on erroneous data quantum bits.

2. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The method of comparing the preset threshold combination with the measurement signal to obtain a plurality of quantum measurement results includes: Comparing the measurement signals of each auxiliary quantum bit using a combination of any number of preset thresholds in the preset threshold combination to obtain a comparison result; The comparison result is used to determine the state of each auxiliary quantum bit to obtain the quantum measurement result.

3. The device for superconducting quantum computing control, reading and feedback according to claim 2, characterized in that: Determining the error type of the data quantum bit in the quantum chip according to each quantum measurement result, and determining the quantum error correction operation corresponding to the error type, including: Processing the quantum measurement result using a preset coding logic to obtain a logic operation result; The error type of the data quantum bit is determined according to the logic operation result.

4. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The acquisition module includes a radio frequency signal output module, a radio frequency signal input module, a pulse signal output module, a pulse signal input module, a logic control module, and a timing synchronization module, wherein: The output end of the radio frequency signal output module is connected to the input end of the quantum chip, and is used to output the driving signal; The input end of the radio frequency signal input module is connected to the output end of the quantum chip, and is used to receive the measurement signal of the auxiliary quantum bit; The pulse signal output module is used to generate an output pulse signal; The pulse signal input module is used to receive an input pulse signal, wherein the input pulse signal includes the state of an auxiliary quantum bit; The timing synchronization module is used to receive a clock synchronization signal to achieve clock synchronization with other acquisition modules; The logic control module is connected to the RF signal output module, the RF signal input module, the pulse signal output module, the pulse signal input module, and the timing synchronization module. The logic control module is used to compare the preset threshold with the read signal of each auxiliary quantum bit to obtain multiple quantum measurement results, determine the error type of the data quantum bit according to each quantum measurement result, and determine the quantum error correction operation corresponding to the error type, and then generate digital driving information according to the quantum error correction operation, and the digital driving information is used to generate the driving signal.

5. The device for superconducting quantum computing control, reading and feedback according to claim 4, characterized in that: The RF signal output module includes a digital-to-analog converter, which is used to perform digital-to-analog conversion on the received digital driving information and obtain the driving signal; The RF signal input module includes an analog-to-digital converter and a comparison circuit. The analog-to-digital converter is used to perform analog-to-digital conversion on the received measurement signal of the auxiliary quantum bit to obtain a target digital signal; the comparison circuit is used to perform a comparison operation between the target digital signal and a preset threshold to determine the state of the auxiliary quantum bit according to the comparison result.

6. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The clock module includes an atomic clock signal input module, a clock synchronization signal output module, a trigger signal input module, and a trigger signal output module, wherein: The clock signal input end of the atomic clock signal input module is used to receive the atomic clock signal and configure the clock signal for the clock module; The clock synchronization signal output module is used to output the clock synchronization signal; The trigger signal input module is connected to the host computer or the external trigger device, and is used to receive the first trigger signal sent by the host computer, or the second trigger signal sent by the external trigger device; The trigger signal output module is used to output one or more third trigger signals.

7. The device for superconducting quantum computing control, reading and feedback according to claim 6, characterized in that: The clock module also includes a rubidium atomic clock. The clock signal input end of the atomic clock signal input module is connected to the output end of the rubidium atomic clock. The output end of the rubidium atomic clock is used to output the atomic clock signal.

8. The device for superconducting quantum computing control, reading and feedback according to claim 4, characterized in that: The sampling rates of the radio frequency signal output module and the radio frequency signal input module are both greater than 1 Gsps.

9. The device for superconducting quantum computing control, reading and feedback according to claim 1, characterized in that: The acquisition module and the clock module are both implemented based on a field programmable gate array (FPGA).

10. A system for superconducting quantum computing control, reading and feedback, characterized in that: The system for superconducting quantum computing control, reading and feedback comprises one or more devices for superconducting quantum computing control, reading and feedback and quantum chips as described in any one of claims 1 to 9.

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