Quantum State Amplitude Encoding Method, Apparatus, Device, and Medium

Abstract

The present invention discloses a quantum state amplitude encoding method, apparatus, device and medium. The method includes normalizing the complex vector to be encoded; calculating the modulus length of each element in the normalized complex vector to be encoded to obtain a modulus length vector; constructing a quantum circuit including a parametric quantum gate according to the modulus length vector, and calculating the parameters of the parametric quantum gate by using a real vector amplitude encoding algorithm to obtain a first quantum circuit, so as to output a first quantum state evolved by the first quantum circuit; calculating the argument of each element in the normalized complex vector to be encoded to obtain an argument vector; constructing a second quantum circuit according to the argument vector; the second quantum circuit includes 2 n operation units connected in sequence, and the operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; executing the first quantum circuit and the second quantum circuit to output a target quantum state; the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum computing, and particularly to a quantum state amplitude encoding method, apparatus, device, and medium. Background Art

[0002] Quantum algorithms, as advanced computing paradigms based on the principles of quantum mechanics, use qubits (quantum bits) as the basic units for information encoding, and ingeniously utilize unique properties of quantum mechanics such as quantum superposition and quantum entanglement to achieve efficient processing of computational tasks. In specific computational scenarios, quantum algorithms exhibit significant performance advantages compared to traditional algorithms. For example, when dealing with the problem of factoring large integers, the Shor algorithm provides exponential acceleration compared to classical algorithms; while when performing the search task of an unordered database, the Grover algorithm achieves quadratic efficiency improvement compared to classical search algorithms. These breakthroughs not only demonstrate the potential of quantum algorithms in solving complex problems, but also provide a solid theoretical foundation and practical guidance for the continuous development and practical application of quantum computing technology.

[0003] Currently, in the field of classical machine learning, the data processed by algorithms is mainly real vectors; in the field of quantum machine learning, the data mainly processed by quantum algorithms is often complex vectors. Therefore, how to efficiently encode complex vector data into quantum states is an urgent problem to be solved currently. Summary of the Invention

[0004] The purpose of the present invention is to provide a quantum state amplitude encoding method, apparatus, device, and medium.

[0005] An embodiment of the present invention provides a quantum state amplitude encoding method, including: performing normalization processing on the complex vector to be encoded to obtain a normalized complex vector to be encoded, where the normalized complex vector to be encoded includes 2 n elements, and n is a positive integer; calculating the modulus length of each element in the normalized complex vector to be encoded to obtain a modulus length vector; constructing a quantum circuit including parameterized quantum gates according to the modulus length vector, and calculating the parameters of the parameterized quantum gates by using a real vector amplitude encoding algorithm to obtain a first quantum circuit with fixed parameter values, so as to output a first quantum state evolved by the first quantum circuit, where the modulus length vector is mapped to the amplitude of the first quantum state; calculating the argument of each element in the normalized complex vector to be encoded to obtain an argument vector; constructing a second quantum circuit according to the argument vector, where the second quantum circuit includes 2 nAn operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; execute the first quantum circuit and the second quantum circuit to output a target quantum state, where the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state; both the first quantum circuit and the second quantum circuit include n qubits.

[0006] Further, constructing the second quantum circuit according to the argument vector includes: initializing n qubits, and the n qubits are sorted in ascending order from the low bit to the high bit; dividing the initialized n qubits into 2 n operation units; arranging the sequence numbers of the 2 n operation units in sequence as 0, 1, ……, 2 n - 2, 2 n - 1; converting the sequence number of each operation unit into an n-bit binary string, where the characters in the n-bit binary string correspond one by one to the sorting of the qubits from the low bit to the high bit in order; distributing each computational basis state in the first quantum state in sequence according to the sequence number of each operation unit, so that each operation unit has a target basis state corresponding to the n-bit binary string; creating a multi-controlled phase shift gate in each operation unit, where the multi-controlled phase shift gate is an n-bit quantum gate, the multi-controlled phase shift gate acts on the highest-bit qubit, and the multi-controlled phase shift gate has n - 1 controlled bits, the sorting of each argument in the argument vector corresponds one by one to the sequence number of each operation unit, and the parameter carried by each multi-controlled phase shift gate is the corresponding argument in the argument vector; creating a first operation column and a second operation column in each operation unit, where the multi-controlled phase shift gate is located between the first operation column and the second operation column, the first operation column includes n first quantum gates, and the n quantum gates are correspondingly set on the n qubits, the second operation column is set to be the same as the first operation column, the first quantum gate is set to be an X gate or an I gate, the first operation column is used to convert the target basis state of the current operation unit into the all |1> state, perform an operation on the current multi-controlled phase shift gate to realize adding the current argument to the corresponding amplitude of the first quantum state, and the second operation column is used to make the computational basis states in the quantum states output by each operation unit consistent with the computational basis states in the first quantum state.

[0007] Further, creating a first operation column and a second operation column in each operation unit includes: an n-bit binary string performs a unitary operation to transform the target ground state corresponding to the current operation unit into an all |1> state; wherein, it is judged whether the current character in the n-bit binary string corresponding to the current operation unit is equal to "0", if the current character is equal to "0", the first quantum gate on the target qubit corresponding to the current character is set to an X gate, if the current character is not equal to "0", the first quantum gate is set to an I gate; all characters in the n-bit binary string are traversed in sequence, so that the target ground state corresponding to the current operation unit is transformed into an all |1> state, so as to complete the creation of the first operation column before the multi-controlled phase shift gate; a second operation column is created after the multi-controlled phase shift gate.

[0008] Further, constructing the second quantum circuit according to the argument vector further includes: traversing in sequence according to the serial number of each operation unit, so as to realize the creation of the multi-controlled phase shift gate, the first operation column and the second operation column in each operation unit, so as to realize adding each argument in the argument vector to the amplitude of the first quantum state correspondingly.

[0009] Further, constructing the second quantum circuit according to the argument vector further includes: arbitrarily arranging the front-back execution order of each operation unit in the second quantum circuit; adjusting the front-back execution order of each operation unit in the second quantum circuit, so that two adjacent X gates on the same qubit are cancelled out, so as to obtain an optimized second quantum circuit with the fewest quantum gates.

[0010] Further, executing the first quantum circuit and the second quantum circuit to output a target quantum state includes: connecting the first quantum circuit and the optimized second quantum circuit in sequence front and back to obtain a combined quantum circuit; executing the combined quantum circuit to output a target quantum state.

[0011] Further, the parameter-containing quantum gates in the first quantum circuit include one or more of the following: RX gate, RY gate, RZ gate, multi-qubit RX gate, multi-qubit RY gate, and multi-qubit RZ gate.

[0012] An embodiment of the present invention provides a quantum state amplitude encoding device, including: a normalization module, which is used to perform normalization processing on the complex vector to be encoded to obtain a normalized complex vector to be encoded, and the normalized complex vector to be encoded includes 2 nAn element, where n is a positive integer; a modulus vector module for calculating the modulus of each element in the normalized complex vector to be encoded to obtain a modulus vector; a first construction module for constructing a quantum circuit including parameterized quantum gates according to the modulus vector, calculating the parameters of the parameterized quantum gates using a real vector amplitude encoding algorithm to obtain a first quantum circuit with fixed parameter values, and outputting a first quantum state evolved by the first quantum circuit, where the modulus vector is mapped to the amplitude of the first quantum state; an argument vector module for calculating the argument of each element in the normalized complex vector to be encoded to obtain an argument vector; a second construction module for constructing a second quantum circuit according to the argument vector, where the second quantum circuit includes 2 n operation units connected in sequence, and the operation units are used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; an output module for executing the first quantum circuit and the second quantum circuit to output a target quantum state, where the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state; both the first quantum circuit and the second quantum circuit include n qubits.

[0013] An embodiment of the present invention provides an electronic device, which includes a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the steps of the above method are implemented.

[0014] An embodiment of the present invention provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the steps of the above method are implemented.

[0015] The above technical solution of the present invention has the following beneficial technical effects:

[0016] In the embodiment of the present invention, the amplitude encoding of the modulus vector into the quantum state can be realized by using the real vector amplitude encoding algorithm; the first quantum state evolved by the first quantum circuit can include 2 n computational basis states, and 2 n computational basis states can be assigned to 2 n operation units in sequence one by one, and then each argument in the argument vector can be added to the amplitude of the first quantum state in the corresponding order by executing the operation units in the second quantum circuit; connecting the first quantum circuit and the second quantum circuit in sequence and executing the first quantum circuit and the second quantum circuit can output the target quantum state, thereby realizing the efficient amplitude encoding of the normalized complex vector to be encoded with N = 2 n dimensions; the technical solution of the present invention can be flexibly adapted to various real vector amplitude encoding schemes, aiming to solve 2 nThe problem of amplitude encoding of a one-dimensional normalized complex vector, without relying on auxiliary qubits, can accurately output an amplitude-encoded quantum state corresponding to the normalized complex vector. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings in the embodiments of the present invention.

[0018] Figure 1 It is a flowchart of a method for amplitude encoding of a quantum state according to an embodiment of the present invention.

[0019] Figure 2 It is a schematic diagram of a Top-down amplitude-encoding quantum circuit constructed according to a modulus vector in an embodiment of the present invention.

[0020] Figure 3 It is another schematic diagram of a Top-down amplitude-encoding quantum circuit constructed according to a modulus vector in an embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of an optimized first quantum circuit in an embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of a second quantum circuit constructed according to an argument vector in an embodiment of the present invention.

[0023] Figure 6 is Figure 5 A schematic diagram of a second quantum circuit after optimizing the quantum circuit in

[0024] Figure 7 It is another schematic diagram of a second quantum circuit constructed according to an argument vector in an embodiment of the present invention.

[0025] Figure 8 It is a schematic diagram of a combined quantum circuit in an embodiment of the present invention.

[0026] Figure 9 It is a structural block diagram of a device for amplitude encoding of a quantum state according to an embodiment of the present invention.

[0027] Figure 10 It is a schematic diagram of an electronic device for implementing a method for amplitude encoding of a quantum state according to an embodiment of the present invention. Detailed Embodiments

[0028] The principles and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that the purpose of providing these embodiments is to make the principles and spirit of the present invention clearer and more thorough, so that those skilled in the art can better understand and then implement the principles and spirit of the present invention. The exemplary embodiments provided herein are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments herein, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0029] Those skilled in the art know that the embodiments of the present invention can be implemented as a quantum state amplitude encoding method, a quantum circuit, an electronic device, and a computer-readable storage medium. Therefore, the present disclosure can be specifically implemented in at least one of the following forms: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0030] In this article, terms such as first and second are only used to distinguish one entity (or operation) from another entity (or operation), and do not require or imply any order or association between these entities (or operations). In this article, the elements (such as components, components, processes, steps) defined by the statement "including..." do not exclude the existence of other elements outside the listed elements, that is, other elements that are not explicitly listed may also be included. In this article, any element and its quantity in the drawings are used for illustration rather than limitation, and any naming in the drawings is only used for distinction and does not have any limiting meaning.

[0031] The principles and spirit of the present invention will be elaborated in detail below with reference to several exemplary or representative embodiments of the present invention.

[0032] A quantum state, that is, the state of a quantum bit, whose eigenstates are represented in binary in a quantum algorithm (or quantum program). For example, a group of quantum bits are q0, q1, q2, representing the 0th, 1st, and 2nd quantum bits. Sorted from the lowest bit to the highest bit as q0, q1, q2, the quantum state that can be evolved according to this group of quantum bits can be expressed as a linear combination of 8 computational basis states on 3 quantum bits: x0|000>, x1|001>, x2|010>, x3|011>, x4|100>, x5|101>, x6|110>, x7|111>. This quantum state has a total of 8 (2 3 ), and the amplitudes correspond in sequence to the 8 (2 3( ) elements, each computational ground state corresponds exactly to the qubit positions. For example, in the state |000>, 000 corresponds to q2q1q0 from the high-order bit to the low-order bit, that is, the qubits q2q1q0 are all in the |0> state; for example, in the state |001>, 001 corresponds to q2q1q0 from the high-order bit to the low-order bit, that is, the qubits q2q1 are all in the |0> state, and the qubit q0 is in the |1> state.

[0033] In the field of quantum machine learning, to achieve the effective processing of classical data by quantum algorithms, the key lies in mapping classical data to quantum states. Amplitude encoding, as a widely used encoding strategy in quantum information processing, characterizes data through the amplitude attributes of quantum states. The advantage of this encoding technique is that it can make full use of the high-dimensional data representation ability provided by the quantum superposition principle, enabling quantum systems to efficiently process large-scale data sets. This encoding method provides important technical support for quantum machine learning algorithms when dealing with high-dimensional data, enabling quantum algorithms to effectively utilize their unique quantum characteristics to enhance data processing capabilities.

[0034] For amplitude encoding, a series of technical solutions have been proposed. These include the top-down Top-down amplitude encoding technique, which directly utilizes the superposition characteristics of quantum states to encode data in an exact manner without the need for additional auxiliary qubits. In contrast, the bottom-up Bottom-up amplitude encoding technique requires the introduction of auxiliary qubits and encodes data by constructing quantum states step by step. This method provides greater flexibility when dealing with complex data structures, although it may require more quantum resources. In addition, the MPS approximation encoding technique, as an approximation method, although it cannot fully guarantee 100% fidelity of data encoding, can provide an effective approximation of data encoding in specific cases. This technique is particularly important when dealing with high-dimensional data because it can significantly reduce the demand for computing resources while maintaining a relatively high fidelity.

[0035] Currently, in the field of classical machine learning, the data processed by algorithms is mainly real vectors; in the field of quantum machine learning, the data mainly processed by quantum algorithms is often complex vectors. Therefore, how to efficiently encode complex vector data into quantum states is an urgent problem to be solved currently.

[0036] Based on this, the embodiments of the present invention propose a quantum state amplitude encoding method that can accurately and efficiently encode complex vector data into quantum states.

[0037] Figure 1 The flowchart of a quantum state amplitude encoding method according to an embodiment of the present invention is shown. The method includes the following steps:

[0038] S110: Normalize the complex vector to be encoded to obtain a normalized complex vector to be encoded; the normalized complex vector to be encoded includes 2 n elements, where n is a positive integer.

[0039] Specifically, normalize the obtained complex vector to be encoded to achieve the purpose of encoding the input classical data onto the amplitude of the quantum state, and determine whether the number of elements of the complex vector to be encoded is N = 2 n . If the number of elements does not conform to the form of 2 n , it is necessary to pad it with zeros to make the number of elements reach 2 n to meet the encoding conditions of amplitude encoding; where n is a positive integer.

[0040] S120: Calculate the modulus length of each element in the normalized complex vector to be encoded to obtain a modulus length vector.

[0041] Specifically, for a normalized complex vector to be encoded with N = 2 n dimensions , where normalization means that the modulus length of the complex vector to be encoded is 1, that is , T represents transpose; specifically, the j-th element in the complex vector to be encoded x can be written as , where and are real numbers, and respectively represent the real part and the imaginary part of the j-th element, and ; is the j-th element in the complex vector to be encoded; for the normalized complex vector to be encoded, calculate the modulus length of each element, and the modulus length vector

[0042] can be obtained,

[0043] where the modulus length of each element , and .

[0044] S130: Construct a quantum circuit including a parameterized quantum gate according to the modulus length vector, calculate the parameters of the parameterized quantum gate using the real vector amplitude encoding algorithm, and obtain a first quantum circuit with fixed parameter values to output a first quantum state evolved by the first quantum circuit; where the modulus length vector is mapped onto the amplitude of the first quantum state.

[0045] Specifically, as described above, each modulus in the modulus vector is a real number, and the modulus vector is a normalized real vector. Therefore, a real vector amplitude encoding algorithm can be used to implement the amplitude encoding of the quantum state for the modulus vector. A quantum circuit including parameterized quantum gates is constructed based on the modulus vector. This quantum circuit can include n qubits and does not require the use of auxiliary qubits. The parameterized quantum gates can be, for example, RX gate, RY gate, RZ gate, two-qubit CRX gate, CRY gate, and CRZ gate, as well as other multi-qubit gates, etc. The parameters carried by the quantum gates are, for example, rotation angles. The real vector amplitude encoding algorithm is, for example, a variational quantum algorithm. By constructing a quantum circuit including parameterized quantum gates and constructing a quantum-classical hybrid neural network, the training parameters of the variational quantum circuit in the quantum-classical hybrid neural network are trained and optimized through a classical optimizer until the training parameters or the loss value converge to a set threshold, at which point the training stops and the training parameters are fixed to obtain the target variational quantum circuit. Therefore, the quantum final state evolved by the target variational quantum circuit can be output to implement the amplitude encoding of the modulus vector. In this way, combining classical optimization techniques and quantum circuit algorithms can accurately map the modulus vector to its corresponding amplitude-encoded quantum state, ensuring the integrity and accuracy of the information.

[0046] S140: Calculate the argument of each element in the normalized complex vector to be encoded to obtain an argument vector.

[0047] Specifically, for the complex vector to be encoded, calculate the argument of each element to obtain an argument vector

[0048] ,

[0049] where, represents the argument of the complex number x j and satisfies .

[0050] S150: Construct a second quantum circuit according to the argument vector; wherein, the second quantum circuit includes two operation units connected in sequence, and the operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly. n Specifically, the first quantum state evolved by the first quantum circuit is, for example, a linear combination of two computational basis states. The two computational basis states and the two operation units can be correspondingly assigned in sequence. For example, the sequence numbers of the two operation units are set to 0, 1,..., 2

[0051] -2, 2 n -1 in sequence, so that they are in one-to-one correspondence with the two n computational basis states. For example, the sequence numbers of the two n operation units are set to 0, 1,..., 2 n -2, 2 n -1 in sequence, so that they are in one-to-one correspondence with the two n computational basis states, and nThe computational ground states can be put into one-to-one correspondence in sequence; then, by executing the operation unit, each argument in the argument vector can be added to the amplitude of the first quantum state in the corresponding sequence one by one.

[0052] S160: Execute the first quantum circuit and the second quantum circuit to output a target quantum state; wherein, the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state; both the first quantum circuit and the second quantum circuit include n qubits.

[0053] In the embodiments of the present invention, the amplitude encoding of the modulus vector into a quantum state can be realized by adopting the real vector amplitude encoding algorithm; the first quantum state evolved by the first quantum circuit can include 2 n computational ground states, and 2 n computational ground states can be assigned to 2 n operation units in one-to-one correspondence in sequence, and then by executing the operation unit in the second quantum circuit, each argument in the argument vector can be added to the amplitude of the first quantum state in the corresponding sequence one by one; connecting the first quantum circuit and the second quantum circuit in the front-back order and executing the first quantum circuit and the second quantum circuit can output the target quantum state, thereby realizing the efficient amplitude encoding of the normalized complex vector to be encoded with N = 2 n dimensions; the technical solution of the present invention can be flexibly adapted to various real vector amplitude encoding schemes, aiming to solve the amplitude encoding problem of the 2 n -dimensional normalized complex vector, and without relying on auxiliary qubits, the amplitude encoding quantum state corresponding to the normalized complex vector can be accurately output.

[0054] In some embodiments, step S150: The constructing the second quantum circuit according to the argument vector may include the following specific steps:

[0055] S151: Initialize n qubits; the n qubits are sorted in sequence from the low bit to the high bit;

[0056] S152: Divide the initialized n qubits into 2 n operation units;

[0057] S153: Set the sequence numbers of the 2 n operation units to 0, 1,..., 2 n -2, 2 n -1 in sequence;

[0058] S154: Convert the sequence number of each operation unit into an n-bit binary string; wherein, the characters in the n-bit binary string are in one-to-one correspondence with the sorting of the qubits from the low bit to the high bit in sequence from the low bit to the high bit;

[0059] S155: Sequentially allocate each computational basis state in the first quantum state according to the serial number of each operation unit, so that each operation unit has a target basis state corresponding to an n-bit binary string;

[0060] S156: Create a multi-controlled phase shift gate in each operation unit. The multi-controlled phase shift gate is an n-qubit quantum gate; among them, the multi-controlled phase shift gate acts on the qubit with the highest bit, and the multi-controlled phase shift gate has n - 1 control bits; the sorting of each argument in the argument vector corresponds one-to-one with the serial number of each operation unit; the parameter carried by each multi-controlled phase shift gate is the corresponding argument in the argument vector;

[0061] S157: Create a first operation column and a second operation column in each operation unit. The multi-controlled phase shift gate is located between the first operation column and the second operation column; the first operation column includes n first quantum gates, and the n quantum gates are correspondingly set on n qubits, and the second operation column is set to be the same as the first operation column; among them, the first quantum gate is set to be an X gate or an I gate; the first operation column is used to convert the target basis state of the current operation unit into the all |1> state, and perform an operation on the current multi-controlled phase shift gate to realize adding the current argument to the amplitude of the corresponding first quantum state; the second operation column is used to make the computational basis states in the quantum states output by each operation unit consistent with the computational basis states in the first quantum state.

[0062] Specifically, the Multiple-Control Phase Shift Gate, also known as the Multiple-Control PS Gate, can apply a specific phase change to the target qubit under the condition of multiple control qubits. That is, when all control qubits are in the |1> state, performing the Multiple-Control PS Gate operation can achieve a phase shift on the target qubit; otherwise, the target qubit remains unchanged. When the first quantum gate is set to the X gate, each X gate in the first operation column is used to transform the target qubit where the X gate is located from the |0> state to the |1> state, so that the target ground state of the current operation unit is transformed into the all-|1> state. Perform an operation on the current Multiple-Control Phase Shift Gate to add the current argument to the amplitude of the corresponding first quantum state, thereby obtaining the quantum state output by the current operation unit. Since the X gates in the first operation column cause the computational ground states in the quantum state output by each operation unit to change relative to the respective computational ground states in the first quantum state, by setting the second operation column to be the same as the first operation column and the X gates in the second operation column perform operations to transform the target qubit where the X gate is located from the |1> state to the |0> state, so that the all-|1> state in the quantum state output by the current operation unit is transformed into the corresponding target ground state, and the computational ground states in the quantum states output by other operation units are restored to be consistent with the respective computational ground states in the first quantum state. When the first quantum gate is set to the I gate, since the meaning of performing the I gate operation in the quantum circuit is not to perform any operation on the qubit, no quantum gate symbol is added in the quantum circuit in this embodiment.

[0063] In some embodiments, step S157: Creating the first operation column and the second operation column in each operation unit may include the following specific steps:

[0064] S1571: The n-bit binary string performs a unitary operation to transform the target ground state corresponding to the current operation unit into the all-|1> state; where

[0065] S15711: Determine whether the current character in the n-bit binary string corresponding to the current operation unit is equal to "0"; if the current character is equal to "0", set the first quantum gate on the target qubit corresponding to the current character to the X gate; if the current character is not equal to "0", set the first quantum gate on the target qubit corresponding to the current character to the I gate;

[0066] S15712: Traverse all characters in the n-bit binary string in sequence, so that the target ground state corresponding to the current operation unit is transformed into the all-|1> state to complete the creation of the first operation column before the Multiple-Control Phase Shift Gate;

[0067] S1572: Create the second operation column after the Multiple-Control Phase Shift Gate.

[0068] Specifically, it is determined whether the current character in the n-bit binary string corresponding to the current operation unit is equal to "0"; if the current character is equal to "0", an X gate operation is performed on the target qubit corresponding to the current character. Correspondingly, an X gate can be created first on the target qubit in the first operation column. Performing the X gate operation can transform the target qubit where it is located from the |0> state to the |1> state; if the current character is not equal to "0" but equal to "1", an I gate can be created on the target qubit in the first operation column, which is equivalent to not performing any operation on the target qubit corresponding to the current character. By sequentially traversing all the characters in the n-bit binary string from the low order to the high order, the target ground state corresponding to the current operation unit can be transformed into the all |1> state, thereby completing the creation of the first operation column before the multi-controlled phase shift gate; as Figure 5 shown, the I gates are not shown in the first operation column and the second operation column, and the X gates created in the second operation column in each operation unit are the same as the X gates created in the first operation column.

[0069] In some embodiments, step S150: The constructing the second quantum circuit according to the argument vector further includes the following specific steps:

[0070] S158: Traverse in sequence according to the serial numbers of each operation unit to achieve the creation of the multi-controlled phase shift gate, the first operation column, and the second operation column in each operation unit, so as to realize adding each argument in the argument vector to the amplitude of the first quantum state correspondingly.

[0071] Specifically, set the serial numbers of 2 n operation units to 0, 1, ……, 2 n -2, 2 n -1 in sequence; set each argument in the argument vector to , by setting the subscript data of each argument to be the same as the serial number of each operation unit, convert the serial number of each operation unit into an n-bit binary string; after distributing each computational ground state in the first quantum state according to the serial number of each operation unit in sequence, each operation unit has a target ground state corresponding to the n-bit binary string, and the target ground state corresponds to the qubit positions in a one-to-one manner. For example, when the serial number of the operation unit is "0", its target ground state is the |000> state, and 000 corresponds to q2q1q0 from the high order to the low order, that is, the qubits q2q1q0 are all in the |0> state; when the serial number of the operation unit is "1", its target ground state is the |001> state, and 001 corresponds to q2q1q0 from the high order to the low order, that is, the qubits q2q1 are all in the |0> state, and the qubit q0 is in the |1> state. Therefore, each argument can be accurately added to the amplitude of the first quantum state correspondingly.

[0072] The following takes a two-qubit system as an example to elaborate on the implementation process of adding each argument to the amplitude of the first quantum state correspondingly.

[0073] The two qubits are denoted as q1 and q0 from high bit to low bit. After executing the first quantum circuit, the first quantum state that can be evolved is represented as follows:

[0074]

[0075] The binary character corresponding to the operation unit with serial number 0 is

[00] . Therefore, X gates need to be created on both qubits q1 and q0. By performing the X gate on both qubits q1 and q0, the quantum states corresponding to each operation unit can be obtained as follows:

[0076]

[0077] Comparing with the quantum state before performing the X gate, it can be seen that the overall quantum state of this quantum system has not changed.

[0078] Then, perform the C ^ { 1}PS(β0) gate operation on the two qubits, increasing the first argument β0 to the first quantum state to obtain That is, the quantum state of the current quantum system is represented as:

[0079]

[0080] Then, perform the X gate operation on the two qubits again. The quantum state of this quantum system obtained is represented as:

[0081]

[0082] Thus, the first argument β0 is encoded into the amplitude of the first quantum state.

[0083] For the binary character corresponding to the operation unit with serial number 1 is

[01] . Therefore, only an X gate needs to be created on the second qubit q1. By performing the X gate on the second qubit q1, the quantum state of the current quantum system is represented as:

[0084]

[0085] Comparing with the quantum state before performing the X gate, it can be seen that the overall quantum state of this quantum system has not changed.

[0086] Then, perform the C ^ { 1}PS(β1) gate operation on the two qubits, increasing the second argument β1 to the second quantum state to obtain That is, the quantum state of the current quantum system is represented as:

[0087]

[0088] Then, perform the X gate operation on the second qubit q1, and the quantum state of the quantum system obtained is represented as:

[0089]

[0090] Thus, the second argument β1 is encoded onto the second quantum state, and it can be seen that the computational basis state of the quantum state corresponding to each operation unit has returned to the computational basis state of the original first quantum state.

[0091] And so on, the target quantum state data obtained after encoding is represented as:

[0092]

[0093] Among them, the binary character corresponding to the last operation unit with the serial number 3 is

[11] , that is, create the I gate on both qubits, which is equivalent to performing no operation on the two qubits, and perform the C ^ { 1}PS(β1) gate operation to add the fourth argument β3 to the fourth quantum state on.

[0094] In some embodiments, step S150: The constructing the second quantum circuit according to the argument vector further includes the following specific steps:

[0095] S159: Set the front - to - back execution order of each operation unit in the second quantum circuit to be arbitrary;

[0096] S1591: Adjust the front - to - back execution order of each operation unit in the second quantum circuit so that two adjacent X gates on the same qubit cancel each other out to obtain an optimized second quantum circuit with the fewest quantum gates.

[0097] Specifically, as Figure 5 shown, each operation unit includes a first operation column, a multi - controlled phase - shift gate, and a second operation column, and can be arranged and executed in sequence from front to back to perform quantum operations. The "front" and "back" here refer to the "front" and "back" in the sense of time, corresponding to Figure 5, that is, the left is the front and the right is the back. In the order from front to back, it is in the order from left to right. When performing two consecutive X-gate operations on a qubit, it is equivalent to not performing any operation on the qubit. That is, the state after two consecutive X-gate operations is the same as the state before the operation. Therefore, after eliminating two adjacent X-gates, the quantum state is not changed, and the quantum operations are reduced, resulting in a reduction in the number of quantum gates in the quantum circuit and simplifying the quantum circuit structure. Each operation unit can perform operations in the order from front to back. To eliminate more adjacent X-gates on the same qubit, the front-to-back execution order of each operation unit in the second quantum circuit can be adjusted and not performed in the preset order 0, 1, ……, 2 n -2, 2 n -1. After adjusting the order, then eliminate two adjacent X-gates on the same qubit, as Figure 6 shown, to obtain the optimized second quantum circuit with the fewest quantum gates. Similarly, two adjacent X-gates on the same qubit in the first quantum circuit can also be eliminated.

[0098] In some embodiments, step S160: Execute the first quantum circuit and the second quantum circuit to output the target quantum state, including the following specific steps:

[0099] S161: Connect the first quantum circuit and the optimized second quantum circuit in the front-to-back order to obtain a combined quantum circuit;

[0100] S162: Execute the combined quantum circuit to output the target quantum state.

[0101] In an exemplary embodiment, the parameterized quantum gates in the first quantum circuit include one or more of the following: RX gate, RY gate, RZ gate; multi-qubit RX gate, multi-qubit RY gate, and multi-qubit RZ gate.

[0102] The implementation manners and advantages of the embodiments of the present invention have been described above through multiple embodiments. The following combines specific examples to describe the specific processing process of the embodiments of the present invention in detail.

[0103] Step S1: Obtain a normalized complex vector to be encoded with N = 2 n dimensions, where normalization means that the modulus length of the complex vector to be encoded is 1, that is , T represents transpose; specifically, the j-th element in the complex vector x to be encoded can be written as , where and are real numbers, and respectively represent the real part and the imaginary part of the j-th element, and . If the dimension of the complex vector x to be encoded is not equal to 2 n ​, appropriate 0s can be added to make its dimension equal to 2 n . If the complex vector to be encoded does not satisfy the normalization condition, a normalization operation, such as extracting the common factor, can be performed to make it satisfy the normalization condition.

[0104] For example, if there is a complex vector x to be encoded with N = 16 = 2 4 dimensions after normalization as follows:

[0105] [1.42285003e-01 + 0.14238149i 2.45769699e-01 + 0.19062108i 3.90238908e-05 + 0.04789905i 1.03153767e-01 + 0.06759085i 5.00720875e-02 + 0.27320847i 3.15052852e-02 + 0.3303641i 6.35506865e-02 + 0.10693815i 1.17902913e-01 + 0.23621565i 1.35374298e-01 + 0.29901787i 1.83840516e-01 + 0.30523356i 1.43026248e-01 + 0.02901649i 2.33792120e-01 + 0.01332522i 6.97576832e-02 + 0.05794496i 2.99607552e-01 + 0.2996161i 9.34445599e-03 + 0.03355525i 2.28758843e-01 + 0.14367899i].

[0106] According to the above complex vector x to be encoded, it can be known that n = 4, and the modulus of the complex vector x to be encoded is 1.

[0107] Step S2: For the complex vector x to be encoded, calculate the modulus of each element to obtain the modulus vector

[0108] ,

[0109] where, , and .

[0110] For example, by calculating the modulus of each element of the above complex vector x to be encoded, the corresponding modulus vector γ can be obtained as follows:

[0111] [0.20128962 0.31102916 0.04789906 0.12332568 0.27775903 0.331862960.12439637 0.26400555 0.3282345 0.35632129 0.14593993 0.23417155 0.090684910.42371511 0.03483208 0.27013748]。

[0112] Step S3: For the complex vector x to be encoded, calculate the argument of each element to obtain the argument vector

[0113] ,

[0114] where represents the argument of the complex number x j and satisfies .

[0115] For example, by calculating the modulus of each element of the above complex vector x to be encoded, the corresponding argument vector β can be obtained as follows:

[0116] [0.78573712 0.65969015 1.56998162 0.58005259 1.38953368 1.475718521.03459688 1.10784295 1.14567463 1.02869135 0.20015873 0.05693442 0.693158820.78541244 1.29919799 0.5608115 ].

[0117] Step S4: According to the modulus vector γ, a Top-down amplitude encoding quantum circuit can be constructed, as Figure 2 shown; according to each element of the modulus vector , use the angle tree algorithm to calculate each parameter required for the RY gates in the above Top-down amplitude encoding circuit, where , and there are a total of 2 n -1 RY gates carrying parameters.

[0118] For example, for the above N = 2 4 -dimensional complex vector x to be encoded, generate the complete Top-down amplitude encoding circuit of the corresponding modulus vector, as Figure 3As shown in the figure; among them, the 4 qubits arranged in ascending order can be denoted as q0, q1, q2, and q3, and the parameters carried by each Ry gate can be successively denoted as: theta0, theta1, ……theta13, theta14. For example, in Figure 2 the control bit of CRy(θ1) is q n-1 , at this time it is a hollow dot. The hollow dot indicates that the control bit is in the |0> state and takes effect. An X gate needs to be added on each side of the hollow dot to turn the hollow dot into a solid dot. The X gate added on the left is used to convert the control bit to the |1> state, and the X gate added on the right is used to revert (or convert) the control bit back to its initial state; in Figure 2 the control bit of C^Ry(θ2) is q n-1 , but at this time the control bit is a solid dot. The solid dot indicates that the control bit is in the |1> state and takes effect, so there is no need to add an X gate; in Figure 2 the control bits of C^2Ry(θ3) are q n-2 and q n-1 , but at this time both control bits are hollow dots, so an X gate needs to be added on each side of the hollow dots; and so on. By adding an X gate on each side of all the control bits that are hollow dots, the complete Top-down amplitude encoding circuit as shown in Figure 3 can be obtained. By canceling adjacent two X gates on the same qubit to reduce the number of quantum gates, the optimized Top-down amplitude encoding circuit can be obtained. For example, calculating the modulus vector γ in step S2 above and obtaining each parameter required for the corresponding RY gate is as follows:

[0119]

[0120] Therefore, the first quantum circuit with fixed parameters and optimized as shown in Figure 4 can be obtained.

[0121] Step S5: Executing the Figure 4 quantum circuit, the quantum state that realizes amplitude encoding for the modulus vector γ can be obtained.

[0122] Step S6: According to the argument vector β, a second quantum circuit can be constructed, which can include the following specific steps:

[0123] Step S6-1: Initialize n qubits; the n qubits are sorted in ascending order from low to high; for example, constructing 4 qubits for the argument vector β in step S3 above, and sorting them in ascending order from low to high as q0, q1, q2, q3;

[0124] Step S6-2: Divide the initialized n qubits into 2 n operation units;

[0125] Step S6-3: Set the serial numbers p of 2 n operation units to 0, 1, ……, 2 n -2, 2 n -1 in sequence;

[0126] For example, divide the above 4 qubits into 16 operation units, and set the serial numbers p of each operation unit to 0, 1, ……, 14, 15 in sequence;

[0127] Step S6-4: Convert the serial number p of each operation unit into an n-bit binary string, which can be denoted as

[0000] ,

[0001] , ……,

[1110] ,

[1111] in sequence; It can be seen that this is consistent with each computational basis state of the first quantum state assigned to each operation unit;

[0128] Step S6-5: Create a multi-controlled PS gate in each operation unit, which can be denoted as C^{n-1}PS(β j ) gate. The multi-controlled phase shift gate is a 4-bit quantum gate, which can be denoted as C^{3}PS(β j ) gate; β j is the j-th element in the argument vector;

[0129] Step S6-6: Let p = 0, that is, start from the leftmost 1st operation unit. The corresponding n-bit binary string is

[0000] . Traverse the n-bit binary string from the low bit to the high bit. If the current character m k is "0", then perform the X gate on the k-th qubit, otherwise perform the I gate; It can be seen that X gates need to be created on all 4 qubits in the 1st operation unit to obtain the first operation column, and the first operation column is located on the left side of the multi-controlled PS gate;

[0130] Step S6-7: Perform the C^{n-1}PS(β j ) gate operation on the left side of the n qubits;

[0131] Step S6-8: Create a second operation column on the right side of the multi-controlled PS gate, and set the second operation column to be the same as the first operation column;

[0132] Step S6-9: Let p = 1, that is, starting from the second operation unit on the left, repeat the above steps S6-6, S6-7, and S6-8; for example, the n-bit binary string corresponding to the second operation unit is

[0001] . Traverse the n-bit binary string from the low bit to the high bit. The first character m0 is "1", so perform the I gate on the qubit q0, and perform the X gate on the remaining qubits q1, q2, and q3. It can be seen that X gates need to be created on the qubits q1, q2, and q3 in the second operation unit, and an I gate (the I gate is not shown in the figure) needs to be created on the qubit q0. Traverse p in sequence until p = 2 n -1 to complete the creation of each operation unit, and the second quantum circuit as shown in Figure 5 can be obtained; it should be noted that Figure 5 the dashed line in does not belong to the structure of the variational quantum circuit in the embodiments of the present invention, and is only used to distinguish each operation unit.

[0133] Step S6-10: If further optimization is performed on Figure 5 , two adjacent X gate operations on the same qubit can be canceled, and the obtained quantum circuit is as shown in Figure 6 .

[0134] For example, the complete second quantum circuit constructed for the argument vector β in step S3 is as shown in Figure 7 . This second quantum circuit includes a total of 16 operation units. The 4 qubits are sorted in order from the low bit to the high bit as q0, q1, q2, q3; C^{3}PS(β j ) gates are created in each operation unit, and the parameters carried by each C^{3}PS(β j ) gate are set as beta0, beta1,..., beta14, beta15 in sequence; the parameter values are as follows:

[0135]

[0136] Step S7: Further optimize the complete second quantum circuit as shown in Figure 7 , that is, cancel the adjacent X gates on the same qubit, and the optimized second quantum circuit can be obtained.

[0137] Step S8: Connect the optimized first quantum circuit as shown in Figure 4 with the optimized second quantum circuit, and the combined quantum circuit as shown in Figure 8 can be obtained. After optimization, the number of quantum gates required for the combined quantum circuit is reduced from 129 to 83; the reduction in the number of quantum gates can improve the amplitude encoding efficiency of complex vectors. It should be noted that Figure 7 the thick solid line in does not belong to the structure of the variational quantum circuit in the embodiments of the present invention, and is only used to distinguish each operation unit.

[0138] Step S9: Execute Figure 8 the combined quantum circuit shown to obtain the target quantum state as follows:

[0139] (0.14228500264993257 + 0.14238149124285226i)|0000> (0.24576969872687432 + 0.19062107712419107i)|0001> (3.9023890839065115e-05 + 0.04789904538559103i)|0010> (0.1031537674582972 + 0.06759084792060513i)|0011> (0.0500720875117822 + 0.2732084681171133i)|0100> (0.03150528522047643 + 0.33036410384464304i)|0101> (0.06355068646401656 + 0.10693814599003476i)|0110> (0.11790291257675982 + 0.2362156531173297i)|0111> (0.1353742979644006 + 0.2990178730394566i)|1000> (0.18384051575449734 + 0.3052335609438082i)|1001> (0.14302624782414 + 0.029016492424040162i)|1010> (0.23379211967309557 + 0.01332521994791732i)|1011> (0.06975768320806329 + 0.05794495596225954i)|1100> (0.29960755153183993 + 0.2996161042307253i)|1101> (0.0093444559922479 + 0.033555254530341194i)|1110> (0.22875884338637364 + 0.14367898783299107i)|1111>

[0140] It can be seen that the amplitudes of the output target quantum state correspond one-to-one with the elements of the normalized complex vector x to be encoded, and the target quantum state The amplitude is consistent or nearly consistent with the complex vector x to be encoded, which means that the amplitude encoding of the complex vector with a fidelity of up to 100% is achieved.

[0141] In summary, the technical solution of the present invention has the following advantages:

[0142] 1. The technical solution of the present invention can efficiently implement the amplitude encoding of complex vectors, and achieves a fidelity of 100%. It can process any normalized complex vector, significantly expanding the application scope of amplitude encoding; this wide applicability makes this technical solution more advantageous in quantum machine learning tasks and can play a more effective role, bringing important progress to the field of quantum computing.

[0143] 2. The technical solution of the present invention has achieved remarkable results through simulation experiments conducted in the MindSpore Quantum quantum computing software; the experimental data clearly show that this technical solution has successfully implemented the amplitude encoding of normalized complex vectors and accurately obtained the corresponding encoded quantum states; particularly notable is that the fidelity of this process has reached 100%, which not only verifies the efficiency and accuracy of this technical solution in the field of amplitude encoding but also provides strong evidence for its reliability in quantum computing applications.

[0144] 3. In the technical solution of the present invention, a series of different real vector amplitude encoding schemes can be adapted for the modulus vector to meet the specific requirements in specific application scenarios; in addition, for the processing of the argument vector, each operation unit is allowed to execute in any order, further enhancing the adaptability and flexibility of the quantum algorithm; this design not only improves the generality of the quantum algorithm but also provides solid technical support for the diverse applications of quantum computing.

[0145] Corresponding to the method embodiment of the present invention, the embodiment of the present invention also provides a quantum state amplitude encoding device, as Figure 9 shown, specifically including:

[0146] A normalization module 510, which is used to normalize the complex vector to be encoded to obtain a normalized complex vector to be encoded; the normalized complex vector to be encoded includes 2 n elements, where n is a positive integer;

[0147] A modulus vector module 520, which is used to calculate the modulus of each element in the normalized complex vector to be encoded to obtain a modulus vector;

[0148] A first construction module 530 is used to construct a quantum circuit including a parameterized quantum gate according to the modulus vector, and calculate the parameters of the parameterized quantum gate using a real vector amplitude coding algorithm to obtain a first quantum circuit with fixed parameter values, so as to output a first quantum state after the first quantum circuit evolves; wherein the modulus vector is mapped to the amplitude of the first quantum state;

[0149] An argument vector module 540, which is used to calculate the argument of each element in the normalized complex vector to be encoded to obtain an argument vector;

[0150] The second construction module 550 is used to construct a second quantum circuit according to the argument vector; wherein the second quantum circuit includes two sequentially connected n An operation unit, the operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state accordingly;

[0151] An output module 560, which is used to execute the first quantum circuit and the second quantum circuit to output a target quantum state; wherein the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state;

[0152] The first quantum circuit and the second quantum circuit both include n quantum bits.

[0153] In another aspect, the present invention further provides an electronic device, see Figure 10 , Figure 10 1 is a block diagram of the structure principle of an electronic device according to an embodiment of the present invention. Figure 10 As shown, the electronic device includes a processor 601 and a memory 602 storing computer program instructions; when the processor 601 executes the computer program instructions, the quantum state amplitude encoding method in the above-mentioned embodiment is implemented.

[0154] Specifically, the processor 601 may include a central processing unit (CPU) or a graphics processing unit (GPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The memory 602 may include a memory for data or instructions. For example, the memory 602 may be at least one of the following: a hard disk drive (HDD), a read only memory (ROM), a random access memory (RAM), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, a universal serial bus (USB) drive, or other physical / tangible memory storage devices. Additionally, the memory 602 includes removable or non-removable (or fixed) media. Further, the memory 602 may be inside or outside the integrated gateway disaster recovery device. The memory 602 may be a non-volatile solid state memory. In other words, generally, the memory 602 includes a tangible (non-transitory) computer-readable storage medium (such as a memory device) encoded with executable instructions, and when the executable instructions stored therein are executed by the processor 601 (such as by one or more processors), the quantum state amplitude encoding method in the embodiments of the present invention can be implemented.

[0155] In one example, Figure 10 The illustrated electronic device may further include a communication interface 603 and a bus 610. Among them, the processor 601, the memory 602, and the communication interface 603 are connected through the bus 610 to complete communication with each other. The communication interface 603 is mainly used to implement communication between various modules, devices, units, and / or devices in the electronic device.

[0156] The bus 610 includes hardware, software, or both, and can couple the components of the online data flow charging device to each other. For example, the bus may include at least one of the following: an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a front side bus (FSB), a hypertransport (HT) interconnect, an industry standard architecture (ISA) bus, an infinite bandwidth interconnect, a low pin count (LPC) bus, a memory bus, a microchannel architecture (MCA) bus, a peripheral component interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a serial advanced technology attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable buses. The bus 610 may include one or more buses. Although the embodiments of the present invention describe or illustrate specific buses, the embodiments of the present invention may contemplate any suitable bus or interconnect method.

[0157] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the foregoing quantum state amplitude encoding method is implemented.

[0158] The flowcharts and / or block diagrams of the methods and systems of the embodiments of the present invention are exemplarily described above, and the relevant aspects are described. It should be understood that each box in the flowchart and / or block diagram, or a combination thereof, can be implemented by computer program instructions, can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. For example, these computer program instructions can be provided to a processor of a general-purpose computer, a dedicated computer, or other programmable data processing device to form a machine, so that these instructions executed by such a processor enable the implementation of the specified function / action in each box or a combination thereof in the flowchart and / or block diagram. Such a processor can be a general-purpose processor, a dedicated processor, a special application processor, or a field-programmable logic circuit.

[0159] The functional blocks shown in the structural block diagrams of the embodiments of the present invention can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc.; when implemented in software, it is a program or a code segment for performing the required tasks. The program or code segment can be stored in a memory, or transmitted via a data signal carried in a carrier wave on a transmission medium or a communication link. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0160] It should be noted that the present invention is not limited to the specific configurations and processes described above or shown in the figures. The above are only specific embodiments of the present invention. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the described systems, devices, modules, or units can refer to the corresponding processes in the method embodiments and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of the present invention.

Claims

1. A quantum state amplitude encoding method, characterized in that, Including: Normalize the complex vector to be encoded to obtain a normalized complex vector to be encoded, where the normalized complex vector to be encoded includes 2 n elements, and n is a positive integer; Calculating the modulus length of each element in the normalized complex vector to be encoded to obtain a modulus length vector; Constructing a first quantum circuit including n qubits according to the modulus length vector, and calculating the parameters of the parameter-containing quantum gates in the first quantum circuit by using the real vector amplitude encoding algorithm to obtain a first quantum circuit with fixed parameter values, so as to output a first quantum state evolved by the first quantum circuit, wherein the modulus length vector is mapped to the amplitude of the first quantum state; Calculating the argument of each element in the normalized complex vector to be encoded to obtain an argument vector; Construct a second quantum circuit containing n qubits according to the argument vector, where the second quantum circuit includes two operation units connected in sequence, and the operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; n The operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; Executing the first quantum circuit and the second quantum circuit to output a target quantum state, wherein the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state; Wherein, a multi-controlled phase shift gate is created in each operation unit, the multi-controlled phase shift gate is an n-bit quantum gate, the multi-controlled phase shift gate acts on the highest-bit qubit, and the multi-controlled phase shift gate has n - 1 controlled bits, the sorting of each argument in the argument vector corresponds one by one to the serial number of each operation unit, and the parameter carried by each multi-controlled phase shift gate is the corresponding argument in the argument vector.

2. The method according to claim 1, wherein The constructing a second quantum circuit including n qubits according to the argument vector further includes: Initializing n qubits; the n qubits are sorted in order from the low bit to the high bit; Divide the initialized n qubits into 2 n operation units; Take 2 n Number the 2 operation units as 0, 1, ……, 2 n -2, 2 n -1 in sequence; Converting the serial number of each operation unit into an n-bit binary string, wherein the characters in the n-bit binary string correspond one by one to the sorting of the qubits from the low bit to the high bit in order from the low bit to the high bit; Allocating each computational basis state in the first quantum state in sequence according to the serial number of each operation unit, so that each operation unit has a target basis state corresponding to the n-bit binary string; Creating a first operation column and a second operation column in each operation unit, wherein the multi-controlled phase shift gate is located between the first operation column and the second operation column, the first operation column includes n first quantum gates, the n quantum gates are correspondingly arranged on the n qubits, the second operation column is set to be the same as the first operation column, the first quantum gate is set to be an X gate or an I gate, the first operation column is used to convert the target basis state of the current operation unit into an all |1> state, and perform an operation on the current multi-controlled phase shift gate to realize adding the current argument to the amplitude of the corresponding first quantum state, and the second operation column is used to make the computational basis states in the quantum states output by each operation unit consistent with the computational basis states in the first quantum state.

3. The method according to claim 2, wherein The creating a first operation column and a second operation column in each operation unit includes: Performing a unitary operation on the n-bit binary string to convert the target basis state corresponding to the current operation unit into an all |1> state; wherein, Judging whether the current character in the n-bit binary string corresponding to the current operation unit is equal to "0", if the current character is equal to "0", setting the first quantum gate on the target qubit corresponding to the current character to be an X gate, if the current character is not equal to "0", then setting the first quantum gate to be an I gate; Traversing all the characters in the n-bit binary string in sequence, so that the target basis state corresponding to the current operation unit is converted into an all |1> state, so as to complete creating the first operation column before the multi-controlled phase shift gate; Creating a second operation column after the multi-controlled phase shift gate.

4. The method according to claim 3, characterized in that, The constructing of the second quantum circuit including n qubits according to the argument vector further includes: Traversing in sequence according to the serial number of each operation unit, so as to complete the creation of a multi-controlled phase shift gate, a first operation column, and a second operation column in each operation unit, thereby realizing adding each argument in the argument vector to the amplitude of the first quantum state correspondingly.

5. The method according to claim 4, wherein The constructing of the second quantum circuit including n qubits according to the argument vector further includes: Arbitrarily arranging the execution order before and after of each operation unit in the second quantum circuit; Adjusting the execution order before and after of each operation unit in the second quantum circuit, so as to cancel two adjacent X gates on the same qubit, thereby obtaining an optimized second quantum circuit with the fewest quantum gates.

6. The method according to claim 5, wherein Executing the first quantum circuit and the second quantum circuit to output a target quantum state, including: Connecting the first quantum circuit and the optimized second quantum circuit in sequence before and after to obtain a combined quantum circuit; Executing the combined quantum circuit to output a target quantum state.

7. The method according to claim 1, characterized in that, The parameterized quantum gates in the first quantum circuit include one or more of the following: RX gate, RY gate, RZ gate, multi-qubit RX gate, multi-qubit RY gate, and multi-qubit RZ gate.

8. A quantum state amplitude encoding device, characterized in that, Including: A normalization module, which is used to perform normalization processing on the complex vector to be encoded to obtain a normalized complex vector to be encoded, and the normalized complex vector to be encoded includes 2 n elements, where n is a positive integer; A modulus vector module, which is used to calculate the modulus of each element in the normalized complex vector to be encoded to obtain a modulus vector; A first construction module, which is used to construct a first quantum circuit including n qubits according to the modulus vector, calculate the parameters of the parameterized quantum gates in the first quantum circuit by using the real vector amplitude encoding algorithm, obtain a first quantum circuit with fixed parameter values, and output a first quantum state evolved by the first quantum circuit, wherein the modulus vector is mapped to the amplitude of the first quantum state; An argument vector module, which is used to calculate the argument of each element in the normalized complex vector to be encoded to obtain an argument vector; A second building block, which is used to construct a second quantum circuit including n qubits according to an argument vector, where the second quantum circuit includes two operation units connected in sequence, and the operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; n operation units, and the operation unit is used to add each argument in the argument vector to the amplitude of the first quantum state correspondingly; An output module, which is used to execute the first quantum circuit and the second quantum circuit to output a target quantum state, wherein the normalized complex vector to be encoded is mapped to the amplitude of the target quantum state; Wherein, a multi-controlled phase shift gate is created in each operation unit, wherein the multi-controlled phase shift gate is an n-bit quantum gate, the multi-controlled phase shift gate acts on the highest-bit qubit, and the multi-controlled phase shift gate has n - 1 control bits, the sorting of each argument in the argument vector corresponds one by one to the serial number of each operation unit, and the parameter carried by each multi-controlled phase shift gate is the corresponding argument in the argument vector.

9. An electronic device, characterized in that, The electronic device includes: a processor and a memory storing computer program instructions; when the electronic device executes the computer program instructions, the method described in any one of claims 1-7 is implemented.

10. A computer-readable storage medium, characterized in that, Computer program instructions are stored on the computer-readable storage medium, and when the computer program instructions are executed by a processor, the method described in any one of claims 1-7 is implemented.

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