Chip efficiency optimization method and system, electronic equipment and storage medium

Abstract

The invention relates to the technical field of chip optimization, in particular to a chip efficiency optimization method and system, electronic equipment and a storage medium, and the method comprises the steps: dividing an MAC structure of a target chip into a plurality of MAC groups, and splitting target image data into image sub-data corresponding to at least one image input depth; wherein the number of the image sub-data corresponding to each image input depth is the same as the number of the MAC groups and the image sub-data and the MAC groups are in one-to-one correspondence; and sequentially sending the image sub-data corresponding to each image input depth to a plurality of MAC groups for processing so as to realize efficiency optimization of the target chip. According to the invention, the function that each MAC group independently processes the corresponding image sub-data is realized, and the degree of parallelism of calculation is increased, so that the processing efficiency is improved, the waiting time of data reading and processing is reduced, the delay is effectively reduced, and the overall performance is improved.

Description

Background Art

[0002] With the rapid development of artificial intelligence, the bottlenecks of existing computers with von Neumann architecture systems are gradually emerging. At present, the hardware running neural networks is roughly divided into two categories: deep learning accelerator chips and neuromorphic chips. In addition, Tsinghua University has developed hybrid brain-like chips that support heterogeneous fusion networks for general artificial intelligence. At present, most accelerators use a storage-computing separation architecture, that is, the traditional von Neumann architecture.

[0003] This type of chip uses increased transistor density to improve energy efficiency, such as the TPU from the first generation of 45nm to the fourth generation of 7nm, and on the other hand, uses near-memory design and domain-specific architecture design (DSA) to reduce power consumption. Due to the use of external storage, data requires a lot of movement between the computing unit and the storage unit, and read and write operations. The access power consumption caused by moving data will cause computing delays due to reading and writing. On the other hand, when the number of computing units gradually increases, the neural network needs to be finely split. Although the von Neumann architecture accelerator chip also has a multi-core architecture, most of them are serial processing from an algorithm perspective. The "von Neumann" based on the separation of storage and computing has a simple structure and is easy to use for high-speed computing, and the mapping method is simple, and resources are scheduled according to the time complexity of the task.

[0004] Due to the high degree of parallelism of deep neural networks, some deep learning accelerator chips are also beginning to adopt decentralized architectures. Simba, for example, is decentralized at the chip level and uses storage and computing separation inside the chip. Graphcore's IPU distributed storage and computing integrated architecture reduces the storage wall effect through a decentralized architecture.

[0005] For neuromorphic chips of neural networks, the number of MACs can often be divided into the corresponding weight part and the data parameter part. The number of MACs is determined by the product of the two. Figure 2 As shown: the MAC array has 32 MACs in the corresponding weight part and 4 MACs in the corresponding data IA part, totaling 128 MACs.

[0006] Under a fixed read and write access operation bandwidth, assuming it is 32B / clc, for the neural network parallel computing pipeline method, 32B of weight data is read in for each clock and calculated once at the same time. When the number of MACs corresponding to the number of weights is greater than 32, for example 64, it is necessary to read the weights twice and calculate once. At this time, the read-calculation ratio of the pipeline system is 2:1, and the computing efficiency is not higher than 50%. When it is 128, the calculation ratio is 4:1. This will reduce the proportion of the chip's computing time to the total time, and the computing efficiency is no more than 25%. At this time, the computing efficiency of the chip is low. Therefore, to ensure the efficiency of the pipeline system, when designing the number of MACs, one side is used as the corresponding number of pipeline data equal to the access bandwidth.

[0007] by Figure 3 In the pipeline system shown, it is necessary to read in 4 image data and then read in the bias data for calculation. If the input depth of the weight is 32, 32 clocks are required for calculation under 1x1 convolution. It takes 4 clocks to read in the image data, 16 clocks to load 128 4B bias data, and 16 clocks to write back 128 calculation results. Therefore, the calculation efficiency is 32 / (4+16+32+16)=47%. If it is for a 3x3 convolution kernel, the calculation efficiency of the pipeline is 32×3×3 / (4+16+32×3×3+16)=88.89%. In addition, there are a large number of 1x1 convolutions inside the artificial neural network, so there are problems such as low processing efficiency, long waiting time for data reading and processing, high latency, and poor overall performance.

[0008] Therefore, it is urgent to provide a technical solution to solve the above problems. Summary of the invention

[0009] In order to solve the above technical problems, the present invention provides a chip efficiency optimization method, system, electronic device and storage medium.

[0010] In a first aspect, the present invention provides a chip efficiency optimization method, the technical solution of the method is as follows:

[0011] Divide the MAC structure of the target chip into multiple MAC groups, and split the target image data into image sub-data corresponding to at least one image input depth; wherein the number of image sub-data corresponding to each image input depth is the same as the number of MAC groups and corresponds one to one;

[0012] The image sub-data corresponding to each image input depth are sent to a plurality of MAC groups in sequence for processing, so as to optimize the efficiency of the target chip.

[0013] The beneficial effects of a chip efficiency optimization method of the present invention are as follows:

[0014] The method of the present invention realizes the function of each MAC group independently processing the corresponding image sub-data, increases the parallelism of calculation, thereby improving the processing efficiency, and also reduces the waiting time for data reading and processing, effectively reduces the delay, and improves the overall performance.

[0015] Based on the above solution, a chip efficiency optimization method of the present invention can also be improved as follows.

[0016] In an optional manner, each image sub-data is: image data used for convolution operation.

[0017] In the above optional manner, it is clarified that the image sub-data is specifically used for convolution operation, thereby optimizing the utilization of computing resources and making the calculation of the MAC group more targeted and efficient.

[0018] In an optional manner, the processing process of any MAC group on any image sub-data is as follows:

[0019] Any MAC group multiplies any image sub-data by preset weight data corresponding to any image sub-data to obtain a processing result.

[0020] In the above optional manner, by multiplying the image sub-data with the preset weight data, the operation steps of the MAC group are specifically defined, which ensures the accuracy and consistency of the calculation process and improves the accuracy and reliability of the operation.

[0021] In an optional manner, it also includes: storing the processing result of any MAC group processing any image sub-data in an accumulation register.

[0022] In the above optional method, by storing the processing results in the accumulator register, the preservation of the intermediate results and the continuity of subsequent calculations are ensured, the risk of data loss and repeated calculations is reduced, and the stability and computing efficiency of the system are improved.

[0023] In a second aspect, the present invention provides a chip efficiency optimization system, the technical solution of which is as follows:

[0024] The chip efficiency optimization system comprises: a division module and a processing module;

[0025] The division module is used to: divide the MAC structure of the target chip into multiple MAC groups, and split the target image data into image sub-data corresponding to at least one image input depth; wherein the number of image sub-data corresponding to each image input depth is the same as the number of MAC groups and corresponds one to one;

[0026] The processing module is used to send the image sub-data corresponding to each image input depth to multiple MAC groups in sequence for processing, so as to optimize the efficiency of the target chip.

[0027] The beneficial effects of a chip efficiency optimization system of the present invention are as follows:

[0028] The system of the present invention realizes the function of each MAC group independently processing the corresponding image sub-data, increases the parallelism of calculation, thereby improving the processing efficiency, and also reduces the waiting time for data reading and processing, effectively reduces the delay, and improves the overall performance.

[0029] Based on the above solution, the chip efficiency optimization system of the present invention can also be improved as follows.

[0030] In an optional manner, each image sub-data is: image data used for convolution operation.

[0031] In the above optional manner, it is clarified that the image sub-data is specifically used for convolution operation, thereby optimizing the utilization of computing resources and making the calculation of the MAC group more targeted and efficient.

[0032] In an optional manner, the processing module is specifically used to:

[0033] Any MAC group multiplies any image sub-data by the preset weight data corresponding to the any image sub-data to obtain a processing result.

[0034] In the above optional manner, by multiplying the image sub-data with the preset weight data, the operation steps of the MAC group are specifically defined, which ensures the accuracy and consistency of the calculation process and improves the accuracy and reliability of the operation.

[0035] In an optional manner, a storage module is also included:

[0036] The storage module is used to store the processing result of any MAC group processing any image sub-data in an accumulation register.

[0037] In the above optional method, by storing the processing results in the accumulator register, the preservation of the intermediate results and the continuity of subsequent calculations are ensured, the risk of data loss and repeated calculations is reduced, and the stability and computing efficiency of the system are improved.

[0038] In a third aspect, a technical solution of an electronic device of the present invention is as follows:

[0039] The invention comprises a memory, a processor and a program stored in the memory and running on the processor. When the processor executes the program, the steps of the chip efficiency optimization method of the present invention are implemented.

[0040] In a fourth aspect, the present invention provides a computer-readable storage medium having the following technical solution:

[0041] Instructions are stored in the computer-readable storage medium. When the computer-readable storage medium reads the instructions, the computer-readable storage medium executes the steps of the chip efficiency optimization method of the present invention.

[0042] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present invention. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings. In the accompanying drawings:

[0044] Figure 1 A schematic diagram of a flow chart of an embodiment of a chip efficiency optimization method of the present invention;

[0045] Figure 2 Design a schematic diagram for the number of MAC units inside a single computing core;

[0046] Figure 3 It is a schematic diagram of the existing water flow system;

[0047] Figure 4 Schematic diagram of the MAC unit structure design;

[0048] Figure 5 It is a schematic diagram of the cyclic calculation process;

[0049] Figure 6 A schematic diagram of the cycle calculation timing;

[0050] Figure 7 A schematic diagram of the structure of an embodiment of a chip efficiency optimization system of the present invention;

[0051] Figure 8 The figure is a schematic structural diagram of an embodiment of an electronic device of the present invention. DETAILED DESCRIPTION

[0052] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0053] Figure 1FIG. 1 is a flow chart showing an embodiment of a chip efficiency optimization method provided by the present invention, wherein the method is executed by a controller. Figure 1 As shown, the following steps are included:

[0054] S1. Divide the MAC structure of the target chip into multiple MAC groups, and split the target image data into image sub-data corresponding to at least one image input depth; wherein the number of image sub-data corresponding to each image input depth is the same as the number of MAC groups and corresponds one to one. In S1:

[0055] 1) The MAC group contains multiple MAC units. The MAC unit refers to the basic computing unit divided out of the MAC structure (multiplier-adder structure). Each MAC unit can independently perform multiplication and addition operations. The MAC group is responsible for performing multiplication and addition operations on the image sub-data and the preset weight data to obtain the processing result. By dividing the MAC structure into multiple MAC groups, each MAC group independently and parallelly processes different image sub-data, thereby improving the parallelism and processing efficiency of the calculation.

[0056] 2) If Figure 4 As shown, a MAC unit (multiplier-adder) contains a gate and multiple registers. During the cyclic calculation process, the gate can dynamically select the intermediate result stored in any register according to the control signal, and feed the intermediate result back to the adder for accumulation. Through the control of the gate, the multiplier-adder can flexibly manage multiple accumulated data streams to achieve complex multi-step calculations, such as in scenarios that require repeated iterations such as convolution operations, recursive calculations, or matrix multiplications, thereby optimizing the accumulation process of the MAC unit and improving the calculation efficiency. At the same time, it ensures that at each calculation moment, different MAC units can simultaneously process different data pairs (image sub-data and preset weight data), and load the preset weight data of the next depth while calculating to maximize the use of computing resources.

[0057] 3) Target image data refers to the original image data that needs to be convolved or otherwise processed. During the cyclic calculation process, the target image data will be read in and directly split into multiple image sub-data, and then assigned to different MAC groups for parallel processing, providing an input data source for subsequent calculations. Parallel processing can improve computing efficiency and meet the needs of high-performance computing.

[0058] 4) Image input depth refers to the depth information of the target image data, indicating how many channels each image pixel consists of. The image input depth determines how many image sub-data the target image data needs to be split into. The number of image sub-data corresponding to each image input depth is the same as the number of MAC groups, and they correspond one to one, ensuring that each MAC group processes one image sub-data in each clock cycle.

[0059] 5) Image sub-data refers to the data block after the target image data is split according to the image input depth. Each image sub-data corresponds to a MAC group and is processed by the corresponding MAC group. Image sub-data is the basic unit of MAC group processing. Each MAC group receives an image sub-data in each clock cycle, and performs multiplication and addition operations with the preset weight data to generate intermediate results, thereby realizing parallel processing of target image data and improving overall computing efficiency.

[0060] Specifically, the controller divides the MAC structure of the target chip into a plurality of MAC groups, and splits the target image data into image sub-data corresponding to at least one image input depth.

[0061] S2. Send the image sub-data corresponding to each image input depth to multiple MAC groups for processing in sequence to optimize the efficiency of the target chip.

[0062] Specifically, the controller further sends the image sub-data corresponding to each image input depth to multiple MAC groups for processing in sequence to achieve efficiency optimization of the target chip.

[0063] The technical solution of this embodiment realizes the function of each MAC group independently processing the corresponding image sub-data, increases the parallelism of calculation, thereby improving processing efficiency, and also reduces the waiting time for data reading and processing, effectively reduces latency, and improves overall performance.

[0064] In an optional manner, each image sub-data is: image data used for convolution operation;

[0065] The processing process of any MAC group on any image sub-data is as follows: any MAC group multiplies any image sub-data by the preset weight data corresponding to the any image sub-data to obtain a processing result.

[0066] It should be noted that the target image data is split into at least one image sub-data corresponding to each image input depth. Each image sub-data corresponds to an area, and multiple areas together cover the entire target image data. Each image sub-data is composed of a set of pixel values, and the pixel values ​​are organized in the form of a matrix, such as an n×n pixel matrix, where n is the size of an area in the target image data corresponding to each image sub-data. The size is a predetermined or defined size, and further, the size is the width and height of the image sub-data. For example: if n=3 is specified, then each image sub-data is a 3×3 matrix containing 9 pixel values; if n=5 is specified, then each image sub-data is a 5×5 matrix containing 25 pixel values.

[0067] In this embodiment, the image sub-data is a 4×4 matrix, each matrix contains 16 pixel values, and each pixel value occupies 2 bytes. The image sub-data is divided into four image data: X0, X1, X2, and X3.

[0068] like Figure 5 As shown, first, four registers are used for image reading. At a rate of 32 bytes / clock, four clock cycles are used to read four groups of 32 bytes (4×32B) of image data, X0, X1, X2, and X3, respectively. Each image data is assigned to four MAC groups, each MAC group contains 32 different MAC units, and further:

[0069] X0 is assigned to the first group of 32 different MAC units.

[0070] X1 is distributed to the second group of 32 different MAC units.

[0071] X2 is assigned to a third group of 32 different MAC units.

[0072] X3 is assigned to the fourth group of 32 different MAC units.

[0073] Therefore, the four image data (X0, X1, X2, X3) in the image sub-data are read and distributed to the four MAC groups within four clock cycles before the calculation starts.

[0074] After reading in the 4 image data (X0, X1, X2, X3) in the image sub-data, a convolution calculation is performed, and within each clock cycle, the MAC group can read the currently required preset weight data. For example: in the first clock cycle, the 4 MAC groups read the initial preset weight data (such as the 1st group reads the preset weight data W0, the 2nd group reads the preset weight data W1, the 3rd group reads the preset weight data W2, and the 4th group reads the preset weight data W3). While calculating, the preset weight data of the next preset weight data depth will be preloaded. In each subsequent clock cycle, the preset weight data will be updated as the data is cyclically shifted, and the preset weight data of the next preset weight data depth will continue to be preloaded.

[0075] Therefore, the preset weight data is read at the beginning of each clock cycle, and the preset weight data of the next preset weight data depth is preloaded while the convolution calculation is being performed. Figure 6 As shown, the specific process is as follows:

[0076] First clock cycle:

[0077] The first MAC group performs the multiplication and addition calculation of X0 and W0.

[0078] The second MAC group performs the multiplication and addition calculation of X1 and W1.

[0079] The third MAC group performs the multiplication and addition calculation of X2 and W2.

[0080] The fourth MAC group performs the multiplication and addition calculation of X3 and W3.

[0081] In the next clock cycle, the image data and the preset weight data are cyclically shifted.

[0082] MAC group 1 will process X1 and W1 (ie the data has been shifted).

[0083] MAC Group 2 will handle X2 and W2.

[0084] MAC group 3 will handle X3 and W3.

[0085] The 4th MAC group will process X0 and W0 (looping back to the original data).

[0086] The circular shift operation will continue for multiple clock cycles until all combinations of image data X and preset weight data W have been processed. The specific circular calculation is as follows:

[0087] Second clock cycle:

[0088] The first MAC group performs the multiplication and addition calculation of X3 and W0.

[0089] The second MAC group performs the multiplication and addition calculation of X0 and W1.

[0090] The third MAC group performs the multiplication and addition calculation of X1 and W2.

[0091] The fourth MAC group performs the multiplication and addition calculation of X2 and W3.

[0092] While calculating, the preset weight data of the next preset weight data depth of the second group is loaded.

[0093] The third clock cycle:

[0094] The first MAC group performs the multiplication and addition calculation of X2 and W0.

[0095] The second MAC group performs the multiplication and addition calculation of X3 and W1.

[0096] The third MAC group performs the multiplication and addition calculation of X0 and W2.

[0097] The fourth MAC group performs the multiplication and addition calculation of X1 and W3.

[0098] While calculating, the preset weight data of the next preset weight data depth of the 3rd group is loaded.

[0099] Fourth clock cycle:

[0100] The first MAC group performs the multiplication and addition calculation of X1 and W0.

[0101] The second MAC group performs the multiplication and addition calculation of X3 and W1.

[0102] The third MAC group performs the multiplication and addition calculation of X2 and W2.

[0103] The fourth MAC group performs the multiplication and addition calculation of X0 and W3.

[0104] While calculating, the preset weight data of the next preset weight data depth of the 4th group is loaded.

[0105] Every 4 clock cycles (ie, one cycle), the 4 MAC groups are updated with one depth on the image input depth, and this cycle continues until the image input depth is completely used.

[0106] In an optional manner, it also includes: storing a processing result after any MAC group processes any image sub-data in an accumulation register.

[0107] It should be noted that in the loop calculation, the calculation results of each MAC group will be continuously accumulated in the accumulation register until the calculation of all image input depths is completed, and finally the preliminary convolution calculation result is obtained. For example, the calculation result of the first group of MAC groups will be added to the current value in the accumulation register in each clock cycle. After the accumulation is completed, the bias data (B) will be read and added to the preliminary convolution calculation result of the accumulation register to obtain the target convolution calculation result. The clock cycle of the bias data reading time depends on the bit width of the bias data.

[0108] In this embodiment, 128 different offset data are read, each offset data is 4 bytes, and a total of 16 clock cycles are required. The loading of the offset data is related to the chip design. The bit width of the offset data can be 3 bytes or 2 bytes. Assuming that the bit width of the offset data is 3 bytes, 12 clock cycles are required.

[0109] Assuming that the bias data is 128 different biases and the bit width of each bias is 2 bytes, 8 clock cycles are required; if the bit width of each bias is 3 bytes, 12 clock cycles are required.

[0110] Therefore, the bias data is read after the accumulator register completes the depth direction calculation of all image inputs and is added to the preliminary convolution calculation result to obtain the target convolution calculation result.

[0111] It should be noted that the computational efficiency can also be verified by calculating the efficiency of the convolution primitives based on the input depth and convolution kernel size:

[0112] The efficiency of convolution primitive utilization under 1×1 convolution kernel is:

[0113] 32×4 / (4+16+32×4+16×4)=60.3%;

[0114] The efficiency of convolution primitives under 3×3 convolution kernel is:

[0115] 32×4×9 / (4+16+32×9×4+16×4)=93.2%.

[0116] Compared with the existing computing efficiency in the background technology, the computing efficiency is improved by 27.7% and 5.6% respectively.

[0117] Figure 7 FIG. 2 is a schematic diagram showing a structure of an embodiment of a chip efficiency optimization system 200 provided by the present invention. Figure 7 As shown, the system 200 includes: a partitioning module 210 and a processing module 220 .

[0118] The division module 210 is used to: divide the MAC structure of the target chip into multiple MAC groups, and split the target image data into image sub-data corresponding to at least one image input depth; wherein the number of image sub-data corresponding to each image input depth is the same as the number of MAC groups and corresponds one to one;

[0119] The processing module 220 is used to send the image sub-data corresponding to each image input depth to multiple MAC groups in sequence for processing, so as to optimize the efficiency of the target chip.

[0120] In an optional manner, each image sub-data is: image data used for convolution operation.

[0121] In an optional manner, the processing module is specifically used for:

[0122] Any MAC group multiplies any image sub-data by the preset weight data corresponding to any image sub-data to obtain a processing result.

[0123] In an optional manner, a storage module is also included:

[0124] The storage module is used to store the processing result after any MAC group processes any image sub-data in the accumulation register.

[0125] The technical solution of this embodiment realizes the function of each MAC group independently processing the corresponding image sub-data, increases the parallelism of calculation, thereby improving processing efficiency, and also reduces the waiting time for data reading and processing, effectively reduces latency, and improves overall performance.

[0126] The above parameters and steps for each module to implement corresponding functions in the chip efficiency optimization system 200 of this embodiment can refer to the parameters and steps in the embodiment of the chip efficiency optimization method above, and will not be repeated here.

[0127] like Figure 8 As shown, an electronic device 300 according to an embodiment of the present invention includes a processor 320, the processor 320 is coupled to a memory 310, and the memory 310 stores at least one computer program 330, and the at least one computer program 330 is loaded and executed by the processor 320, so that the electronic device 300 implements any of the above chip efficiency optimization methods, specifically:

[0128] The electronic device 300 may have relatively large differences due to different configurations or performances, and may include one or more processors 320 (Central Processing Units, CPU) and one or more memories 310, wherein the one or more memories 310 store at least one computer program 330, and the at least one computer program 330 is loaded and executed by the one or more processors 320, so that the electronic device 300 implements any chip efficiency optimization method provided in the above embodiments. Of course, the electronic device 300 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the electronic device 300 may also include other components for implementing device functions, which will not be repeated here.

[0129] A computer-readable storage medium according to an embodiment of the present invention stores at least one computer program, and the at least one computer program is loaded and executed by a processor so that a computer implements any of the above chip efficiency optimization methods.

[0130] Optionally, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0131] In an exemplary embodiment, a computer program product or a computer program is also provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device performs any of the above chip efficiency optimization methods.

[0132] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects and represent the definition of a specific order or sequence. The order of use of similar objects can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than the order shown or described.

[0133] Those skilled in the art know that the present invention can be implemented as a system, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: it can be complete hardware, it can be complete software (including firmware, resident software, microcode, etc.), or it can be a combination of hardware and software, which is generally referred to as "circuit", "module" or "system" herein. In addition, in some embodiments, the present invention can also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium contains computer-readable program code.

[0134] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, device, or device.

[0135] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A chip efficiency optimization method, characterized in that: include: Divide the MAC structure of the target chip into multiple MAC groups, and split the target image data into image sub-data corresponding to at least one image input depth; wherein the number of image sub-data corresponding to each image input depth is the same as the number of MAC groups and corresponds one to one; The image sub-data corresponding to each image input depth are sent to a plurality of MAC groups in sequence for processing, so as to optimize the efficiency of the target chip.

2. The chip efficiency optimization method according to claim 1, characterized in that: Each image sub-data is: image data used for convolution operation.

3. The chip efficiency optimization method according to claim 1, characterized in that: The processing process of any MAC group for any image sub-data is as follows: Any MAC group multiplies any image sub-data by preset weight data corresponding to any image sub-data to obtain a processing result.

4. The chip efficiency optimization method according to claim 3, characterized in that: Also includes: The processing result after any one of the MAC groups processes any one of the image sub-data is stored in an accumulation register.

5. A chip efficiency optimization system, characterized in that: include: Divide modules and process modules; The division module is used to: divide the MAC structure of the target chip into multiple MAC groups, and split the target image data into image sub-data corresponding to at least one image input depth; wherein the number of image sub-data corresponding to each image input depth is the same as the number of MAC groups and corresponds one to one; The processing module is used to send the image sub-data corresponding to each image input depth to multiple MAC groups in sequence for processing, so as to optimize the efficiency of the target chip.

6. The chip efficiency optimization system according to claim 5, characterized in that: Each image sub-data is: image data used for convolution operation.

7. The chip efficiency optimization system according to claim 5, characterized in that: The processing module is specifically used for: Any MAC group multiplies any image sub-data by the preset weight data corresponding to the any image sub-data to obtain a processing result.

8. The chip efficiency optimization system according to claim 7, characterized in that: Also includes storage modules: The storage module is used to store the processing result of any MAC group processing any image sub-data in an accumulation register.

9. An electronic device, characterized in that: The electronic device includes a processor, the processor is coupled to a memory, the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor so that the electronic device implements the chip efficiency optimization method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by a processor so that the computer-readable storage medium implements the chip efficiency optimization method according to any one of claims 1 to 4.

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