Clock detection circuit, clock detection method and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a clock detection circuit, a clock detection method and a display panel, and the clock detection circuit comprises an anomaly detection module which is used for carrying out the anomaly detection of a first clock signal and a second clock signal, and outputting a corresponding anomaly detection result; the result identification module is used for identifying the abnormal detection result and outputting a target identification signal to a corresponding memory, so that a time schedule controller performs single-end driving or double-end driving on a display panel according to the target identification signal in all the memories; according to the invention, when it is detected that the clock signal at any side of any row is abnormal, the double-end driving mode of all rows in the display panel can be changed into the single-end driving mode at the same time in time, so that brightness abnormity between a normal row and an abnormal row is avoided; therefore, the problem of improving the picture display effect under the condition that the clock signal of the double-end drive is abnormal is solved.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and in particular relates to a clock detection circuit, a clock detection method and a display panel. Background Art

[0002] At present, the competition for automotive products in the panel industry is becoming increasingly fierce. Only high resolution and high PPI (Pixels Per Inch, pixel density unit) can make products competitive. The environmental experimental requirements of automotive products themselves are relatively high, so most of the automotive products in the panel industry are driven by gate IC (gate chip), which has a better charging effect but is relatively expensive. The stability of GDL driven products is slightly inferior to gate IC, but the cost is lower; therefore, for high-resolution automotive products, the dual-end drive of GDL technology can improve the pixel charging efficiency and make the picture quality better.

[0003] However, in the display panel using GDL technology and dual-end drive, due to various factors, the clock signal of some pixel rows has unilateral abnormality, so that the abnormal pixel row changes from dual-end drive to single-end drive, while other pixel rows are normal dual-end drive. In terms of macro performance, there is a difference in charging effect between normal rows and abnormal rows, and there are changes in brightness, and evenly spaced horizontal stripes can be seen.

[0004] Therefore, how to improve the picture display effect when the double-ended driven clock signal is abnormal is a problem that the current baseband needs to solve. Summary of the invention

[0005] The present application provides a clock detection circuit, a clock detection method and a display panel, which solve the problem of improving the picture display effect when an abnormality occurs in a double-ended driven clock signal.

[0006] In a first aspect, the present application provides a clock detection circuit, which is applied to a dual-end driven display panel, and the clock detection circuit includes: an abnormality detection module, wherein the first input end of the abnormality detection module is connected to the first clock signal output end, and the second input end of the abnormality detection module is connected to the second clock signal output end, and is used to perform abnormality detection on the first clock signal and the second clock signal, and output corresponding abnormality detection results; a result recognition module, wherein the input end of the result recognition module is connected to the output end of the abnormality detection module, the first output end of the result recognition module is connected to the first memory, the second output end of the result recognition module is connected to the second memory, and the third output end of the result recognition module is connected to the third memory, and is used to identify the abnormality detection result, output a target recognition signal to the corresponding memory, so that the timing controller performs single-end drive or dual-end drive on the display panel according to the target recognition signals in all memories.

[0007] Optionally, the abnormality detection module includes: a first transistor, a control end of the first transistor is connected to the first clock signal output end, and a first end of the first transistor is connected to the second clock signal output end; a second transistor, a control end of the second transistor is connected to the control end of the first transistor, and a first end of the second transistor is connected to the second end of the first transistor; a third transistor, a control end of the third transistor is connected to the first end of the first transistor, a first end of the third transistor is connected to the first end of the second transistor, and a second end of the third transistor is connected to the control end of the second transistor; a fourth transistor, a control end of the fourth transistor is connected to the second end of the second transistor, a first end of the fourth transistor is connected to the first end of the third transistor, and a second end of the fourth transistor is connected to the second end of the third transistor; an inverter, an input end of the inverter is connected to the control end of the third transistor, and an output end of the inverter is connected to the control end of the fourth transistor; wherein the second end of the first transistor is the output end of the abnormality detection module.

[0008] Optionally, the turn-on voltages of the first transistor and the second transistor are opposite, the turn-on voltages of the third transistor and the fourth transistor are opposite, and the turn-on voltages of the first transistor and the third transistor are the same.

[0009] Optionally, the abnormality detection module also includes: a first resistor, a first end of the first resistor is connected to the second end of the first transistor, and the second end of the first resistor is grounded; a diode, an anode of the diode is connected to the first end of the first resistor; and a capacitor, a first end of the capacitor is connected to the cathode of the diode, and the second end of the capacitor is grounded.

[0010] Optionally, the result identification module includes: a fifth transistor, a control end of the fifth transistor is connected to the output end of the abnormality detection module, and a first end of the fifth transistor is connected to a power supply end; a second resistor, a first end of the second resistor is connected to the second end of the fifth transistor, and a second end of the second resistor is grounded; wherein the second end of the fifth transistor is the first output end of the result identification module.

[0011] Optionally, the result identification module also includes: a comparator, a first input end of the comparator is connected to the output end of the abnormality detection module, and a second input end of the comparator is connected to the power supply end; a sixth transistor, a control end of the sixth transistor is connected to the output end of the comparator, and a first end of the sixth transistor is connected to the power supply end; a seventh transistor, a control end of the seventh transistor is connected to the second end of the fifth transistor, and a first end of the seventh transistor is connected to the second end of the sixth transistor; a third resistor, a first end of the third resistor is connected to the second end of the seventh transistor, and a second end of the third resistor is grounded; wherein the second end of the seventh transistor is the second output end of the result identification module.

[0012] Optionally, the result identification module also includes: an eighth transistor, the control end of the eighth transistor is connected to the output end of the comparator, and the first end of the eighth transistor is connected to the power supply end; a fourth resistor, the first end of the fourth resistor is connected to the second end of the eighth transistor, and the second end of the fourth resistor is grounded; wherein the second end of the eighth transistor is the third output end of the result identification module.

[0013] In a second aspect, the present application provides a clock detection method, which is applied to a clock detection circuit, and the clock detection method includes: performing abnormal detection on a first clock signal and a second clock signal corresponding to each pixel row to obtain a corresponding abnormal detection result; wherein the abnormal detection result includes a first detection result that both the first clock signal and the second clock signal are normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal; identifying the abnormal detection result, outputting a target identification signal to a corresponding memory, so that a timing controller performs single-ended or double-ended driving on a display panel according to the target identification signal in all memories; wherein, if it is the first detection result, the target identification signal is output to the first memory, if it is the second detection result, the target identification signal is output to the second memory, and if it is the third detection result, the target identification signal is output to the third memory.

[0014] In a third aspect, the present application provides a display panel, the display panel comprising: a clock generator, configured to output N first clock signals and N second clock signals; a clock detection circuit, the clock detection circuit being connected to a first clock signal output terminal and a second clock signal output terminal of the clock generator, respectively, and configured to perform abnormality detection on the first clock signal and the second clock signal; a first memory, connected to a first output terminal of each clock detection circuit, configured to receive a target identification signal output by each clock detection circuit; a second memory, connected to a second output terminal of each clock detection circuit, configured to receive a target identification signal output by each clock detection circuit; a third memory, connected to a third output terminal of each clock detection circuit, configured to receive a target identification signal output by each clock detection circuit; M cascaded first G A gate drive circuit, wherein each first GDL circuit is respectively connected to the first clock signal output terminal of the clock generator and the first end of the corresponding scan line in the display panel, and is used for outputting a corresponding gate drive signal under the action of the first clock signal; M cascaded second GDL circuits, wherein each second GDL circuit is respectively connected to the second clock signal output terminal of the clock generator and the second end of the corresponding scan line in the display panel, and is used for outputting a corresponding gate drive signal under the action of the second clock signal; a timing controller, wherein the timing controller is respectively connected to the first memory, the second memory, the third memory, the first GDL circuit and the second GDL circuit, and is used for controlling the first GDL circuit and the second GDL circuit to be turned on or off according to target identification signals in all memories.

[0015] Optionally, the first GDL circuit and the second GDL circuit are controlled to be turned on or off according to the target identification signals in all memories, including: when there are N target identification signals in the first memory, the first GDL circuit and the second GDL circuit are turned on at the same time; when there is at least one target identification signal in the second memory, the second GDL circuit is turned off; when there is at least one target identification signal in the third memory, the first GDL circuit is turned off.

[0016] The technical solution provided by this application has at least the following beneficial effects: The present application performs abnormality detection on the clock signals at both ends of the display panel through an abnormality detection module, and classifies and stores the abnormality detection results into different memories through a result recognition module, so that the timing controller performs single-end drive or double-end drive on the display panel according to the target recognition signals in all memories; therefore, when the present application detects that an abnormality occurs in the clock signal on any side of any row, the double-end drive mode of all rows in the display panel can be changed to a single-ended drive mode in a timely manner, thereby avoiding brightness abnormalities between normal rows and abnormal rows, thereby solving the problem of improving the picture display effect when an abnormality occurs in the clock signal of the double-end drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0018] Figure 1 Shown is a structural schematic diagram of a clock detection circuit provided in an embodiment of the present application.

[0019] Figure 2 Shown is a circuit diagram of a clock detection circuit provided in an embodiment of the present application.

[0020] Figure 3 Shown is a schematic diagram of a signal waveform provided in an embodiment of the present application.

[0021] Figure 4 Shown is another signal waveform schematic diagram provided in an embodiment of the present application.

[0022] Figure 5 Shown is another signal waveform schematic diagram provided in an embodiment of the present application.

[0023] Figure 6 The figure is a flow chart of a clock detection method provided in an embodiment of the present application.

[0024] Figure 7 Shown is a schematic structural diagram of a display panel provided in an embodiment of the present application.

[0025] Description of reference numerals: 100, clock detection circuit; 110, abnormality detection module; 120, result recognition module; 200, first clock signal output terminal; 300, second clock signal output terminal; 400, first memory; 500, second memory; 600, third memory; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; U1, inverter; U2, comparator; D1, diode; C1, capacitor; VCC, power supply terminal; Vo1, first output terminal; Vo2, second output terminal; Vo3, third output terminal. DETAILED DESCRIPTION

[0026] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0027] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0028] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0029] In a first aspect, the present application provides a clock detection circuit, which specifically includes the following embodiments: Figure 1 FIG. 1 is a schematic diagram of a clock detection circuit provided in an embodiment of the present application; Figure 1As shown, the clock detection circuit 100 includes: an abnormality detection module 110 and a result recognition module 120; specifically, the first input end of the abnormality detection module 110 is connected to the first clock signal output end 200, and the second input end of the abnormality detection module 110 is connected to the second clock signal output end 300, for performing abnormality detection on the first clock signal and the second clock signal, and outputting corresponding abnormality detection results; optionally, the input end of the result recognition module 120 is connected to the output end of the abnormality detection module 110, the first output end Vo1 of the result recognition module 120 is connected to the first memory 400, the second output end Vo2 of the result recognition module 120 is connected to the second memory 500, and the third output end Vo3 of the result recognition module 120 is connected to the third memory 600, for identifying the abnormality detection result, outputting the target recognition signal to the corresponding memory, so that the timing controller performs single-end drive or double-end drive on the display panel according to the target recognition signals in all memories.

[0030] In this embodiment, the clock detection circuit 100 is applied to a dual-end driven display panel. The dual-end drive means using two GDL circuits to drive the same scan line in the display panel. Each GDL circuit needs to generate a corresponding gate drive signal based on a clock signal; therefore, the first clock signal can be a clock signal for driving the right side of the scan line, and the second clock signal can be a clock signal for driving the left side of the scan line.

[0031] It should also be noted that, according to the GDL cascade relationship, one clock signal can sequentially drive multiple levels of non-adjacent GDL circuits. The present application does not elaborate on the correspondence between the GDL, the scan line and the clock signal, and only performs abnormality detection on each pair of clock signals (the first clock signal and the second clock signal). Under normal circumstances, the waveforms of the first clock signal and the second clock signal should be exactly the same. In addition, for the case of N pairs of clock signals, N clock detection circuits 100 can be used for simultaneous detection, or one clock detection circuit can be used to detect N pairs of clock signals in sequence.

[0032] Here, the abnormality detection process of a pair of clock signals is specifically described: the abnormality detection results in this embodiment include a first detection result that the first clock signal and the second clock signal are both normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal; that is: when the abnormality detection module 110 detects that the first clock signal and the second clock signal are both normal signals, the first detection result is output; when the abnormality detection module 110 detects that the first clock signal is a normal signal and the second clock signal is an abnormal signal, the second detection result is output; when the abnormality detection module 110 detects that the first clock signal is a normal signal and the second clock signal is an abnormal signal, the third detection result is output.

[0033] Next, the abnormal detection result is identified through the result recognition module 120, and a target recognition signal is output to the corresponding memory; specifically: if the result recognition module 120 recognizes that the abnormal detection result output by the abnormal detection module 110 is the first detection result, the target recognition signal is output to the first memory 400 through the first output terminal Vo1; if the result recognition module 120 recognizes that the abnormal detection result output by the abnormal detection module 110 is the second detection result, the target recognition signal is output to the second memory 500 through the second output terminal Vo2; if the result recognition module 120 recognizes that the abnormal detection result output by the abnormal detection module 110 is the third detection result, the target recognition signal is output to the third memory 600 through the third output terminal Vo3.

[0034] Finally, the display panel can be single-ended or double-ended driven according to the target recognition signals in all memories through the timing controller; specifically, double-ended driving is performed according to the target recognition signal in the first memory 400, right-end driving is performed according to the target recognition signal in the second memory 500, or left-end driving is performed according to the target recognition signal in the third memory 600.

[0035] It can be seen from this that the present application performs abnormality detection on the clock signals at both ends of the display panel through the abnormality detection module 110, and classifies and stores the abnormality detection results in different memories through the result recognition module 120, so that the timing controller performs single-ended or dual-ended driving on the display panel according to the target recognition signals in all memories; therefore, when an abnormality occurs in the clock signal on any side of any row, the present application promptly changes the dual-ended driving mode of all rows in the display panel to a single-ended driving mode at the same time, avoiding brightness abnormalities between normal rows and abnormal rows, thereby solving the problem of improving the picture display effect when an abnormality occurs in the clock signal of the dual-ended drive.

[0036] Figure 2 FIG. 1 is a circuit diagram of a clock detection circuit provided in an embodiment of the present application; Figure 2As shown, the abnormality detection module 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and an inverter U1; wherein the control end of the first transistor T1 is connected to the first clock signal output end 200, and the first end of the first transistor T1 is connected to the second clock signal output end 300; the control end of the second transistor T2 is connected to the control end of the first transistor T1, and the first end of the second transistor T2 is connected to the second end of the first transistor T1; the control end of the third transistor T3 is connected to the first end of the first transistor T1, the first end of the third transistor T3 is connected to the first end of the second transistor T2, and the second end of the third transistor T3 is connected to the control end of the second transistor T2; the control end of the fourth transistor T4 is connected to the second end of the second transistor T2, the first end of the fourth transistor T4 is connected to the first end of the third transistor T3, and the second end of the fourth transistor T4 is connected to the second end of the third transistor T3; the input end of the inverter U1 is connected to the control end of the third transistor T3, and the output end of the inverter U1 is connected to the control end of the fourth transistor T4; the second end of the first transistor T1 is the output end of the abnormality detection module 110.

[0037] In one embodiment, the turn-on voltages of the first transistor T1 and the second transistor T2 are opposite, the turn-on voltages of the third transistor T3 and the fourth transistor T4 are opposite, and the turn-on voltages of the first transistor T1 and the third transistor T3 are the same. Optionally, the first transistor T1 and the third transistor T3 are P-type MOS transistors, and the second transistor T2 and the fourth transistor T4 are N-type MOS transistors; optionally, the first transistor T1 and the third transistor T3 are N-type MOS transistors, and the second transistor T2 and the fourth transistor T4 are P-type MOS transistors.

[0038] In one embodiment, the abnormality detection module 110 also includes: a first resistor R1, a first end of the first resistor R1 is connected to the second end of the first transistor T1, and a second end of the first resistor R1 is grounded; wherein the first resistor R1 acts as a pull-down resistor, so that the voltage of the output end can be pulled down when the abnormality detection module 110 outputs a low level.

[0039] In one embodiment, the abnormality detection module 110 also includes a diode D1 and a capacitor C1, wherein the anode of the diode D1 is connected to the first end of the first resistor R1; the first end of the capacitor C1 is connected to the cathode of the diode D1, and the second end of the capacitor C1 is grounded; wherein the diode D1 has a rectifying function, and the capacitor C1 has a filtering function, so that the abnormality detection module 110 outputs a stable DC voltage.

[0040] For example: Here, the first transistor T1 and the third transistor T3 are P-type MOS tubes, and the second transistor T2 and the fourth transistor T4 are N-type MOS tubes. The working principle of the abnormality detection module 110 is described in detail in combination with the waveform diagram: 1. If Figure 3 As shown, when the first clock signal CKL_R and the second clock signal CKL_L are both normal square wave waveforms, the following two cases are described: (1) When the first clock signal CKL_R and the second clock signal CKL_L output a high level in the square wave, the control terminals of the first transistor T1 and the third transistor T3 input a high level, so that the first transistor T1 and the third transistor T3 are turned off; at the same time, the control terminal of the second transistor T2 inputs a high level, and the second transistor T2 is turned on; in addition, the high level of the second clock signal is converted into a low level after passing through the inverter U1, so that the fourth transistor T4 is turned off and the second end of the second transistor T2 is a low level, so that the turned-on second transistor T2 outputs a low level, and the rectifier diode D1 is turned off; that is: when the first clock signal and the second clock signal are both high levels, the abnormality detection module 110 outputs a low level, such as Figure 3 In the Va waveform; it should also be noted that, since the capacitor C1 has the energy storage function, there will be voltage, but the voltage is small, equivalent to a low level.

[0041] (2) When the first clock signal CKL_R and the second clock signal CKL_L output a low level in the square wave, the control end of the second transistor T2 inputs a low level, so that the second transistor T2 is turned off; at the same time, the control ends of the first transistor T1 and the third transistor T3 input a low level, so that the first transistor T1 and the third transistor T3 are turned on; in addition, the low level of the second clock signal is converted into a high level after passing through the inverter U1, so that the fourth transistor T4 is turned on, so that the turned-on first transistor T1, the third transistor T3 and the fourth transistor T4 all output a low level; that is to say: when the first clock signal and the second clock signal are both low levels, the abnormality detection module 110 still outputs a low level, such as Figure 3 Medium Va waveform.

[0042] 2. If Figure 4As shown, when the first clock signal CKL_R is a normal square wave signal, and the second clock signal CKL_L is an abnormal signal; it should be noted that, when the sine wave is regarded as an abnormal wave of an embodiment, the reference starting points of the sine wave and the square wave are the same, both of which are based on the low level point of the square wave, and the potential of the sine wave is higher than the potential of the square wave; therefore, when the first clock signal CKL_R is a normal square wave low level L, the second clock signal CKL_L is an abnormal sine wave and is regarded as a high level H; this implementation is only used as a comparative example, and other waveforms can also be regarded as abnormal waves, only It can be the same as the normal square wave signal; it can be seen that when the first clock signal is a low level L and the second clock signal is a high level H, the first transistor T1 is turned on and outputs a high level, and at the same time, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off, so that the anode end of the diode D1 has a higher potential, and the first end of the capacitor C1 outputs a first high level (for example, 4.6V); that is to say: when the first clock signal CKL_R is a normal square wave waveform and the second clock signal CKL_L is an abnormal waveform, the abnormality detection module 110 outputs a first high level H1, such as Figure 4 Medium Va waveform.

[0043] 3. If Figure 5 As shown, when the first clock signal CKL_R is an abnormal sine wave and the second clock signal CKL_L is a normal square wave, the second clock signal CKL_L is a low level L, the first clock signal CKL_R is a high level H, the first transistor T1 is turned off, and at the same time, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned on to output a high level to the anode end of the diode D1, and the diode D1 is turned on so that the first end of the capacitor C1 outputs a second high level (for example, 8.7V); it should be noted that, compared with the above-mentioned point 2, there is a superposition of two conduction paths at the anode of the diode D1, and the voltage value of the second high level is greater than the voltage value of the first high level; that is to say: when the first clock signal CKL_R is an abnormal sine wave and the second clock signal CKL_L is a normal square wave, the abnormality detection module 110 outputs the second high level H2, as shown in FIG. Figure 5 Medium Va waveform.

[0044] In one embodiment, if Figure 2 As shown, the result identification module 120 includes: a fifth transistor T5 and a second resistor R2, the control end of the fifth transistor T5 is connected to the output end of the abnormality detection module 110, and the first end of the fifth transistor T5 is connected to the power supply end VCC; the first end of the second resistor R2 is connected to the second end of the fifth transistor T5, and the second end of the second resistor R2 is grounded.

[0045] It should be noted that the second end of the fifth transistor T5 is used as the first output end Vo1 of the result recognition module 120, that is, the output node 1; specifically, the fifth transistor T5 is a P-type MOS tube; when the abnormality detection module 110 outputs a low level, the fifth transistor T5 is turned on, so that the output node 1 outputs a high level, such as Figure 3 In addition, when the abnormality detection module 110 outputs a high level, the fifth transistor T5 is turned off, so that the first output terminal Vo1 outputs a low level, such as Figure 4 and 5 The Vo1 waveform in .

[0046] In another embodiment, if Figure 2 As shown, the result identification module 120 also includes a comparator U2, a sixth transistor T6, a seventh transistor T7 and a third resistor R3; the first input end of the comparator U2 is connected to the output end of the abnormality detection module 110, and the second input end of the comparator U2 is connected to the power supply end VCC; the control end of the sixth transistor T6 is connected to the output end of the comparator U2, and the first end of the sixth transistor T6 is connected to the power supply end VCC; the control end of the seventh transistor T7 is connected to the second end of the fifth transistor T5, and the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6; the first end of the third resistor R3 is connected to the second end of the seventh transistor T7, and the second end of the third resistor R3 is grounded.

[0047] In one embodiment, the result identification module 120 further includes an eighth transistor T8 and a fourth resistor R4, wherein the control end of the eighth transistor T8 is connected to the output end of the comparator U2, and the first end of the eighth transistor T8 is connected to the power supply end VCC; the first end of the fourth resistor R4 is connected to the second end of the eighth transistor T8, and the second end of the fourth resistor R4 is grounded; It should be noted that the second end of the seventh transistor T7 is used as the second output end Vo2 of the result identification module 120, that is, the output node 2; the second end of the eighth transistor T8 is used as the third output end Vo3 of the result identification module 120, that is, the output node 3.

[0048] Optionally, the comparator U2 is used to compare the output voltage of the abnormality detection module 110 with the threshold voltage, and outputs a high level if the output voltage of the abnormality detection module 110 is greater than the threshold voltage, and outputs a low level if the output voltage of the abnormality detection module 110 is less than the threshold voltage; in this embodiment, the threshold voltage is set to be greater than the first high level and less than the second high level, for example, 5V, and the voltage output by the power supply terminal VCC is used as the threshold voltage. Optionally, the sixth transistor T6 and the seventh transistor T7 are P-type MOS tubes, and the eighth transistor T8 is an N-type MOS tube.

[0049] Specifically, when the abnormality detection module 110 outputs a low level, the comparator U2 outputs a low level, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned off, so that the first output terminal Vo1 outputs a high level, the second output terminal Vo2 outputs a low level, and the third output terminal Vo3 outputs a low level. Figure 3 The Vo1, Vo2, and Vo3 waveforms in .

[0050] Specifically, when the abnormality detection module 110 outputs the first high level, the comparator U2 outputs a low level, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off, so that the first output terminal Vo1 outputs a low level, the second output terminal Vo2 outputs a high level, and the third output terminal Vo3 outputs a low level. Figure 4 The Vo1, Vo2, and Vo3 waveforms in .

[0051] Specifically, when the abnormality detection module 110 outputs the second high level, the comparator U2 outputs a high level, the fifth transistor T5 is turned off, the sixth transistor T6 is turned off, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned on, so that the first output terminal Vo1 outputs a low level, the second output terminal Vo2 outputs a low level, and the third output terminal Vo3 outputs a high level. Figure 5 The Vo1, Vo2, and Vo3 waveforms in .

[0052] Here, the detection results of the above clock signals are summarized as shown in Table 1: Table 1. Clock signal detection results

[0053] In this embodiment, the high level H outputted by the first output terminal Vo1, the second output terminal Vo2 or the third output terminal Vo3 is used as the target recognition signal.

[0054] It should also be noted that the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can also be N-type MOS transistors, and the eighth transistor T8 is a P-type MOS transistor; different from the above embodiment, the output logic of the three output terminals of the result identification module 120 is opposite, so that the subsequent processing logic can also be adaptively adjusted without affecting the feasibility of the solution.

[0055] In a second aspect, the present application provides a clock detection method, which specifically includes the following embodiments: Figure 6 FIG. 1 is a flow chart of a clock detection method provided in an embodiment of the present application; Figure 6 As shown, the clock detection method specifically includes the following steps: Step S100: Perform an abnormality detection on the first clock signal and the second clock signal corresponding to each pixel row to obtain a corresponding abnormality detection result.

[0056] Among them, the abnormal detection results include a first detection result that both the first clock signal and the second clock signal are normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal.

[0057] Step S200, identifying the abnormal detection result, outputting the target recognition signal to the corresponding memory, so that the timing controller performs single-end driving or double-end driving on the display panel according to the target recognition signals in all memories.

[0058] Wherein, if it is the first detection result, the target recognition signal is output to the first memory, if it is the second detection result, the target recognition signal is output to the second memory, and if it is the third detection result, the target recognition signal is output to the third memory.

[0059] It should be noted that the detection principle of the clock detection method is the same as the working principle of the clock detection circuit in the above embodiment, and will not be described in detail here.

[0060] In a third aspect, the present application provides a display panel, which specifically includes the following embodiments: Figure 7 FIG. 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application; Figure 7 As shown, the display panel specifically includes: A clock generator, configured to output N first clock signals and N second clock signals; A clock detection circuit, the clock detection circuit is connected to the first clock signal output terminal and the second clock signal output terminal of the clock generator respectively, and is used to detect abnormalities of the first clock signal and the second clock signal; A first memory, connected to a first output terminal of each clock detection circuit, for receiving a target identification signal output by each clock detection circuit; A second memory, connected to the second output terminal of each clock detection circuit, for receiving the target identification signal output by each clock detection circuit; a third memory connected to the third output terminal of each clock detection circuit and configured to receive the target identification signal output by each clock detection circuit; M cascaded first GDL circuits ( Figure 7 (not shown), each first GDL circuit is respectively connected to a first clock signal output terminal of the clock generator and a first end of a corresponding scan line in the display panel, and is used to output a corresponding gate drive signal under the action of the first clock signal; M cascaded second GDL circuits ( Figure 7 (not shown), each second GDL circuit is respectively connected to the second clock signal output terminal of the clock generator and the second end of the corresponding scan line in the display panel, and is used to output a corresponding gate drive signal under the action of the second clock signal; A timing controller is connected to the first memory, the second memory, the third memory, the first GDL circuit and the second GDL circuit respectively, and is used to control the first GDL circuit and the second GDL circuit to be turned on or off according to the target identification signals in all the memories.

[0061] In one embodiment, according to the target identification signals in all memories, the first GDL circuit and the second GDL circuit are controlled to be turned on or off, specifically including the following situations: (1) When there are N target identification signals in the first memory, the first GDL circuit and the second GDL circuit are turned on at the same time; it should be noted that when there are N target identification signals in the first memory, it means that all the first clock signals and all the second clock signals are normal signals, then all the first GDL circuits and the second GDL circuits are turned on through the timing controller to realize double-end driving of the display panel.

[0062] (2) When at least one target identification signal exists in the second memory, the second GDL circuit is turned off; specifically, when at least one target identification signal exists in the second memory, it indicates that at least one second clock signal is abnormal, and all second GDL circuits need to be turned off to implement right-end driving of the display panel.

[0063] (3) When at least one target identification signal exists in the third memory, the first GDL circuit is turned off; specifically, when at least one target identification signal exists in the third memory, it indicates that at least one first clock signal is abnormal, and it is necessary to turn off all first GDL circuits to implement left-end driving of the display panel.

[0064] It should also be noted that the target identification signal usually does not exist in the second memory and the third memory at the same time.

[0065] Therefore, when this embodiment detects an abnormality in the clock signal on either side of any row, it promptly changes the double-ended driving mode of all rows in the display panel to a single-ended driving mode at the same time, avoiding brightness abnormalities between normal rows and abnormal rows, thereby solving the problem of improving the picture display effect when an abnormality occurs in the clock signal of the double-ended drive.

[0066] To summarize, when the clock detection circuit is applied to a dual-end driven display panel, when an abnormality is detected in the clock signal on either side, the gate drive signal on the corresponding side is turned off. If the clock signals on both sides are normal, dual-end driving is used. While improving the stability of the display panel, it can also improve picture abnormalities without affecting customer experience, thereby increasing product life and profits.

[0067] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0068] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0069] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A clock detection circuit, characterized in that: Applicable to a double-ended driven display panel, the clock detection circuit comprises: An abnormality detection module, wherein a first input end of the abnormality detection module is connected to the first clock signal output end, and a second input end of the abnormality detection module is connected to the second clock signal output end, and is used to perform abnormality detection on the first clock signal and the second clock signal, and output corresponding abnormality detection results; A result recognition module, wherein the input end of the result recognition module is connected to the output end of the abnormality detection module, the first output end of the result recognition module is connected to the first memory, the second output end of the result recognition module is connected to the second memory, and the third output end of the result recognition module is connected to the third memory, for identifying the abnormality detection result, outputting a target recognition signal to the corresponding memory, so that the timing controller performs single-end drive or double-end drive on the display panel according to the target recognition signal in all memories.

2. The clock detection circuit according to claim 1, characterized in that: The anomaly detection module comprises: a first transistor, wherein a control terminal of the first transistor is connected to the first clock signal output terminal, and a first terminal of the first transistor is connected to the second clock signal output terminal; a second transistor, wherein a control terminal of the second transistor is connected to a control terminal of the first transistor, and a first terminal of the second transistor is connected to a second terminal of the first transistor; a third transistor, wherein a control terminal of the third transistor is connected to a first terminal of the first transistor, a first terminal of the third transistor is connected to a first terminal of the second transistor, and a second terminal of the third transistor is connected to a control terminal of the second transistor; a fourth transistor, wherein a control end of the fourth transistor is connected to the second end of the second transistor, a first end of the fourth transistor is connected to the first end of the third transistor, and a second end of the fourth transistor is connected to the second end of the third transistor; an inverter, wherein an input end of the inverter is connected to the control end of the third transistor, and an output end of the inverter is connected to the control end of the fourth transistor; Wherein, the second end of the first transistor is the output end of the abnormality detection module.

3. The clock detection circuit according to claim 2, characterized in that: The turn-on voltages of the first transistor and the second transistor are opposite, the turn-on voltages of the third transistor and the fourth transistor are opposite, and the turn-on voltages of the first transistor and the third transistor are the same.

4. The clock detection circuit according to claim 2 or 3, characterized in that: The anomaly detection module also includes: a first resistor, wherein a first end of the first resistor is connected to a second end of the first transistor, and a second end of the first resistor is grounded; a diode, wherein an anode of the diode is connected to a first end of the first resistor; A capacitor, a first end of the capacitor is connected to the cathode of the diode, and a second end of the capacitor is grounded.

5. The clock detection circuit according to claim 1, characterized in that: The result identification module comprises: a fifth transistor, wherein a control end of the fifth transistor is connected to the output end of the abnormality detection module, and a first end of the fifth transistor is connected to a power supply end; a second resistor, wherein a first end of the second resistor is connected to a second end of the fifth transistor, and a second end of the second resistor is grounded; Wherein, the second end of the fifth transistor is the first output end of the result identification module.

6. The clock detection circuit according to claim 5, characterized in that: The result recognition module also includes: A comparator, wherein a first input terminal of the comparator is connected to the output terminal of the abnormality detection module, and a second input terminal of the comparator is connected to the power supply terminal; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the output terminal of the comparator, and a first terminal of the sixth transistor is connected to the power supply terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and a first terminal of the seventh transistor is connected to the second terminal of the sixth transistor; a third resistor, wherein a first end of the third resistor is connected to the second end of the seventh transistor, and a second end of the third resistor is grounded; Wherein, the second end of the seventh transistor is the second output end of the result identification module.

7. The clock detection circuit according to claim 6, characterized in that: The result recognition module also includes: an eighth transistor, wherein a control terminal of the eighth transistor is connected to the output terminal of the comparator, and a first terminal of the eighth transistor is connected to the power supply terminal; a fourth resistor, a first end of the fourth resistor being connected to the second end of the eighth transistor, and a second end of the fourth resistor being grounded; Wherein, the second end of the eighth transistor is the third output end of the result identification module.

8. A clock detection method, characterized in that: Applicable to the clock detection circuit according to any one of claims 1 to 7, the clock detection method comprising: Performing abnormality detection on the first clock signal and the second clock signal corresponding to each pixel row to obtain corresponding abnormality detection results; wherein the abnormality detection results include a first detection result that the first clock signal and the second clock signal are both normal, a second detection result that the first clock signal is normal but the second clock signal is abnormal, and a third detection result that the first clock signal is abnormal but the second clock signal is normal; The abnormal detection result is identified, and a target identification signal is output to a corresponding memory, so that a timing controller performs single-end or double-end driving on the display panel according to the target identification signal in all memories; wherein, if it is a first detection result, the target identification signal is output to a first memory, if it is a second detection result, the target identification signal is output to a second memory, and if it is a third detection result, the target identification signal is output to a third memory.

9. A display panel, characterized in that: The display panel comprises: A clock generator, configured to output N first clock signals and N second clock signals; The clock detection circuit according to any one of claims 1 to 7, wherein the clock detection circuit is respectively connected to a first clock signal output terminal and a second clock signal output terminal of a clock generator, and is used to perform abnormality detection on the first clock signal and the second clock signal; A first memory, connected to a first output terminal of each clock detection circuit, for receiving a target identification signal output by each clock detection circuit; A second memory, connected to the second output terminal of each clock detection circuit, for receiving the target identification signal output by each clock detection circuit; a third memory connected to the third output terminal of each clock detection circuit and configured to receive the target identification signal output by each clock detection circuit; M cascaded first GDL circuits, each of which is respectively connected to a first clock signal output terminal of the clock generator and a first terminal of a corresponding scan line in the display panel, and is used for outputting a corresponding gate drive signal under the action of the first clock signal; M cascaded second GDL circuits, each second GDL circuit is respectively connected to the second clock signal output terminal of the clock generator and the second end of the corresponding scan line in the display panel, and is used for outputting a corresponding gate drive signal under the action of the second clock signal; A timing controller is respectively connected to the first memory, the second memory, the third memory, the first GDL circuit and the second GDL circuit, and is used to control the first GDL circuit and the second GDL circuit to be turned on or off according to the target identification signals in all the memories.

10. The display panel according to claim 9, characterized in that: According to the target identification signals in all memories, controlling the first GDL circuit and the second GDL circuit to be turned on or off includes: When there are N target identification signals in the first memory, the first GDL circuit and the second GDL circuit are turned on simultaneously; When at least one target identification signal exists in the second memory, closing the second GDL circuit; When at least one target identification signal exists in the third memory, the first GDL circuit is turned off.

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