Display device and head-mounted display device

Abstract

The invention discloses a display device and a head-mounted display device. The display device includes: a display panel including a display area in which a plurality of data lines and a plurality of pixels connected to the plurality of data lines are disposed and a non-display area at a periphery of the display area; a temperature sensor disposed in the non-display area of the display panel, the temperature sensor configured to output temperature data corresponding to the sensed temperature; and a data driver configured to convert the temperature data into digital type temperature data, synthesize the background image based on the digital type temperature data, and convert synthesized image data obtained by synthesizing the background image into a data voltage, thereby outputting the data voltage to the plurality of data lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0132131 filed on October 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, a driving method of the display device, and a head-mounted display device including the display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and inorganic light emitting display devices are increasingly used.

[0005] The temperature sensor may be provided in the display device. For example, the controller may adjust the brightness of an image displayed in the display device based on temperature data received from the temperature sensor.

[0006] However, when the connection between the temperature sensor and the controller is deteriorated, it may be difficult for a user to recognize heating (or overheating) of the display device. Summary of the invention

[0007] The embodiments may provide a display device, a driving method of the display device, and a head-mounted display device including the display device, in which a user can visually recognize heating even when a connection between a temperature sensor and a controller is deteriorated.

[0008] An embodiment of a display device includes: a display panel including a display area and a non-display area at the periphery of the display area, wherein a plurality of data lines and a plurality of pixels connected to the plurality of data lines are arranged in the display area; a temperature sensor arranged in the non-display area of ​​the display panel, the temperature sensor being configured to output temperature data corresponding to a sensed temperature; and a data driver configured to convert the temperature data into digital temperature data, synthesize a background image based on the digital temperature data, and convert the synthesized image data obtained by synthesizing the background image into a data voltage, thereby outputting the data voltage to the plurality of data lines.

[0009] The data driver may be connected to a panel line disposed in the non-display area of ​​the display panel. The temperature sensor may output the temperature data through the panel line.

[0010] The data driver may include: an analog-to-digital converter configured to convert the temperature data into the digital temperature data; a memory configured to store the digital temperature data; a temperature image generator configured to store the background image in the temperature image generator and generate composite image data obtained by synthesizing the background image with received image data based on a result obtained by reading the digital temperature data stored in the memory; and an output circuit configured to convert the composite image data into a data voltage, thereby outputting the data voltage to the plurality of data lines.

[0011] The display device may further include: a controller configured to receive the digital temperature data and input image data, generate the image data by correcting the input image data based on the digital temperature data, and output the image data and a data control signal.

[0012] The data driver may further include: a first interface configured to receive the data control signal and output the digital temperature data; and a second interface configured to receive the image data.

[0013] The first interface may be an inter-integrated circuit (I2C) interface, and the second interface may be a low voltage differential signaling (LVDS) interface.

[0014] A plurality of temperature sensors including the temperature sensor may be disposed in the non-display area of ​​the display panel. The plurality of temperature sensors may be disposed corresponding to a plurality of corner areas in the display area.

[0015] The analog-to-digital converter may sequentially sense the plurality of temperature sensors.

[0016] A plurality of digital temperature data generated by sequentially sensing the plurality of temperature sensors may be stored in the memory.

[0017] The temperature image generator may generate the synthesized image data by synthesizing the background image with the image data based on the plurality of digital temperature data so that the background image is displayed in the region determined to be at a high temperature.

[0018] The background image may be displayed in at least one of the plurality of corner areas of the display area.

[0019] The background image may be displayed in an edge region in which two adjacent corner regions among the plurality of corner regions of the display region are connected to each other.

[0020] The temperature image generator may perform different gradient processes on the background image based on the value of the digital temperature data.

[0021] An embodiment of a method for driving a display device includes: receiving temperature data from a temperature sensor disposed in a non-display area of ​​a display panel; converting the received temperature data into digital temperature data; storing the converted digital temperature data in a memory; reading the digital temperature data stored in the memory; synthesizing a pre-stored background image with input image data based on the read digital temperature data; converting the synthesized image data obtained by synthesizing the background image with the image data into a data voltage corresponding thereto; and outputting the data voltage to the display area of ​​the display panel.

[0022] An embodiment of a head-mounted display device includes: a processor configured to output first input image data and second input image data; a first display device including a first display panel, the first display device configured to synthesize a stored background image with first image data corresponding to the first input image data based on temperature data sensed in the first display panel, thereby displaying a first synthesized image to a first eye of a user; and a second display device including a second display panel, the second display device configured to synthesize a stored background image with second image data corresponding to the second input image data based on temperature data sensed in the second display panel, thereby displaying a second synthesized image to a second eye of the user.

[0023] The first display panel may include a display area and a non-display area at the periphery of the display area, and a plurality of data lines and a plurality of pixels connected to the plurality of data lines may be arranged in the display area. The first display device may include: a temperature sensor arranged in the non-display area of ​​the first display panel, the temperature sensor outputting the temperature data corresponding to the sensed temperature; and a data driver configured to convert the temperature data into digital temperature data, synthesize a background image based on the digital temperature data, and convert the synthesized image data obtained by synthesizing the background image into a data voltage, thereby outputting the data voltage to the plurality of data lines.

[0024] The data driver may include: an analog-to-digital converter configured to convert the temperature data into the digital temperature data; a memory configured to store the digital temperature data; a temperature image generator configured to store the background image in the temperature image generator and, based on a result obtained by reading the digital temperature data stored in the memory, generate composite image data obtained by synthesizing the background image with received first image data; and an output circuit configured to convert the composite image data into a data voltage, thereby outputting the data voltage to the plurality of data lines.

[0025] The first display device may further include: a controller configured to receive the digital temperature data and the first input image data, generate the first image data by correcting the first input image data based on the digital temperature data, and output the first image data and the data control signal.

[0026] The data driver may further include: a first interface configured to receive the data control signal and output the digital temperature data; and a second interface configured to receive the first image data. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments will be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0029] Figure 1 is a system block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 A block diagram of an embodiment of a sub-pixel is shown in FIG.

[0031] Figure 3 It is shown Figure 2 An equivalent circuit diagram of an embodiment of a sub-pixel is shown in FIG.

[0032] Figure 4 is a system block diagram of a data driver according to an embodiment of the present disclosure.

[0033] Figure 5 is a plan view showing a display panel according to an embodiment of the present disclosure.

[0034] Figure 6 is an example of an image displayed in a display area according to an embodiment of the present disclosure.

[0035] Figure 7 is through Figure 6 An example of an image obtained by synthesizing a background image in a corner area of ​​an image shown in .

[0036] Figure 8 is through Figure 6 Another example of an image obtained by synthesizing a background image in a corner area of ​​an image shown in .

[0037] Fig. 9 is through Figure 6 An example of an image obtained by synthesizing a background image in the edge region of the image shown in FIG.

[0038] Fig.10 is through Figure 6 An example of an image obtained by synthesizing a gradation-processed background image in the corner area of ​​the image shown in .

[0039] Fig.11 It is shown Figure 5 An exploded perspective view of a portion of a display panel is shown in FIG.

[0040] Fig.12 It is shown Fig.11 A plan view of an embodiment of any one of the pixels shown in .

[0041] Fig.13 It is shown along Fig.12 2 is a cross-sectional view of an example of a pixel taken along line II′ shown in FIG.

[0042] Fig.14 It is shown Fig.13 A cross-sectional view of an embodiment of a light emitting structure included in any one of the first to third light emitting elements shown in FIG.

[0043] Fig.15 It is shown Fig.13 A cross-sectional view of another embodiment of a light emitting structure included in any one of the first to third light emitting elements shown in FIG.

[0044] Fig.16 It is shown Figure 5 A plan view of another embodiment of any of the pixels shown in .

[0045] Fig.17 It is shown Figure 5A plan view of yet another embodiment of any of the pixels shown in .

[0046] Fig.18 is a block diagram illustrating an embodiment of a display system according to an embodiment of the present disclosure.

[0047] Fig.19 It is shown Fig.18 A perspective view of an embodiment of a display system is shown in FIG.

[0048] Fig. 20 is a view showing an embodiment of a head-mounted display device worn by a user. DETAILED DESCRIPTION

[0049] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the exemplary embodiments described in this specification.

[0050] In order to clearly describe the present disclosure, parts irrelevant to the description will be omitted, and the same or similar constituent elements will be represented by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

[0051] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clarity of expression, the thickness of several parts and regions is exaggerated.

[0052] In the description, the expression "equal" may mean "substantially equal." That is, it may mean equality to an equal degree that can be understood by those skilled in the art. Other expressions may be expressions in which "substantially" is omitted.

[0053] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0054] As used herein, the word "or" means a logical "or" such that the statement "A, B, or C" means "A and B and C," "A and B but not C," "A and C but not B," "B and C but not A," "A but not B and not C," "B but not A and not C," and "C but not A and not B," unless the context indicates otherwise.

[0055] The terms "below", "below", "above", and "on top" etc. are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0056] Unless otherwise defined, it will be understood that all terms (including technical terms and scientific terms) used in this specification have the same meaning as those understood by those skilled in the art. In addition, unless clearly and specifically defined, terms defined in general dictionaries should not be ideally or overly formally defined.

[0057] It will also be understood that when the terms "include" and "comprises" (and their variations, such as "comprising") are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

[0058] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0059] Figure 1 is a system block diagram of a display device 100 according to an embodiment of the present disclosure.

[0060] refer to Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110, a gate driving circuit 120, a data driver 130, a voltage generator 140, a controller 150, a temperature sensor 160, and the like.

[0061] The display panel 110 may include a plurality of sub-pixels SP. First to m-th gate lines GL1 to GLm (m is an integer of 2 or more) connected to the plurality of sub-pixels SP may be provided in the display panel 110. First to n-th data lines DL1 to DLn (n is an integer of 2 or more) connected to the plurality of sub-pixels SP may be provided in the display panel 110.

[0062] The plurality of subpixels SP may be connected (eg, electrically connected) to the gate driving circuit 120 through first to m-th gate lines GL1 to GLm. The plurality of subpixels SP may be connected (eg, electrically connected) to the data driver 130 through first to n-th data lines DL1 to DLn.

[0063] Each of the plurality of sub-pixels SP may include at least one light emitting element configured to generate light. Each of the plurality of sub-pixels SP may generate light of a color (e.g., a specific color or a specific wavelength band) such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the plurality of sub-pixels SP may constitute one pixel PXL. For example, three sub-pixels SP may constitute a pixel PXL. Figure 1 A pixel PXL is shown in FIG.

[0064] The gate driving circuit 120 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged in a first direction DR1 as a whole) through the first gate line GL1 to the m-th gate line GLm. The first direction DR1 may be, for example, a direction crossing the display panel 110 from one side (e.g., the left side) to the other side (e.g., the right side) of the display panel 110. The first direction DR1 may be, for example, a row direction.

[0065] The gate driving circuit 120 may output a gate signal (e.g., a gate signal having an on level or an off level) to the first gate line GL1 to the m-th gate line GLm in response to the gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data voltage, etc.

[0066] In an embodiment, first emission control lines EL1 to m-th emission control lines ELm connected to a plurality of sub-pixels SP may be further provided in the display panel 110. The first emission control lines EL1 to m-th emission control lines ELm may be provided in the display panel 110 while extending in the row direction. A plurality of sub-pixels SP may be connected (e.g., electrically connected) to the first emission control lines EL1 to m-th emission control lines ELm. In the above-described embodiment, the gate drive circuit 120 may include an emission control driver configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control driver may operate under the control of the controller 150.

[0067] The gate drive circuit 120 may be disposed at one side of the display panel 110. However, the embodiments of the present disclosure are not limited thereto. For example, the gate drive circuit 120 may be divided into two or more drive circuits that are physically or logically divided, and these drive circuits may be disposed at one side of the display panel 110 and at the other side of the display panel 110 (e.g., the other side of the display panel 110 that faces the side of the display panel 110). Thus, in some embodiments, the gate drive circuit 120 may be disposed in the display panel 110 or at the periphery of the display panel 110 in various forms.

[0068] The data driver 130 may be connected (e.g., electrically connected) to a plurality of sub-pixels SP (e.g., a plurality of sub-pixels SP arranged in a second direction DR2 as a whole) through the first to n-th data lines DL1 to DLn. The second direction DR2 may be, for example, a direction crossing the display panel 110 from one side (e.g., the lower side) of the display panel 110 to the other side (e.g., the upper side) of the display panel 110. The second direction DR2 may be, for example, a column direction.

[0069] The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse signal, a source shift clock signal, a source output enable signal, and the like.

[0070] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data line DL1 to the nth data line DLn by using a voltage (e.g., a gamma voltage Vgamma) from the voltage generator 140. When a gate signal (e.g., a gate signal having an on level) is applied to each of the first gate line GL1 to the mth gate line GLm, a data voltage corresponding to the image data DATA may be applied to the data lines DL1 to DLm. In response to the gate signal (e.g., a gate signal having an on level), each of the plurality of sub-pixels SP may receive a data voltage applied at a corresponding timing. Each of the plurality of sub-pixels SP may generate light corresponding to the received data voltage. Thus, an image may be displayed in the display panel 110.

[0071] In an embodiment, each of the gate driving circuit 120 and the data driver 130 may include a complementary metal oxide semiconductor (CMOS) circuit element.

[0072] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from outside the display device 100. The voltage generator 140 may adjust (e.g., reduce) the level of the received voltage and regulate the voltage having the adjusted level. The voltage generator 140 may be configured to generate a plurality of voltages.

[0073] The voltage generator 140 may generate, for example, a first power supply voltage VDD, a second power supply voltage VSS, a gamma voltage Vgamma, etc. The generated first power supply voltage VDD and the second power supply voltage VSS may be applied (e.g., commonly applied) to a plurality of sub-pixels SP. The first power supply voltage VDD may have a relatively high voltage level. The second power supply voltage VSS may have a voltage level lower than the voltage level of the first power supply voltage VDD. The generated gamma voltage Vgamma may be provided to the data driver 130. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device (e.g., a power management integrated circuit (PMIC)) of the display device 100.

[0074] In some embodiments, the voltage generator 140 may further generate another voltage. For example, the voltage generator 140 may generate an initialization voltage applied (e.g., commonly applied) to the plurality of sub-pixels SP. For example, in a sensing operation for sensing electrical characteristics of transistors or light-emitting elements of the plurality of sub-pixels SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate the reference voltage.

[0075] The controller 150 may be configured to control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of the image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, a voltage control signal VCS, etc. in response to the received control signal CTRL.

[0076] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110, thereby outputting the image data DATA. In an embodiment, the controller 150 may arrange the input image data IMG in a row unit to be suitable for the sub-pixels SP, thereby outputting the image data DATA.

[0077] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted in one integrated circuit. Figure 1As shown in , the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 may be components functionally divided in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be installed in the driver integrated circuit DIC, and another one of the data driver 130, the voltage generator 140, and the controller 150 may be provided to be installed in an integrated circuit different from the driver integrated circuit DIC.

[0078] The temperature sensor 160 may be configured to sense a temperature (e.g., a temperature at its periphery) and generate temperature data TEP indicating the sensed temperature. In some embodiments, the temperature sensor 160 may be disposed in the display panel 110. In some embodiments, the temperature sensor 160 may be disposed adjacent to the display panel 110 or the driver integrated circuit DIC. In some embodiments, the display device 100 may include two or more temperature sensors 160.

[0079] In an embodiment of the present disclosure, the data driver 130 may receive temperature data TEP from the temperature sensor 160. The data driver 130 may include an analog-to-digital converter ADC configured to convert the temperature data TEP input from the temperature sensor 160 into digital temperature data D_TEP. However, the embodiment of the present disclosure is not limited thereto, and the analog-to-digital converter ADC may be located outside the data driver 130.

[0080] The analog-to-digital converter ADC may convert the input temperature data TEP into digital temperature data D_TEP corresponding thereto. The digital temperature data D_TEP may be output from the data driver 130 to be input to the controller 150.

[0081] The controller 150 may control various operations of the display device 100 in response to the digital temperature data D_TEP. In an embodiment, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the digital temperature data D_TEP. For example, in response to the digital temperature data D_TEP, the controller 150 may generate image data DATA by correcting input image data IMG. For example, the controller 150 may adjust at least one of a data voltage input to the display panel 110, a first power supply voltage VDD, and a second power supply voltage VSS by controlling a component such as the data driver 130 or the voltage generator 140.

[0082] Figure 2 It is shown Figure 1 A block diagram of an embodiment of a sub-pixel SP is shown in FIG.

[0083] exist Figure 2 In the example, it is shown Figure 1 A sub-pixel SPij disposed on the i-th row (i is an integer greater than 1 and less than or equal to m) and the j-th column (j is an integer greater than 1 and less than or equal to n) among the plurality of sub-pixels SP shown in .

[0084] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0085] The light emitting element LD may be connected (eg, electrically connected) between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be a node to which a Figure 1 The second power supply voltage node VSSN may be a node to which the first power supply voltage VDD is applied. Figure 1 A node of the second power supply voltage VSS is shown in .

[0086] The light emitting element LD may include a first electrode, a light emitting structure EMS, and a second electrode. The first electrode may be any one of the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD. The second electrode may be the other of the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD. Hereinafter, for ease of description, a case where the first electrode of the light emitting element LD is the anode electrode AE ​​and the second electrode of the light emitting element LD is the cathode electrode CE is described as an example.

[0087] The anode electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power supply voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected (e.g., electrically connected) to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected (e.g., electrically connected) to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0088] The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm shown in FIG. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line Elm shown in FIG. The sub-pixel circuit SPC of the sub-pixel SPij may be connected (eg, electrically connected) to Figure 1The j-th data line DLj among the first to n-th data lines DL1 to DLn shown in FIG. The sub-pixel circuit SPC may be configured to control the emission timing or emission brightness of the light emitting element LD according to (or in response to) signals received through these signal lines.

[0089] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi.

[0090] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage of a data voltage (or a voltage corresponding to the data voltage) in response to a gate signal (e.g., a gate signal having a conduction level) received through the i-th gate line GLi. The sub-pixel circuit SPC may adjust the timing of current flowing through the light-emitting element LD in response to an emission control signal (e.g., an emission control having a conduction level) applied through the i-th emission control line ELi. The magnitude of the current flowing through the light-emitting element LD may vary according to the voltage stored in the sub-pixel circuit SPC. The light-emitting element LD may generate light having a brightness corresponding to the data voltage.

[0091] Figure 3 It is shown Figure 2 Equivalent circuit diagram of an embodiment of a sub-pixel SPij shown in FIG.

[0092] refer to Figure 3 The sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD. The sub-pixel circuit SPC may be connected (eg, electrically connected) to an i-th gate line GLi, an i-th emission control line ELi, and a j-th data line DLj.

[0093] The i-th gate line GLi may include two or more sub-gate lines. Figure 3 , the i-th gate line GLi may include a first sub-gate line SGL1, a second sub-gate line SGL2, and a third sub-gate line SGL3.

[0094] The i-th emission control line ELi may include two or more sub-emission control lines. Figure 3 , the i-th emission control line ELi may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0095] The sub-pixel circuit SPC may include at least two switching elements (eg, transistors) and at least one storage element (eg, at least one capacitor). Figure 3 , the sub-pixel circuit SPC according to an embodiment of the present disclosure may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0096] The first transistor T1 may be connected between the first power supply voltage node VDDN and the first node N1. Figure 3 , the first transistor T1 may be connected between the sixth transistor T6 and the first node N1. The gate of the first transistor T1 may be connected (e.g., electrically connected) to the second node N2. The first transistor T1 may be turned on according to the voltage level of the second node N2. The magnitude of the current (e.g., the drive current) flowing through the first transistor T1 may be differently controlled according to the voltage level of the second node N2. The first transistor T1 may be designated as a drive transistor.

[0097] The second transistor T2 may be connected between the j-th data line DLj and the second node N2. Figure 3 , the second transistor T2 may be configured to switch the electrical connection between the j-th data line DLj and the first capacitor C1. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1. The second transistor T2 may be controlled in response to the first gate signal SCAN1 applied to the first sub-gate line SGL1. The second transistor T2 may be turned on in response to the first gate signal SCAN1 having a turn-on level. The second transistor T2 may be designated as a switching transistor.

[0098] The third transistor T3 may be configured to switch the electrical connection between the first node N1 and the second node N2. The gate of the third transistor T3 may be connected (e.g., electrically connected) to the second sub-gate line SGL2. The third transistor T3 may be controlled in response to a second gate signal SCAN2 applied to the second sub-gate line SGL2. The third transistor T3 may be turned on in response to the second gate signal SCAN2 having a turn-on level.

[0099] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. Figure 3 , the fourth transistor T4 may be configured to switch the electrical connection between the first node N1 and the fourth node N4. The gate of the fourth transistor T4 may be connected to the second sub-emission control line SEL2. The fourth transistor T4 may be controlled in response to the second emission control signal EM2 applied to the second sub-emission control line SEL2. The fourth transistor T4 may be turned on in response to the second emission control signal EM2 having a turn-on level.

[0100] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. Figure 3The fifth transistor T5 can be configured to switch the electrical connection between the fourth node N4 and the initialization voltage node VINTN. The initialization voltage node VINTN can be configured to transmit the initialization voltage VINT. In an embodiment, the initialization voltage VINT can be Figure 1 , the voltage generator 140 shown in . In other embodiments, the initialization voltage VINT may be provided by an external device (e.g., a power management integrated circuit (PMIC)) that is distinguished from the display device 100. The gate of the fifth transistor T5 may be connected (e.g., electrically connected) to the third sub-gate line SGL3. The fifth transistor T5 may be controlled in response to a third gate signal SCAN3 applied to the third sub-gate line SGL3. The fifth transistor T5 may be turned on in response to the third gate signal SCAN3 having a turn-on level.

[0101] The sixth transistor T6 may be connected between the first power supply voltage node VDDN and the first transistor T1. Figure 3 , the sixth transistor T6 may be configured to switch the electrical connection between the third node N3 and the first transistor T1. The gate of the sixth transistor T6 may be connected to the first sub-emission control line SEL1. The sixth transistor T6 may be controlled in response to the first emission control signal EM1 applied to the first sub-emission control line SEL1. The sixth transistor T6 may be turned on in response to the first emission control signal EM1 having a turn-on level.

[0102] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The first capacitor C1 may include one electrode connected to the second transistor T2 and another electrode connected to the second node N2.

[0103] The second capacitor C2 may be connected between the third node N3 and the second node N2. The second capacitor C2 may include one electrode connected to the second node N2 and another electrode connected to the third node N3.

[0104] Each of the first capacitor C1 and the second capacitor C2 may not be any parasitic capacitor. For example, each of the first capacitor C1 and the second capacitor C2 may be an intentionally formed capacitor.

[0105] As described above, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first capacitors C1 and second capacitors C2. However, embodiments of the present disclosure are not limited thereto. The sub-pixel circuit SPC may be implemented as any of various types of circuits each including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. According to an embodiment of the sub-pixel circuit SPC, the number of sub-gate lines SGL included in the i-th gate line GLi may vary. In some embodiments, the number of sub-emission control lines SEL included in the i-th emission control line ELi may vary.

[0106] refer to Figure 3 , each of the first transistor T1 to the sixth transistor T6 may be a P-type transistor (e.g., a transistor including a P-type semiconductor). At least one of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSEFT). However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the first transistor T1 to the sixth transistor T6 may be replaced by an N-type transistor (e.g., a transistor including an N-type semiconductor).

[0107] In an embodiment, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a polysilicon semiconductor, an oxide semiconductor, or the like.

[0108] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light emitting structure EMS. The light emitting structure EMS may be disposed between the anode electrode AE ​​and the cathode electrode CE. The data voltage Vdata written to the sub-pixel SPij through the data line DLj (e.g., the jth data line DLj) may be reflected as the voltage of the second node N2 through the coupling phenomenon of the first capacitor C1. When the first emission control signal EM1 and the second emission control signal EM2 are enabled to a turn-on level (e.g., a low level), the fourth transistor T4 and the sixth transistor T6 may be turned on. The first transistor T1 may be turned on according to the voltage of the second node N2, and a current (e.g., a driving current) having a magnitude corresponding to the voltage of the second node N2 may flow through the first transistor T1. Therefore, the current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light having a brightness corresponding to the magnitude of the current (which may be referred to as a driving current) flowing therethrough.

[0109] Figure 4 is a system block diagram of the data driver 130 according to an embodiment of the present disclosure.

[0110] refer to Figure 4According to an embodiment of the present disclosure, the data driver 130 may include an analog-to-digital converter (ADC) 410, a memory 420, a temperature image generator 430, an output circuit 440, a first interface (I / F1) 450, a second interface (I / F2) 460, and the like.

[0111] ADC 410 may be configured to convert temperature data TEP into digital temperature data D_TEP corresponding thereto. Temperature data TEP may be input to ADC 410 via a panel line PW (or multiple panel lines PW). In an embodiment where multiple panel lines PW are connected (e.g., electrically connected) to ADC 410, a multiplexer (e.g., an N:1 multiplexer) may be further provided between ADC 410 and multiple panel lines PW. Temperature data TEP may be, for example, an analog voltage.

[0112] The memory 420 may store the digital temperature data D_TEP output from the ADC 410 . The memory 420 may be implemented as, for example, a register. In an embodiment where a plurality of panel lines PW are connected (eg, electrically connected) to the ADC 410 , a plurality of digital temperature data D_TEP may be stored in the memory 420 .

[0113] The temperature image generator 430 may receive digital temperature data D_TEP, image data DATA, and a data control signal DCS. The temperature image generator 430 may obtain the value of the digital temperature data D_TEP with reference to the memory 420. The temperature image generator 430 may synthesize the pre-stored background image BIMG with the image data DATA with reference to the acquired digital temperature data D_TEP. For example, the temperature image generator 430 may display the pre-stored background image BIMG (or the background image BIMG synthesized with the image data DATA) at the periphery of the area where the temperature indicated by the digital temperature data D_TEP is high. For example, the temperature image generator 430 may display the image corresponding to the image data DATA as is at the periphery of the area where the temperature indicated by the digital temperature data D_TEP is low (or within a normal range). The temperature image generator 430 may be controlled in response to the data control signal DCS. The temperature image generator 430 may output the synthesized image data SDATA obtained by synthesizing the background image BIMG and the image data DATA with reference to the digital temperature data D_TEP.

[0114] The output circuit 440 may receive the synthesized image data SDATA. The output circuit 440 may generate a data voltage Vdata corresponding to the synthesized image data SDATA. The data voltage Vdata generated in the output circuit 440 may be output through the data line DL (or a plurality of data lines DL).

[0115] The data control signal DCS may be input to the I / F1 450. The data control signal DCS input to the I / F1 450 may be input to components in the data driver 130 (e.g., the temperature image generator 430 and the output circuit 440, etc.). The I / F1 450 may be implemented as an inter-integrated circuit (I2C) interface. However, the embodiments of the present disclosure are not limited thereto. For example, the I / F1 450 may be implemented as a display port (DP) or an embedded display port (eDP), etc.

[0116] The digital temperature data D_TEP may be output through the I / F1 450. The digital temperature data D_TEP output from the I / F1 450 may be input to the controller 150 (see Figure 1 ). The controller 150 may control the display device 100 in response to the digital temperature data D_TEP (see Figure 1 ) operations.

[0117] In an embodiment of the present disclosure, the data driver 130 can generate the synthesized image data SDATA using the input temperature data TEP. Figure 1 ) is deteriorated and it is difficult to properly transmit the temperature data TEP to the controller 150, the display device 100 (see Figure 1 ) can also easily check the presence of heat in the display device 100. Therefore, the risk that the user using the display device 100 according to the embodiment of the present disclosure will be injured (e.g., burned) can be significantly reduced. This advantage in use can be more effective in a device (e.g., a head-mounted display device, etc.) in which an image is displayed at a position very close to the user (e.g., the user's eyes).

[0118] The image data DATA may be input to the I / F2 460. The image data DATA input to the I / F2 460 may be input to the temperature image generator 430. The I / F2 460 may be implemented as, for example, a low voltage differential signaling (LVDS) interface. However, the embodiments of the present disclosure are not limited thereto. For example, the I / F2 460 may be implemented as a serial peripheral interface (SPI) or a mobile industry processor interface (MIPI), etc.

[0119] Figure 5 is a plan view showing a display panel DP according to an embodiment of the present disclosure.

[0120] Figure 5 The display panel DP shown in FIG. 1 can be applied to Figure 1 The display panel 110 shown in FIG.

[0121] refer to Figure 5, the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be disposed at the periphery of the display area DA (eg, in an edge area).

[0122] The display panel DP may include a substrate SUB, a plurality of pixels PXL disposed (or formed) on the substrate SUB, and a plurality of pads (not shown) disposed (or formed) on the substrate SUB.

[0123] When the display panel DP according to an embodiment of the present disclosure is used as a display screen of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, and the like, the display panel DP may be very close to the user's eyes. In the above-mentioned embodiments, the pixels PXL may need to be integrated at a relatively high density. In order to improve the integration of the pixels PXL, the substrate SUB according to an embodiment of the present disclosure may be provided as a silicon substrate. The pixels PXL or the display panel DP may be formed on a substrate SUB which is a silicon substrate. A display device 100 (see Figure 1 ) can be designated as an OLED-on-silicon (OLEDoS) display device.

[0124] A plurality of pixels PXL may be disposed in the display area DA on the substrate SUB. Figure 5 , the pixels PXL may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments of the present disclosure are not limited thereto. For example, a plurality of pixels PXL according to an embodiment of the present disclosure may be arranged in a zigzag form along the first direction DR1 and the second direction DR2. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0125] Components for controlling the pixels PXL may be disposed in the non-display area NDA on the substrate SUB. Figure 1 Lines of the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn shown in FIG. 5 may be disposed to extend to at least a portion of the non-display area NDA.

[0126] Figure 1 At least one of the gate driving circuit 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 shown in FIG. 1 may be disposed (eg, integrated) in the non-display area NDA of the display panel DP.

[0127] In an embodiment, Figure 1The gate driving circuit 120 shown in FIG. 1 may be formed and disposed in the non-display area NDA of the display panel DP. In another embodiment, the gate driving circuit 120 may be implemented as a separate integrated circuit to be mounted in the non-display area NDA separate from the display panel DP.

[0128] In an embodiment, Figure 1 The temperature sensor 160 shown in FIG. 1 may be disposed in the non-display area NDA to sense the temperature of the display panel DP. The temperature sensor 160 may be disposed at a corner (or vertex) or in an area corresponding thereto. Two or more temperature sensors 160 may be disposed in the display panel DP.

[0129] The pad can connect the display panel DP to the display device 100 (see Figure 1 In an embodiment, voltages and signals necessary for operations of components included in the display panel DP may be provided from the data driver 130 to the plurality of pixels PXL through the pads.

[0130] In an embodiment, the circuit board may be electrically connected to the pad using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC (see Figure 1 ) can be mounted on a circuit board to be electrically connected to the pads.

[0131] In an embodiment, the display area DA may have various shapes. For example, the display area DA may have a closed loop shape including straight or curved edges. For example, the display area DA may have shapes such as polygons, circles, semicircles, and ellipses.

[0132] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may at least partially have a circular display surface. In an embodiment, the display panel DP may be bendable, foldable or rollable. The display panel DP or the substrate SUB may include a rigid material or a flexible material.

[0133] refer to Figure 5 , shows an embodiment in which the temperature sensor 160 is disposed in an area corresponding to a corner of the display area DA. The temperature sensor 160 may include a first temperature sensor 510a, a second temperature sensor 510b, a third temperature sensor 510c, and a fourth temperature sensor 510d (hereinafter, indicated as the first temperature sensor 510a to the fourth temperature sensor 510d) respectively disposed in areas corresponding to the four corners of the display area DA.

[0134] When the display panel DP is viewed in one direction (eg, the third direction DR3), the first temperature sensor 510a may be located in an upper left end area. The first temperature sensor 510a may be located near the first pixel PXLa located at the upper left end in the display area DA.

[0135] When the display panel DP is viewed in one direction (eg, third direction DR3), the second temperature sensor 510b may be located in the upper right end region. The second temperature sensor 510b may be located near the second pixel PXLb located at the upper right end in the display area DA.

[0136] When the display panel DP is viewed in one direction (eg, third direction DR3), the third temperature sensor 510c may be located in a lower left end area. The third temperature sensor 510c may be located near the third pixel PXLc located at the lower left end in the display area DA.

[0137] When the display panel DP is viewed in one direction (eg, the third direction DR3), the fourth temperature sensor 510d may be located in the lower right end region. The fourth temperature sensor 510d may be located near the fourth pixel PXLd located at the lower right end in the display area DA.

[0138] The first to fourth temperature sensors 510a to 510d may output different temperature data TEP according to the temperatures sensed in the corresponding temperature sensors, respectively. The temperature data TEP may be provided in the form of voltage or current, for example, but the embodiments of the present disclosure are not limited thereto. The temperature data TEP may be provided through the panel line PW.

[0139] Each of the first to fourth temperature sensors 510a to 510d may be connected to the panel line PW. Figure 5 , the first to fourth temperature sensors 510 a to 510 d may be connected to the first to fourth panel lines PW1 to PW4 , respectively.

[0140] The first temperature sensor 510a may output first temperature data TEP1 through the first panel line PW1. The second temperature sensor 510b may output second temperature data TEP2 through the second panel line PW2. The third temperature sensor 510c may output third temperature data TEP3 through the third panel line PW3. The fourth temperature sensor 510d may output fourth temperature data TEP4 through the fourth panel line PW4.

[0141] The first to fourth panel lines PW1 to PW4 may be disposed in the non-display area NDA of the substrate SUB. The first to fourth panel lines PW1 to PW4 may be connected to the ADC 410.

[0142] The ADC 410 may convert the temperature data TEP into digital temperature data D_TEP. The digital temperature data D_TEP may be stored in the memory 420. The temperature image generator 430 may generate the synthesized image data SDATA with reference to the digital temperature data D_TEP stored in the memory 420. The output circuit 440 may output the data voltage Vdata corresponding to the synthesized image data SDATA.

[0143] The ADC 410 may sense (eg, sequentially sense according to a predetermined order) the plurality of sensors 510a to 510d. The ADC 410 may output (eg, sequentially output) digital temperature data D_TEP generated by sensing the plurality of sensors 510a to 510d.

[0144] A plurality of digital type temperature data D_TEP generated by sequentially sensing the plurality of sensors 510 a to 510 d may be stored in the memory 420 .

[0145] The temperature image generator 430 can synthesize the background image BIMG (see Figure 4 ) and image data DATA (see Figure 4 ) to generate the synthesized image data SDATA so that the background image BIMG is displayed in a region determined to be at a high temperature among the plurality of digital temperature data D_TEP.

[0146] Figure 6 is an example of an image displayed in the display area DA according to an embodiment of the present disclosure.

[0147] refer to Figure 6 , the reference image DIMG may be displayed in the display area DA. Figure 6 The reference image DIMG shown in FIG. 4 may indicate an image displayed if the temperature at the periphery of the display area DA is within a normal range.

[0148] Figure 7 is through Figure 6 An example of an image obtained by synthesizing the background image BIMG in the corner region of the image shown in .

[0149] refer to Figure 7 , the background image BIMG can be synthesized with the reference image DIMG to be displayed in the upper left corner area of ​​the reference image DIMG. Figure 5, the first temperature sensor 510a located at the upper left end of the display area DA may output the first temperature data TEP1, and the first temperature data TEP1 may be a high temperature (or a temperature exceeding a predetermined threshold temperature). Each of the second temperature data TEP2 to the fourth temperature data TEP4 may be within a normal range (or a temperature equal to or lower than a predetermined threshold temperature). Referring to the memory 420, the temperature image generator 430 may output the synthesized image data SDATA obtained by synthesizing the background image BIMG at the periphery of the area where the first temperature data TEP1 is sensed. Therefore, the background image BIMG may be synthesized with the reference image DIMG to be displayed in the corner area of ​​the upper left end.

[0150] The background image BIMG may be displayed in an area in the display area DA where no main content is displayed. For example, a main content of a text type such as "SDC" may be displayed in a central area of ​​the display area DA. The background image BIMG may be displayed in a region that can be visually displayed to the display device 100 (see Figure 1 ) in an area that provides users with fever-related notifications rather than an area that displays main content.

[0151] Figure 8 is through Figure 6 Another example of an image obtained by synthesizing the background image BIMG in the corner region of the image shown in .

[0152] refer to Figure 8 , the background image BIMG can be synthesized with the reference image DIMG to be displayed in the upper left and lower left corner regions of the reference image DIMG. Figure 5 , the first temperature sensor 510a located at the upper left end of the display area DA may output the first temperature data TEP1, and the first temperature data TEP1 may be a high temperature (or a temperature exceeding a predetermined threshold temperature). The third temperature sensor 510c located at the lower left end of the display area DA may output the third temperature data TEP3, and the third temperature data TEP3 may be a high temperature (or a temperature exceeding a predetermined threshold temperature). Each of the second temperature data TEP2 and the fourth temperature data TEP4 may be within a normal range (or a temperature equal to or lower than a predetermined threshold temperature). Referring to the memory 420, the temperature image generator 430 may output the synthesized image data SDATA obtained by synthesizing the background image BIMG at the periphery of the area where the first temperature data TEP1 and the third temperature data TEP3 are sensed. Therefore, the background image BIMG may be synthesized with the reference image DIMG to be displayed in the corner areas of the upper left end and the lower left end.

[0153] Fig. 9 is through Figure 6An example of an image obtained by synthesizing the background image BIMG in the edge region of the image shown in FIG.

[0154] refer to Fig. 9 , the background image BIMG can be synthesized with the reference image DIMG to be displayed in the edge region edg where the corners of the upper left end and the lower left end are connected to each other. Figure 5 , the first temperature sensor 510a located at the upper left end of the display area DA can output the first temperature data TEP1, and the first temperature data TEP1 can be a high temperature (or a temperature exceeding a predetermined threshold temperature). The third temperature sensor 510c located at the lower left end of the display area DA can output the third temperature data TEP3, and the third temperature data TEP3 can be a high temperature (or a temperature exceeding a predetermined threshold temperature). Each of the second temperature data TEP2 and the fourth temperature data TEP4 can be within a normal range (or a temperature equal to or lower than a predetermined threshold temperature). Referring to the memory 420, the temperature image generator 430 can output the synthesized image data SDATA obtained by synthesizing the background image BIMG in the area where the first temperature data TEP1 and the third temperature data TEP3 are sensed and the edge area where these areas are connected to each other. Therefore, the background image BIMG can be synthesized with the reference image DIMG to be displayed in the edge area edg where the corners of the upper left end and the lower left end are connected to each other.

[0155] However, the embodiments of the present disclosure are not limited thereto. Figure 5 , when temperature data as a high temperature (or a temperature exceeding a predetermined threshold temperature) is generated in any one of the first to fourth temperature sensors 510a to 510d, the background image BIMG may be synthesized with the reference image DIMG to be located in all edge areas edg of the display area DA.

[0156] Fig.10 is through Figure 6 An example of an image obtained by synthesizing the gradation-processed background image BIMG in the corner area of ​​the image shown in .

[0157] refer to Fig.10 The background image BIMG may be synthesized with the reference image DIMG to be displayed in the upper left and lower left corner regions of the reference image DIMG. The background image BIMG may be a gradient processed background image.

[0158] The background image BIMG may be processed differently in gradient according to the temperature of the corresponding area. For example, the gradient light / shadow may be processed differently according to the temperature sensed by the temperature sensor located near the corresponding area.

[0159] Further reference to the above Figure 5 , the first temperature sensor 510a located at the upper left end of the display area DA can output the first temperature data TEP1, and the first temperature data TEP1 can be a high temperature (or a temperature exceeding a predetermined threshold temperature). Each of the second temperature data TEP2 to the fourth temperature data TEP4 can be within a normal range (or a temperature equal to or lower than a predetermined threshold temperature). Referring to the memory 420, the temperature image generator 430 can output the synthesized image data SDATA obtained by synthesizing the background image BIMG at the periphery of the area where the first temperature data TEP1 is sensed. Therefore, the background image BIMG can be synthesized with the reference image DIMG to be displayed in the corner area of ​​the upper left end. In the above-mentioned embodiment, the size and light / shadow of the gradient, etc. can be processed differently according to the value of the first temperature data TEP1.

[0160] Fig.11 It is shown Figure 5 8 is an exploded perspective view of a portion of the display panel DP shown in FIG.

[0161] exist Fig.11 In the embodiment, for the sake of clarity and brief description, the display panel DP is schematically shown. Figure 5 The portions corresponding to the first pixel PXL1 and the second pixel PXL2 among the pixels PXL shown in FIG. The portions corresponding to other pixels of the display panel DP may also be configured in the same manner.

[0162] refer to Figure 5 and Fig.11 , the first pixel PXL1 and the second pixel PXL2 may be adjacent to each other in the second direction DR2. Each of the first pixel PXL1 and the second pixel PXL2 may include a plurality of sub-pixels. Fig.11 , each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiments of the present disclosure are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0163] exist Fig.11 , it is shown that when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (e.g., perpendicular to the first direction DR1 and the second direction DR2), the first sub-pixel SP1 to the third sub-pixel SP3 may have a quadrilateral shape and have the same size. However, the embodiments of the present disclosure are not limited thereto. The first sub-pixel SP1 to the third sub-pixel SP3 may be modified to have various shapes.

[0164] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a thin film encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0165] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium, or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0166] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements and lines, etc. The conductive pattern may include copper, but the embodiments of the present disclosure are not limited thereto.

[0167] The circuit element may include a sub-pixel circuit SPC (see FIG. Figure 2 ). The sub-pixel circuit SPC may include at least two transistors and at least one capacitor. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion (e.g., the channel region). In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. The capacitor may include electrodes spaced apart from each other (e.g., facing each other). For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, the capacitor may include electrodes spaced apart from each other in a third direction DR3, with an insulating layer interposed between the electrodes.

[0168] The lines of the pixel circuit layer PCL may include signal lines (eg, gate lines, emission control lines, and data lines, etc.) connected to each of the first to third sub-pixels SP1 to SP3. The lines may also include lines connected to Figure 2 The line may also include a line connected to the first power supply voltage node VDDN shown in FIG. Figure 2 The line of the second supply voltage node VSSN is shown in .

[0169] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0170] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may be connected to (eg, contact) a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light. However, embodiments of the present disclosure are not limited thereto.

[0171] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each of the anode electrodes AE. The opening OP of the pixel defining layer PDL may be an emission region of each of the first to third subpixels SP1 to SP3.

[0172] In an embodiment, the pixel defining layer PDL may include an inorganic material. In the above-mentioned embodiment, the pixel defining layer PDL may include an inorganic layer (eg, a plurality of stacked inorganic layers). For example, the pixel defining layer PDL may include silicon oxide (SiO x ) or silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic layer including an organic material. However, as described above, the material constituting the pixel defining layer PDL according to the embodiment of the present disclosure is not limited.

[0173] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed through the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include at least one functional layer. The light emitting structure EMS may include, for example, a functional layer (such as a light generating layer (or light emitting layer) (not shown) configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes).

[0174] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL. In an embodiment, the light emitting structure EMS may be disposed as a whole on top of the pixel defining layer PDL. For example, the light emitting structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. In the above-mentioned embodiment, at least some of the functional layers in the light emitting structure EMS may be cut or bent at the boundary between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiments of the present disclosure are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the portions may be disposed in the opening OP of the pixel defining layer PDL.

[0175] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend throughout the first to third subpixels SP1 to SP3. The cathode electrode CE may be provided as a common electrode commonly connected to the first to third subpixels SP1 to SP3.

[0176] The cathode electrode CE may have light transmittance. For example, the cathode electrode CE may be a thin metal layer having a thickness to the extent that the light emitted from the light emitting structure EMS can be transmitted through. The cathode electrode CE may be formed of a metal material to have a relatively thin thickness, or may be formed of a conductive material having light transmittance (e.g., transparency). In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. However, as described above, the material constituting the cathode electrode CE according to an embodiment of the present disclosure is not limited. The cathode electrode CE may be used as a semi-reflecting mirror that allows light emitted from the light emitting structure EMS to be partially transmitted through and allows light emitted from the light emitting structure EMS to be partially reflected.

[0177] It can be understood that any one of the anode electrodes AE, the portion of the light emitting structure EMS overlapping therewith, and the portion of the cathode electrode CE overlapping therewith constitute a light emitting element LD (see Figure 2 ). Each of the light emitting elements LD of the first to third sub-pixels SP1 to SP3 may include an anode electrode AE, a portion of the light emitting structure EMS overlapping therewith, and a portion of the cathode electrode CE overlapping therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE may be transferred to the light emitting structure EMS to form excitons, and light may be generated when the excitons change from an excited state to a ground state. The brightness of the light may be determined according to the amount of current flowing through the light emitting structure EMS. The wavelength band of the generated light may be determined according to the configuration of the light emitting structure EMS.

[0178] The thin film encapsulation layer TFE may be disposed above the cathode electrode CE. The thin film encapsulation layer TFE may cover the light emitting element layer LDL or the pixel circuit layer PCL. The thin film encapsulation layer TFE may be configured to prevent oxygen or moisture from penetrating into the light emitting element layer LDL. In an embodiment, the thin film encapsulation layer TFE may include a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, as described above, the materials of the organic layer and the inorganic layer of the thin film encapsulation layer TFE are not limited.

[0179] In order to improve the encapsulation efficiency of the thin film encapsulation layer TFE, the thin film encapsulation layer TFE may further include aluminum oxide (AlO x ). The thin film including aluminum oxide may be located on the top surface of the thin film encapsulation layer TFE facing the optical function layer OFL, or on the bottom surface of the thin film encapsulation layer TFE facing the light emitting element layer LDL. The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) process. However, the embodiments of the present disclosure are not limited thereto. The thin film encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0180] The optical function layer OFL may be disposed on the thin film encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA. In an embodiment, the optical function layer OFL may be attached to the thin film encapsulation layer TFE through an adhesive layer (not shown). For example, the optical function layer OLF may be manufactured separately to be attached to the thin film encapsulation layer TFE through an adhesive layer. The adhesive layer may also perform the function of protecting the lower layer including the thin film encapsulation layer TFE.

[0181] The color filter layer CFL may be disposed between the thin film encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the light emitting structure EMS, thereby selectively outputting light having a wavelength band corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the color filters CF may allow light having a wavelength band corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter corresponding to the third sub-pixel SP3 may allow blue light to pass through. Depending on the light emitted from the light emitting structure EMS in each sub-pixel, at least some of the color filters CF may be omitted. In some embodiments, the color filter layer CFL may be omitted. In an embodiment, the color filters CF may overlap each other (e.g., partially overlap) in a boundary region between the first sub-pixel SP1 to the third sub-pixel SP3. In other embodiments, the color filters CF may be spaced apart from each other in boundary regions between the first to third sub-pixels SP1 to SP3 , and a black matrix may be provided between the color filters CF.

[0182] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may output light emitted from the light emitting structure EMS along a desired path, thereby improving light emitting efficiency. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0183] In an embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be displaced in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel defining layer PDL. Specifically, in the central area of ​​the display area DA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned with or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In an area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be displaced from the center of the opening OP of the pixel defining layer PDL in a plane direction. For example, in an area of ​​the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light emitting structure EMS may be effectively output in the normal direction of the display surface. At the outer portion of the display area DA, the light emitted from the light emitting structure EMS may be effectively output in a direction inclined at a predetermined angle relative to the normal direction.

[0184] The overcoat layer OC may be disposed above the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the thin film encapsulation layer TFE, the light emitting structure EMS, or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the underlying layers from external substances such as dust and moisture.

[0185] The cover window CW may be disposed on the overcoat layer OC. The cover window CW may be configured to protect its lower layer. In some embodiments, the cover window CW may include glass and metal having light transmittance (eg, transparency), etc. However, the embodiments of the present disclosure are not limited thereto.

[0186] Further references Figure 5, the temperature sensor 160 according to an embodiment of the present disclosure may be disposed in the same layer as the pixel circuit layer PCL. In some embodiments, the temperature sensor 160 may be disposed in the same layer as the light emitting element layer LDL. In some embodiments, the temperature sensor 160 may be disposed in the same layer as the thin film encapsulation layer TFE. In some embodiments, the temperature sensor 160 may be disposed in the same layer as the optical function layer OFL. In some embodiments, the temperature sensor 160 may be covered by an outer coating OC. In some embodiments, the temperature sensor 160 may be positioned while overlapping with the cover window CW.

[0187] Fig.12 It is shown Fig.11 A plan view of an embodiment of any one of the pixels shown in .

[0188] exist Fig.12 In order to make the description clear and brief, the schematic diagram is shown. Fig.11 The first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 shown in FIG. The other pixels may be configured identically to the first pixel PXL1. The first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0189] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA at the periphery of the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA at the periphery of the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA at the periphery of the third emission area EMA3.

[0190] The first emission area EMA1 may be where light is emitted from the light emitting structure EMS (see Fig.11 ) may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Fig.11 As described above, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0191] Fig.13 It is shown along Fig.12 2 is a cross-sectional view of an example of a pixel taken along line II′ shown in FIG.

[0192] refer to Fig.13, a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0193] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, or silicon germanium.

[0194] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include at least some of the circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (see FIG. 1 ) included in the first sub-pixel SP1. Figure 2 ). The transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Fig.13 , for clarity and brief description, one of the transistors of each sub-pixel is shown, and other circuit elements of the sub-pixel circuit SPC are not shown.

[0195] The transistor T_SP1 of the first subpixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0196] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed in the well WL to be spaced apart from each other. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0197] The gate electrode GE may be positioned while overlapping (e.g., overlapping in the third direction DR3) the channel region between the source region SRA and the drain region DRA. The gate electrode GE may be included in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL (or the channel region) by an insulating material (e.g., an insulating material such as a gate insulating layer GI). The gate electrode GE may include a conductive material.

[0198] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be connected (e.g., electrically connected) to the drain region DRA by a drain connection portion DRC penetrating one or more insulating layers. The second conductive pattern CP2 may be connected (e.g., electrically connected) to the source region SRA by a source connection portion SRC penetrating one or more insulating layers.

[0199] When the gate electrode GE, the first conductive pattern CP1, and the second conductive pattern CP2 are connected to other circuit elements or lines, the transistor T_SP1 of the first sub-pixel SP1 may be provided as a sub-pixel circuit SPC (see Figure 2 ) of any transistor.

[0200] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured identically to the transistor T_SP1 of the first subpixel SP1 .

[0201] Similar to as described above, the substrate SUB or the pixel circuit layer PCL may include circuit elements of each of the first to third sub-pixels SP1 to SP3 .

[0202] The via layer VIAL may be disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and may have an overall flat surface (eg, a flat top surface). The via layer VIAL may be configured to flatten the step difference on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the embodiments of the present disclosure are not limited thereto.

[0203] The light emitting element layer LDL may be disposed on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0204] The first to third reflective electrodes RE1 to RE3 are respectively disposed in the first to third subpixels SP1 to SP3 on the via layer VIAL. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element disposed in the pixel circuit layer PCL through a via hole penetrating the via layer VIAL.

[0205] The first to third reflective electrodes RE1 to RE3 may be used as a reflector (e.g., a total reflector) that reflects light emitted from the light emitting structure EMS toward the display surface (or the cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but the embodiments of the present disclosure are not limited thereto.

[0206] In an embodiment, a buffer electrode may be disposed on the bottom of each of the first to third reflective electrodes RE1 to RE3. The buffer electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The buffer electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiments of the present disclosure are not limited thereto. In an embodiment, the corresponding reflective electrode may be located between multiple layers of the buffer electrode.

[0207] At least one of the first to third reflective electrodes RE1 to RE3 may be disposed above the buffer pattern BFP. The buffer pattern BFP may be configured to control the position of the corresponding reflective electrode (e.g., the position of the reflective electrode in the third direction DR3). The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the embodiments of the present disclosure are not limited thereto. Fig.13 When the buffer pattern BFP is set, the position of the corresponding reflective electrode (for example, the height of the reflective electrode in the third direction DR3) can be adjusted. Fig.13 , the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust a height of the first reflective electrode RE1 .

[0208] The first to third reflective electrodes RE1 to RE3 may be used as full reflectors, and the cathode electrode CE may be used as a half reflector. The light emitted from the light emitting structure EMS may be amplified by at least partially reciprocating between the corresponding reflective electrode and the cathode electrode CE. The above phenomenon may be understood as a resonance phenomenon. The amplified light may be output through the cathode electrode CE. The distance between each reflective electrode and the cathode electrode CE may be understood as the resonance distance of the light emitted from the light emitting structure EMS. The resonance distance may be adjusted by the buffer pattern BFP.

[0209] refer to Fig.13, through the buffer pattern BFP, the first subpixel SP1 can have a resonance distance shorter than the resonance distance of another subpixel. Light of a specific band (e.g., red) can be effectively and efficiently amplified by the adjusted resonance distance. Therefore, the first subpixel SP1 can effectively and efficiently output light of the corresponding band.

[0210] refer to Fig.13 , it is shown that the buffer pattern BFP is provided for the first sub-pixel SP1 and is not provided for the second sub-pixel SP2 and the third sub-pixel SP3. However, the embodiments of the present disclosure are not limited thereto. A buffer pattern may even be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE. The distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0211] The planarization layer PLNL may be configured to planarize the step difference between the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL integrally covers the first to third reflective electrodes RE1 to RE3 and the via layer VIAL. The planarization layer PLNL may have a flat surface (e.g., a top surface in the third direction DR3). In an embodiment, the planarization layer PLNL may be omitted.

[0212] The first to third anode electrodes AE1 to AE3 may be disposed on the planarization layer PLNL. The first to third anode electrodes AE1 to AE3 may overlap the first to third reflective electrodes RE1 to RE3, respectively (e.g., overlap the first to third reflective electrodes RE1 to RE3, respectively, in the third direction DR3). When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may have the same Fig.12The shapes of the first emission area EMA1 to the third emission area EMA3 shown in FIG. The first anode electrode AE1 to the third anode electrode AE3 may be connected to the first reflective electrode RE1 to the third reflective electrode RE3, respectively. The first anode electrode AE1 may be connected (e.g., electrically connected) to the first reflective electrode RE1 through a first via hole VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 may be connected (e.g., electrically connected) to the second reflective electrode RE2 through a second via hole VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 may be connected (e.g., electrically connected) to the third reflective electrode RE3 through a third via hole VIA3 penetrating the planarization layer PLNL.

[0213] In an embodiment, the first to third anode electrodes AE1 to AE3 may include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first to third anode electrodes AE1 to AE3 are not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0214] The pixel defining layer PDL may be disposed on the first to third anode electrodes AE1 to AE3 and portions of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a portion of each of the first to third anode electrodes AE1 to AE3. The opening OP of the pixel defining layer PDL may define an emission region from which light is emitted from each of the first to third sub-pixels SP1 to SP3. The pixel defining layer PDL may be disposed on Fig.12 The pixel defining layer PDL may define the non-emission area NEA shown in FIG. Fig.12 The first emission area EMA1 to the third emission area EMA3 shown in FIG.

[0215] In an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked sequentially, and each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon oxynitride. However, the embodiments of the present disclosure are not limited thereto. The first to third inorganic insulating layers may have a stepped section in an area adjacent to the opening OP.

[0216] The spacer SPR may be provided (or disposed) in the boundary area BDA between the sub-pixels adjacent to each other. Figure 1 In each boundary region between the sub-pixels SP shown in FIG.

[0217] The spacer SPR may form a discontinuous portion in the light emitting structure in the boundary area BDA. For example, the light emitting structure EMS may be cut or bent by the spacer SPR in the boundary area BDA.

[0218] The spacer SPR may be provided in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more trenches TRCH1 and TRCH2 as the spacer SPR. Fig.13 As shown in , one or more grooves TRCH1 and TRCH2 may penetrate the pixel defining layer PDL and partially penetrate at least a portion of the planarization layer PLNL. In other embodiments, one or more grooves TRCH1 and TRCH2 may penetrate the pixel defining layer PDL and the planarization layer PLNL and partially penetrate at least a portion of the via layer VALL. In yet another embodiment, one or more grooves TRCH1 and TRCH2 may at least partially penetrate at least a portion of the planarization layer PLNL or at least a portion of the via layer VIAL, and at least a portion of the pixel defining layer PDL may be disposed in one or more grooves TRCH1 and TRCH2.

[0219] refer to Fig.13 , it is shown that a plurality of grooves TRCH1 and TRCH2 (e.g., a first groove TRCH1 and a second groove TRCH2) are provided (or arranged) in the boundary area BDA. However, the embodiments of the present disclosure are not limited thereto. For example, the pixel defining layer PDL may include a single (or one) groove in the boundary area BDA. For example, the pixel defining layer PDL may include three or more grooves in the boundary area BDA.

[0220] Due to the first trench TRCH1 and the second trench TRCH2, a gap as a discontinuous portion may be formed in the boundary area BDA. Fig.13 , discontinuities such as the first void VD1 and the second void VD2 may be formed (or provided) in the light emitting structure EMS. Some of the plurality of layers stacked in the light emitting structure EMS may be cut or bent by the first void VD1 and the second void VD2. For example, at least one charge generation layer (CGL) included in the light emitting structure EMS may be cut by the first void VD1 and the second void VD2. Due to the first trench TRCH1 and the second trench TRCH2, at least a portion of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3 may be partially separated.

[0221] refer to Fig.13 , it is shown that the first void VD1 and the second void VD2 are formed in the light emitting structure EMS in the boundary area BDA. However, this is merely illustrative, and the embodiments of the present disclosure are not limited thereto. For example, a concave valley may be formed in the light emitting structure EMS in the boundary area BDA. The discontinuity formed in the light emitting structure EMS may be variously changed according to the shapes of the first trench TRCH1 and the second trench TRCH2.

[0222] In embodiments, the light emitting structure EMS may be formed by processes such as vacuum deposition or inkjet printing. In the above embodiments, the light emitting structure EMS (or the same material as the light emitting structure EMS) may be located on the bottom surface adjacent to the via layer VIAL in the first and second trenches TRCH1 and TRCH2.

[0223] The spacer SPR may be modified in various ways so that the light emitting structure EMS may have a discontinuous portion in the boundary area BDA. In an embodiment, in the absence of the first trench TRCH1 and the second trench TRCH2, an inorganic insulating pattern additionally stacked on the pixel defining layer PDL may be provided in the boundary area BDA. The width of the inorganic insulating pattern at the uppermost portion among the additionally stacked inorganic insulating patterns may be greater than the width of the inorganic insulating pattern directly disposed below the inorganic insulating pattern at the uppermost portion. For example, in an embodiment in which the first inorganic insulating pattern to the third inorganic insulating pattern are sequentially stacked from the pixel defining layer PDL in the boundary area BDA, the width of the third inorganic insulating pattern disposed at the uppermost portion may be greater than the width of the second inorganic insulating layer directly disposed below the third inorganic insulating pattern. For example, the pixel defining layer PDL may have a section having a "T" shape or an "I" shape in the boundary area BDA. According to the pixel defining layer PDL having a "T" shape or an "I" shape, at least some of the multiple layers included in the light emitting structure EMS may be partially cut or bent in the boundary area BDA.

[0224] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed through the opening OP of the pixel defining layer PDL (see Fig.11) on. The light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and be integrally disposed in the first to third sub-pixels SP1 to SP3. As described above, at least a portion of the light emitting structure EMS may be partially cut or bent in the boundary area BDA by the partition SPR. Therefore, in the operation of the display panel PD, the magnitude of the current (e.g., leakage current) leaking from each of the first to third sub-pixels SP1 to SP3 to the sub-pixels adjacent thereto through the layers included in the light emitting structure EMS may be reduced (or removed). Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0225] The cathode electrode CE may be disposed above the light emitting structure EMS. The cathode electrode CE may be commonly provided (or disposed) in the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that allows light emitted from the light emitting structure EMS to partially transmit therethrough and partially reflect.

[0226] The first anode electrode AE1, the portion of the light emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, the portion of the light emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, the portion of the light emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may constitute a third light emitting element LD3.

[0227] A thin film encapsulation layer TFE may be disposed over the cathode electrode CE. The thin film encapsulation layer TFE may prevent oxygen or moisture from penetrating into the light emitting element layer LDL.

[0228] The optical function layer OFL may be disposed on the thin film encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA. In an embodiment, the optical function layer OFL may be attached to the thin film encapsulation layer TFE through an adhesive layer APL. For example, the optical function layer OFL may be manufactured separately to be attached to the thin film encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform a function of protecting the lower layer including the thin film encapsulation layer TFE.

[0229] The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may allow light of different wavelength bands to pass through. For example, the first to third color filters CF1 to CF3 may allow red light, green light, and blue light to pass through, respectively.

[0230] In an embodiment, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided (or disposed) between the first to third color filters CF1 to CF3.

[0231] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 may output light emitted from the first to third light-emitting elements LD1 to LD3, respectively, along intended paths, thereby improving light emission efficiency.

[0232] The outer coating OC may be disposed above the lens array LA. The outer coating OC may include various materials suitable for protecting its lower layer from external substances such as dust and moisture. For example, the outer coating OC may include an inorganic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiments of the present disclosure are not limited thereto. The outer coating OC may have a refractive index less than the refractive index of the lens array LA. The refractive index (e.g., absolute refractive index) of the outer coating OC may be a first refractive index. The first refractive index may have a range of, for example, about 1.2 to about 1.4, but the embodiments of the present disclosure are not limited thereto.

[0233] The cover window CW may be disposed on the outer coating OC. The cover window CW may have a refractive index greater than the refractive index of the outer coating OC. In some embodiments, the cover window CW may include glass, metal, and the like. However, the embodiments of the present disclosure are not limited thereto. The cover window CW may be configured to protect a component disposed on its bottom. The refractive index (e.g., absolute refractive index) of the cover window CW may be a second refractive index. The second refractive index may have a range of, for example, about 1.5 to about 1.9, but the embodiments of the present disclosure are not limited thereto. The cover window CW may be designated as encapsulation glass. The cover window CW may be in contact with the outside (e.g., air).

[0234] Fig.14 It is shown Fig.13 2 is a cross-sectional view of an embodiment of a light emitting structure EMS included in any one of the first to third light emitting elements LD1 to LD3 shown in FIG.

[0235] refer to Fig.14 The light emitting structure EMS may have a series structure in which the first light emitting unit EU1 and the second light emitting unit EU2 are stacked. Fig.13 Each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 is configured substantially identically.

[0236] Each of the first light emitting unit EU1 and the second light emitting unit EU2 may include at least one light emitting layer that generates light according to an applied current. The first light emitting unit EU1 may include a first light emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light emitting unit EU2 may include a second light emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0237] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a functional layer such as a hole buffer layer and an electron blocking layer. Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration. In some embodiments, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may have a different configuration.

[0238] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may also include a functional layer such as an electron buffer layer and a hole blocking layer. Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration. In some embodiments, each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may have a different configuration.

[0239] The connection layer may be connected between the first light emitting unit EU1 and the second light emitting unit EU2. The connection layer may be provided in the form of, for example, a charge generation layer CGL. In an embodiment, the charge generation layer CGL may have a stacked structure of a P dopant layer and an N dopant layer. For example, the P dopant layer may include a P-type dopant such as HAT-CN, TCNQ, or NDP-9. For example, the N dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or any combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0240] In an embodiment, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of different colors (or different wavelength bands). The light emitted from the first light-emitting layer EML1 and the second light-emitting layer EML2, respectively, may be mixed together to be regarded as white light by the user. For example, the first light-emitting layer EML1 may generate blue light, and the second light-emitting layer EML2 may generate yellow light. In an embodiment, the second light-emitting layer EML2 may include a first sub-light-emitting layer (not shown) configured to generate red light and a second sub-light-emitting layer (not shown) configured to generate green light. The red light and the green light may be mixed together to provide yellow light. An intermediate layer configured to perform a function of transporting holes or a function of blocking the transport of electrons may be further disposed between the first sub-light-emitting layer and the second sub-light-emitting layer.

[0241] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may generate light of the same color.

[0242] The light emitting structure EMS may be formed through a process such as vacuum deposition or inkjet printing, but the embodiments of the present disclosure are not limited thereto.

[0243] Fig.15 It is shown Fig.13 2 is a cross-sectional view of another embodiment of the light emitting structure EMS′ included in any one of the first to third light emitting elements LD1 to LD3 shown in FIG.

[0244] refer to Fig.15 , the light emitting structure EMS' may be a series structure of stacking the first light emitting unit EU1' to the third light emitting unit EU3'. The light emitting structure EMS' may be Fig.13 Each of the first to third light emitting elements LD1 to LD3 shown in FIG. 1 is configured substantially identically.

[0245] Each of the first to third light-emitting units EU1' to EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0246] Each of the first hole transport unit HTU1' to the third hole transport unit HTU3' may include at least one of a hole injection layer and a hole transport layer. In some embodiments, each of the first hole transport unit HTU1' to the third hole transport unit HTU3' may also include at least one of a hole buffer layer and an electron blocking layer. In some embodiments, the first hole transport unit HTU1' to the third hole transport unit HTU3' may have the same configuration. Alternatively, the first hole transport unit HTU1' to the third hole transport unit HTU3' may have different configurations.

[0247] Each of the first electron transport unit ETU1' to the third electron transport unit ETU3' may include at least one of an electron injection layer and an electron transport layer. In some embodiments, each of the first electron transport unit ETU1' to the third electron transport unit ETU3' may also include at least one of an electron buffer layer and a hole blocking layer. The first electron transport unit ETU1' to the third electron transport unit ETU3' may have the same configuration. Optionally, the first electron transport unit ETU1' to the third electron transport unit ETU3' may have different configurations.

[0248] The first charge generation layer CGL1' may be disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' may be disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0249] In an embodiment, the first to third light-emitting layers EML1' to EML3' may generate light of different colors. The light emitted from the first to third light-emitting layers EML1' to EML3' may be mixed together to be viewed as white light by a user. For example, the first light-emitting layer EML1' may generate light of a first wavelength band (e.g., blue), the second light-emitting layer EML2' may generate light of a second wavelength band (e.g., green), and the third light-emitting layer EML3' may generate light of a third wavelength band (e.g., red).

[0250] In other embodiments, at least two light-emitting layers of the first to third light-emitting layers EML1 ′ to EML3 ′ may generate light of the same wavelength band (or the same color).

[0251] With Fig.14 and Fig.15 Different from what is shown in Fig.13 The light emitting structure EMS shown in FIG. 1 may include one light emitting unit EU in each of the first to third light emitting elements LD1 to LD3. In the above embodiment, the light emitting unit EU included in each of the first to third light emitting elements LD1 to LD3 may be configured to emit light of different wavelength bands (or different colors). Fig.13 , the light emitting unit EU of the first light emitting element LD1 can emit light of a first wavelength band (e.g., red), the light emitting unit EU of the second light emitting element LD2 can emit light of a second wavelength band (e.g., green), and the light emitting unit EU of the third light emitting element LD3 can emit light of a third wavelength band (e.g., blue). Fig.13 Unlike shown in , the light emitting structures EMS of the first to third sub-pixels SP1 to SP3 may be separated from each other. Each of the light emitting structures EMS may be disposed in the opening OP of the pixel defining layer PDL. In the above-described embodiments, at least some of the color filters CF1 to CF3 may be omitted.

[0252] Fig.16 It is shown Figure 5 A plan view of another embodiment of any one of the pixels PXL shown in FIG.

[0253] refer to Fig.16 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0254] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' at the periphery of the first emission area EMA1'. The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' at the periphery of the second emission area EMA2'. The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' at the periphery of the third emission area EMA3'.

[0255] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2 (or adjacent to each other in the second direction DR2). The third subpixel SP3' may be disposed in the first direction DR1 relative to each of the first subpixel SP1' and the second subpixel SP2' (or adjacent to each of the first subpixel SP1' and the second subpixel SP2' in the first direction DR1).

[0256] The area of ​​the second sub-pixel SP2' may be larger than the area of ​​the first sub-pixel SP1'. The area of ​​the third sub-pixel SP3' may be larger than the area of ​​the second sub-pixel SP2'. The area of ​​the second emission area EMA2' as the emission area of ​​the second sub-pixel SP2' may be larger than the area of ​​the first emission area EMA1' as the emission area of ​​the first sub-pixel SP1'. The area of ​​the third emission area EMA3' as the emission area of ​​the third sub-pixel SP3' may be larger than the area of ​​the second emission area EMA2' as the emission area of ​​the second sub-pixel SP2'. However, the embodiments of the present disclosure are not limited thereto. For example, the areas of the first sub-pixel SP1' and the second sub-pixel SP2' may be the same (or substantially the same), and the area of ​​the third sub-pixel SP3' may be larger than the area of ​​each of the first sub-pixel SP1' and the second sub-pixel SP2'. As described above, in some embodiments, the area of ​​each of the first to third sub-pixels SP1' to SP3' may be variously modified.

[0257] Fig.17 It is shown Figure 5 A plan view of yet another embodiment of any one of the pixels PXL shown in FIG.

[0258] refer to Fig.17 , the first pixel PXL1" may include the first sub-pixel SP1" to the third sub-pixel SP3". The first sub-pixel SP1" may include the first emission area EMA1" and the non-emission area NEA" at the periphery of the first emission area EMA1". The second sub-pixel SP2" may include the second emission area EMA2" and the non-emission area NEA" at the periphery of the second emission area EMA2". The third sub-pixel SP3" may include the third emission area EMA3" and the non-emission area NEA" at the periphery of the third emission area EMA3".

[0259] When viewed in one direction (eg, the third direction DR3), the first to third sub-pixels SP1″ to SP3″ may have a polygonal shape. For example, the shape of each of the first to third sub-pixels SP1″ to SP3″ may be as follows: Fig.17 The hexagonal shape shown in .

[0260] When viewed in one direction (e.g., the third direction DR3), each of the first to third emission areas EMA1″ to EMA3″ may have a circular shape. However, embodiments of the present disclosure are not limited thereto. For example, each of the first to third emission areas EMA1″ to EMA3″ may have a polygonal shape.

[0261] The first subpixel SP1" and the third subpixel SP3" may be arranged in the first direction DR1 (or adjacent to each other in the first direction DR1). The second subpixel SP2" may be disposed in a direction (or a diagonal direction) inclined at an acute angle based on the second direction DR2 with respect to the first subpixel SP1".

[0262] exist Fig.12 , Fig.16 and Fig.17 The arrangement of the sub-pixels shown in the figure is merely illustrative, and the embodiments of the present disclosure are not limited thereto. Each pixel may include two or more sub-pixels, and the sub-pixels in a pixel may be arranged in various ways. Each of the sub-pixels may have various shapes, and the emission area of ​​the sub-pixels may have various shapes.

[0263] Fig.18 is a block diagram illustrating an embodiment of a display system 1800 according to an embodiment of the present disclosure.

[0264] refer to Fig.18 , the display system 1800 may include a processor 1810 and one or more display devices 1820 and 1830 .

[0265] The processor 1810 may perform various tasks and various calculations. In an embodiment, the processor 1810 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, and a central processing unit (CPU), etc. The processor 1810 may be connected to other components of the display system 1800 through a bus system to control the components of the display system 1800.

[0266] exist Fig.18, it is shown that the display system 1800 includes a first display device 1820 and a second display device 1830. The processor 1810 may be connected to the first display device 1820 through a first channel CH1, and connected to the second display device 1830 through a second channel CH2.

[0267] Through the first channel CH1, the processor 1810 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1820. The first display device 1820 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 The first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 The input image data IMG and the control signal CTRL shown in .

[0268] Through the second channel CH2, the processor 1810 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1830. The second display device 1830 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 The image data IMG and the control signal CTRL shown in FIG.

[0269] The display system 1800 may include a computing system for providing an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, or an ultra mobile computer (UMPC). In addition, the display system 1800 may include at least one of a head mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0270] Fig.19 It is shown Fig.18 A perspective view of an embodiment of a display system 1800 is shown in FIG.

[0271] refer to Fig.19 , Fig.18 The display system 1800 shown in FIG. 1 may be applied to a head-mounted display device 1900. The head-mounted display device 1900 may be a wearable electronic device that can be worn on a user's head.

[0272] The head-mounted display device 1900 may include a head-mounted band 1910 and a display device housing 1920. The head-mounted band 1910 may be connected to the display device housing 1920. The head-mounted band 1910 may include a horizontal band or a vertical band for fixing the head-mounted display device 1900 to the user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper part of the user's head. However, the embodiments of the present disclosure are not limited thereto. For example, the head-mounted band 1910 may be implemented in the form of a glasses frame or a helmet, etc.

[0273] The display device receiving housing 1920 can receive Fig.18 The first display device 1820 and the second display device 1830 shown in FIG. The display device receiving housing 1920 can also receive Fig.18 Processor 1810 shown in .

[0274] Fig. 20 19 is a diagram showing an embodiment of a head mounted display device 1900 worn by a user.

[0275] refer to Fig. 20 , the first display device 1820 (see Fig.18 ) of the first display panel DP1 and the second display device 1830 (see Fig.18 ) may be provided in the head mounted display device 1900. The head mounted display device 1900 may further include one or more lenses. For example, the head mounted display device 1900 may include a left eye lens LLNS and a right eye lens RLNS.

[0276] In the display device accommodating housing 1920, a right eye lens RLNS may be disposed between the first display panel DP1 and the right eye (or one eye) of the user USR. In the display device accommodating housing 1920, a left eye lens LLNS may be disposed between the second display panel DP2 and the left eye (or the other eye) of the user USR.

[0277] The image output from the first display panel DP1 may be observed by the right eye of the user USR through the right eye lens RLNS. The right eye lens RLNS may refract the light emitted from the first display panel DP1 to face the right eye of the user USR. The right eye lens RLNS may perform an optical function for adjusting the observation distance between the first display panel DP1 and the right eye of the user USR.

[0278] The image output from the second display panel DP2 can be observed by the left eye of the user USR through the left eye lens LLNS. The left eye lens LLNS can refract the light emitted from the second display panel DP2 to face the left eye of the user USR. The left eye lens LLNS can perform an optical function for adjusting the observation distance between the second display panel DP2 and the left eye of the user USR.

[0279] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped portion. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In the above-described embodiment, each of the first display panel DP1 and the second display panel DP2 may output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images may be observed by the user while passing through the corresponding sub-regions, respectively.

[0280] In the case where heat is generated in any one of the first display panel DP1 and the second display panel DP2, the background image BIMG (see FIG. 1 ) may be displayed only in any one of the first display panel DP1 and the second display panel DP2. Figure 4 The user USR can recognize that there is heat in the first display panel DP1 by synthesizing the background image BIMG and the image displayed on the right eye. Alternatively, the user USR can recognize that there is heat in the second display panel DP2 by synthesizing the background image BIMG and the image displayed on the left eye.

[0281] In the display device, the driving method of the display device, and the head-mounted display device according to the present disclosure, even when the connection between the temperature sensor and the controller is deteriorated, the user can visually recognize that heating occurs.

[0282] Depending on the temperatures of the first display device and the second display device, an image obtained by synthesizing a background image may be displayed in any one of the first display device and the second display device, and an image obtained by not synthesizing the background image may be displayed in the other of the first display device and the second display device.

[0283] Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the scope and spirit of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: A display panel comprising a display area and a non-display area at the periphery of the display area, wherein a plurality of data lines and a plurality of pixels connected to the plurality of data lines are arranged in the display area; a temperature sensor disposed in the non-display area of ​​the display panel, the temperature sensor being configured to output temperature data corresponding to a sensed temperature; and The data driver is configured to convert the temperature data into digital temperature data, synthesize a background image based on the digital temperature data, and convert synthesized image data obtained by synthesizing the background image into data voltages, thereby outputting the data voltages to the plurality of data lines.

2. The display device according to claim 1, wherein: The data driver is connected to a panel line disposed in the non-display area of ​​the display panel, and Wherein, the temperature sensor outputs the temperature data through the panel line.

3. The display device according to claim 1, wherein: The data driver comprises: an analog-to-digital converter, configured to convert the temperature data into the digital temperature data; A memory configured to store the digital temperature data; a temperature image generator configured to store the background image in the temperature image generator and generate composite image data obtained by synthesizing the background image with received image data based on a result obtained by reading the digital temperature data stored in the memory; and The output circuit is configured to convert the composite image data into data voltages, thereby outputting the data voltages to the plurality of data lines.

4. The display device according to claim 3, wherein: The display device further includes: a controller configured to receive the digital temperature data and input image data, generate the image data by correcting the input image data based on the digital temperature data, and output the image data and a data control signal, Wherein, the data driver further includes: a first interface configured to receive the data control signal and output the digital temperature data; and a second interface configured to receive the image data, and Wherein, the first interface is an internal integrated circuit interface, and the second interface is a low voltage differential signaling interface.

5. The display device according to claim 3, wherein: A plurality of temperature sensors including the temperature sensor are disposed in the non-display area of ​​the display panel, The plurality of temperature sensors are arranged corresponding to a plurality of corner areas in the display area. wherein the analog-to-digital converter sequentially senses the plurality of temperature sensors, wherein a plurality of digital temperature data generated by sequentially sensing the plurality of temperature sensors is stored in the memory, and The temperature image generator generates the synthesized image data by synthesizing the background image with the image data based on the plurality of digital temperature data, so that the background image is displayed in the area determined to be at a high temperature.

6. The display device according to claim 5, wherein: The background image is displayed in at least one of the plurality of corner areas of the display area.

7. The display device according to claim 5, wherein: The background image is displayed in an edge region in which two adjacent corner regions among the plurality of corner regions of the display region are connected to each other.

8. The display device according to claim 3, wherein: The temperature image generator performs different gradient processing on the background image based on the value of the digital temperature data.

9. A head mounted display device, wherein: The head mounted display device comprises: a processor configured to output first input image data and second input image data; a first display device including a first display panel, the first display device being configured to synthesize a stored background image with first image data corresponding to the first input image data based on temperature data sensed in the first display panel, thereby displaying a first synthesized image to a first eye of a user; and A second display device includes a second display panel, and the second display device is configured to synthesize a stored background image with second image data corresponding to the second input image data based on temperature data sensed in the second display panel, thereby displaying a second synthesized image to the second eye of the user.

10. The head mounted display device according to claim 9, wherein: According to the temperatures of the first display device and the second display device, an image obtained by synthesizing the background image is displayed in any one of the first display device and the second display device, and an image obtained by not synthesizing the background image is displayed in the other of the first display device and the second display device.

Images