Memory interface circuit and memory control method

Abstract

The invention discloses a memory interface circuit and a memory control method, and relates to the technical field of memories. The memory interface circuit is applied to an electronic device. The electronic device comprises a computing circuit and a memory. The memory interface circuit is coupled to the computing circuit and the memory and includes a command storage circuit, a state machine, and a memory control circuit. The command storage circuit is used for storing at least one command. The state machine is coupled to the command storage circuit for managing a current mode of the memory. The memory control circuit is coupled to the state machine for switching the current mode of the memory. The memory control circuit controls the memory to periodically operate in a first mode and a second mode, and the memory does not process the at least one command in the first mode.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory interface circuit and a memory control method. Background Art

[0002] The suspend to RAM (STR) function uses the self-refresh mode of the dynamic random access memory (DRAM) to reduce the power consumption of electronic devices. When the DRAM is operating in the self-refresh mode, the DRAM is in a dormant state and cannot be accessed. Conversely, when the DRAM is not operating in the self-refresh mode, the DRAM is in an idle state and can be accessed.

[0003] Since the functional circuits (e.g., encoding / decoding circuits, encryption / decryption circuits, etc.) of the electronic device cannot access DRAM in the STR state (i.e., power saving state), the electronic device will undergo the following state switching procedures when entering and exiting the STR state to ensure that the electronic device will not have errors: media switch (i.e., the system switches between DRAM and static random access memory (SRAM)), functional circuit suspend, system suspend, system resume, and functional circuit resume. However, the state switching procedure involves cumbersome switching steps and is quite time-consuming, causing the electronic device to be unable to respond to the DRAM read request of the time-sensitive functional circuit in a timely manner, seriously reducing the performance of the electronic device and the user experience. Summary of the invention

[0004] Based on the deficiencies of the prior art, one of the objectives of the present application is to provide a memory interface circuit and a memory control method to improve the deficiencies of the prior art.

[0005] An embodiment of the present application provides a memory interface circuit, which is applied to an electronic device, wherein the electronic device includes a computing circuit and a memory. The memory interface circuit couples the computing circuit and the memory and includes: a command storage circuit, a state machine, and a memory control circuit. The command storage circuit is used to store at least one command. The state machine is coupled to the command storage circuit and is used to manage a current mode of the memory. The memory control circuit is coupled to the state machine and is used to switch the current mode of the memory. The memory control circuit controls the memory to periodically operate in a first mode and a second mode, and the memory does not process the at least one command in the first mode.

[0006] Another embodiment of the present application provides a memory control method, which is applied to a memory interface circuit. The memory interface circuit stores at least one command and includes a first counter and a second counter. The first counter and the second counter generate a first count value and a second count value, respectively. The method includes: controlling a memory to exit a first mode and enter a second mode according to the first count value; and controlling the memory to exit the second mode and enter the first mode according to the second count value. The memory does not process the at least one command in the second mode.

[0007] The technical means embodied in the embodiments of the present application can improve at least one of the shortcomings of the prior art. Therefore, compared with the prior art, the present application can improve the performance and user experience of the electronic device.

[0008] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a functional block diagram of an embodiment of the electronic device of the present application;

[0010] Figure 2 is a functional block diagram of an embodiment of the state machine and memory control circuit of the present application;

[0011] Figure 3 is a schematic diagram of an embodiment of the memory state of the present application;

[0012] Figure 4 is a flow chart of an embodiment of the memory control method of the present application;

[0013] Figure 5 is a flowchart of an embodiment of the memory of the present application entering and exiting the self-refresh mode SR;

[0014] Figure 6 is a schematic diagram of another embodiment of the memory state of the present application; and

[0015] Figure 7A to Figure 7B is a flow chart of another embodiment of the memory control method of the present application.

[0016] 100: electronic device;

[0017] 110: Computational circuit;

[0018] 120: memory interface circuit;

[0019] 122: command storage circuit;

[0020] 124: state machine;

[0021] 126: memory control circuit;

[0022] 130: memory;

[0023] CMD: command;

[0024] Ctrl_DDR, EN1, EN2: control signal;

[0025] RG: hardware signal;

[0026] 212: control unit;

[0027] 214, 216: counter;

[0028] CLK: system frequency;

[0029] CV1, CV2: count values;

[0030] IDL, IDL1, IDL2: idle mode;

[0031] SC: signal;

[0032] SR: self-refresh mode;

[0033] RQ0, RQ1, RQ2, RQ3, RQ4, RQ5, RQ6: request;

[0034] STR: RAM suspend function;

[0035] S410, S420, S430, S440, S450, S460, S470, S480, S510, S520, S530, S540, S550, S560, S570, S580, S710, S720, S730, S740, S750: steps;

[0036] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13: time points;

[0037] TS0, TS1, TS2, TS3: time period;

[0038] WT: Duration. DETAILED DESCRIPTION

[0039] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some of the terms are explained or defined in this specification, the interpretation of the terms shall be based on the explanation or definition in this specification.

[0040] The disclosure of the present application includes a memory interface circuit and a memory control method. Since some of the components included in the memory interface circuit of the present application may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention. In addition, part or all of the process of the memory control method of the present application may be in the form of software and / or firmware, and can be executed by the memory interface circuit of the present application or its equivalent device. Without affecting the full disclosure and feasibility of the method invention, the following description of the method invention will focus on the step content rather than the hardware.

[0041] See also Figure 1 , Figure 1 1 is a functional block diagram of an embodiment of the electronic device of the present application. The electronic device 100 includes a computing circuit 110, a memory interface circuit 120 and a memory 130 coupled to each other. The computing circuit 110 controls and accesses the memory 130 through the memory interface circuit 120. In some embodiments, the memory 130 may be a DRAM.

[0042] The computing circuit 110 may be a circuit or electronic component with program execution capability, such as a central processing unit, a microprocessor, a microprocessing unit, a digital signal processor, an application specific integrated circuit (ASIC), or an equivalent circuit thereof. The computing circuit 110 implements part of the functions of the electronic device 100 by executing program codes and / or program instructions stored in the memory 130.

[0043] The memory interface circuit 120 is used to control and access the memory 130, and includes a command storage circuit 122, a state machine 124, and a memory control circuit 126 coupled to each other. The command storage circuit 122 is used to store the command CMD. The command CMD can be generated by the calculation circuit 110 or the functional circuit (not shown). The state machine 124 records, detects, and switches the state of the memory 130. When the state of the memory 130 needs to be switched, the state machine 124 controls the memory 130 through the memory control circuit 126 to switch the state of the memory 130. In some embodiments, the state machine 124 can be implemented by a logic circuit.

[0044] See also Figure 2 , Figure 21 is a functional block diagram of an embodiment of the state machine 124 and the memory control circuit 126 of the present application. The state machine 124 manages the current mode of the memory 130: the self-refresh mode SR or the idle mode IDL. The command storage circuit 122 sends a signal to the state machine 124 when receiving the command CMD, and the state machine 124 determines whether the current state of the memory 130 can respond to the command CMD. When the state of the memory 130 needs to be switched (i.e., when the memory 130 cannot respond to the command CMD), the state machine 124 notifies the memory control circuit 126 to switch the state of the memory 130 with a signal SC, and the memory control circuit 126 controls the memory 130 to switch the state (e.g., enter or exit the STR state (i.e., the self-refresh mode SR) with a control signal Ctrl_DDR.

[0045] The memory control circuit 126 includes a control unit 212 , a counter 214 , and a counter 216 coupled to each other.

[0046] The control unit 212 controls the counter 214 to start counting and / or resetting with the control signal EN1. The counter 214 counts the number of commands CMD processed by the memory 130 in the idle mode IDL. Each time the memory 130 processes a command CMD, the counter 214 increases the count value CV1 by 1.

[0047] The control unit 212 controls the counter 216 to start counting and / or resetting with the control signal EN2. The counter 216 generates a count value CV2 according to the system clock CLK. For example, the counter 216 increases the count value CV2 by 1 every time a cycle of the system clock CLK passes.

[0048] The control unit 212 controls the state of the memory 130 according to the count value CV1 and the count value CV2, and notifies the state machine 124 that the state of the memory 130 has been switched. Figure 3 and Figure 4 The operation details of an embodiment of the present application are described. In the following discussion, "command" and "request" are equivalent.

[0049] See also Figure 3 , Figure 3 TS0-TS3 is a schematic diagram of an embodiment of the memory state of the present application. The time periods TS0-TS3 are continuous time periods, and the length of the time periods is controlled by the control unit 212 according to the count value CV2. For example, when the count value CV2 is equal to the first preset value, the control unit 212 ends the current time period and starts the next time period, and resets the counter 216 (i.e., resets the count value CV2) through the control signal EN2. In other words, the control unit 212 controls the memory 130 to perform periodic operations according to the time period (i.e., according to the system frequency CLK).

[0050] See also Figure 4 , Figure 4 It is a flow chart of an embodiment of the memory control method of the present application, which includes the following steps.

[0051] Step S410: When a time period begins (substantially equivalent to the end of the previous time period (step S460 is yes), it can correspond to Figure 3 At time point t3 and time point t8, the control unit 212 controls the memory 130 to operate in the idle mode IDL (eg, idle modes IDL1 and IDL2) with the control signal Ctrl_DDR to process the request. Figure 3 As shown, the memory 130 processes requests RQ0, request RQ1, request RQ2 and request RQ3 generated at time points t1, time points t2, time points t4 and time points t5, respectively, in the idle mode IDL1 of the time period TS1, and processes requests RQ4 and request RQ5 generated at time points t6 and time points t9, respectively, in the idle mode IDL2 of the time period TS2.

[0052] Step S420: The memory interface circuit 120 determines whether the memory 130 has processed a preset number of requests (a second preset value) according to the count value CV1. Figure 3 In the example, the preset number is 4. When the memory 130 has processed the preset number of requests in the idle mode IDL (the result of step S420 is yes, that is, when the count value CV1 is equal to the second preset value, for example, time point t7), the control unit 212 controls the memory 130 to exit the idle mode IDL and enter the STR state (that is, operate in the self-refresh mode SR) (step S450) with the control signal Ctrl_DDR to save power. If the result of step S420 is no, step S430 is executed.

[0053] It should be noted that in Figure 3 In the example, although request RQ4 is generated in time period TS1, because the idle mode IDL (IDL1) of time period TS1 has been used to process four requests, namely, requests RQ0 to RQ3, the memory 130 must wait until the next time period (ie, time period TS2) to process request RQ4.

[0054] Step S430: The memory interface circuit 120 determines whether there is a request to be processed. If yes, the process returns to step S410 to process the request; otherwise, the process proceeds to step S440.

[0055] Step S440: The memory interface circuit 120 determines whether the waiting time WT has been reached. Figure 3In the example of FIG. 1 , the memory 130 exits the STR state at time point t8 and enters the idle mode IDL2, and then processes the request RQ4 and the request RQ5 in the idle mode IDL2. Next, because there is no request to be processed (step S430 is No), the control unit 212 starts to count the preset time length WT (for example, Figure 3 Between time point t10 and time point t11). When the memory interface circuit 120 does not receive any new request in the idle mode IDL for more than the preset time length WT (that is, when the memory 130 does not process any request in the idle mode IDL2 for the preset time length WT, for example, time point t11), the control unit 212 controls the memory 130 to exit the idle mode IDL2 and enter the STR state early to further save power. "Early" means that although the number of requests processed by the memory 130 does not reach the preset number (the second preset value), the control unit 212 still controls the memory 130 to exit the idle mode IDL2 and enter the STR state (step S450). In other words, in Figure 3 In the embodiment, the duration of the idle mode IDL1 (t7-t3) is greater than or equal to the duration of the idle mode IDL2 (t11-t8), that is, the duration of the STR state of the time period TS1 (t8-t7) is less than or equal to the duration of the STR state of the time period TS2 (t13-t11).

[0056] Step S450 : the memory interface circuit 120 controls the memory 130 to exit the idle mode IDL and enter the STR state (ie, enter the self-refresh mode SR).

[0057] Step S460: The memory interface circuit 120 determines whether the current time period has ended according to the count value CV2. If yes, step S470 is executed; otherwise, the process continues to wait for the current time period to end.

[0058] Step S470 : the memory interface circuit 120 controls the memory 130 to exit the STR state (ie, exit the self-refresh mode SR).

[0059] Step S480: The control unit 212 resets the count value CV1 and the count value CV2, and then the process returns to step S410 to enter the idle mode IDL of the next time period. In other words, the control unit 212 periodically resets the count value CV1 and the count value CV2.

[0060] Please note that Figure 3 In the example, the time period TS2 ends at the time point t13, and the request RQ6 generated at the time point t12 is processed in the time period TS3.

[0061] See also Figure 5 , Figure 5 It is a flow chart of an embodiment of the memory of the present application entering and exiting the self-refresh mode SR, including the following steps.

[0062] Step S510: The memory 130 is idle (ie, in a non-STR state). For example, this step may correspond to Figure 3 Idle mode IDL1 or idle mode IDL2.

[0063] Step S520: The memory interface circuit 120 blocks the request from the functional circuit so that the memory 130 will not receive the request from the functional circuit when it operates in the self-refresh mode SR later. Figure 3 , the memory 130 will not receive the request RQ6 in the STR state of the time period TS2. In some embodiments, the request RQ6 is temporarily stored in the command storage circuit 122.

[0064] Step S530 : The memory interface circuit 120 is idle to save power.

[0065] Step S540: The memory 130 enters the self-refresh mode SR. This step may correspond to Figure 3 time point t7 or time point t11.

[0066] Step S550: The power of the memory 130 is turned off.

[0067] Step S560: The power of the memory 130 is turned on.

[0068] Step S570 : the memory 130 exits the self-refresh mode SR.

[0069] Step S580: The memory interface circuit 120 does not block the request from the functional circuit so that the memory 130 can process the request. For example, this step may correspond to Figure 3 time point t3, time point t8 or time point t13.

[0070] Depend on Figure 3 to Figure 5 It can be seen that in one embodiment of the present application, the memory interface circuit 120 automatically controls the memory 130 to periodically enter the self-refresh mode SR (steps S520-S540, corresponding to Figure 3 STR state) and exiting the self-refresh mode SR (steps S570-S580, corresponding to Figure 3 Idle mode IDL1 or idle mode IDL2).

[0071] In some embodiments, the application or firmware on the electronic device 100 (executed by the computing circuit 110) can simply switch the state machine 124 of the memory interface circuit 120 by setting registers (i.e., switching from the self-refresh mode SR to the idle mode IDL, or from the idle mode IDL to the self-refresh mode SR), which greatly simplifies the management burden of the electronic device 100 on the memory 130. Figure 3 For the embodiment of the present invention, the calculation circuit 110 can enable the automatic STR state of the memory interface circuit 120. In the automatic STR state, the memory interface circuit 120 only needs to periodically set the register to enable the memory 130 to periodically enter and exit the self-refresh mode SR.

[0072] In summary, since the memory 130 is controlled by the memory interface circuit 120 in the STR state, rather than by software, the system of the electronic device 100 does not need to undergo a medium switch when entering and exiting the STR state, which not only greatly simplifies the process, but also greatly improves the response speed of the electronic device 100. In addition, the proportion of the STR state in a time period can be adjusted by adjusting the first preset value (D1) and / or the second preset value (D2). The larger the ratio (D1 / D2) of the first preset value to the second preset value, the larger the proportion of the STR state in a time period (i.e., the electronic device 100 is more power-saving).

[0073] See also Figure 6 and Figure 7A to Figure 7B . Figure 6 It is a schematic diagram of another embodiment of the memory state of the present application. Figure 7A to Figure 7B is a flowchart of another embodiment of the memory control method of the present application, corresponding to Figure 6 . Figure 6 and Figure 7A to Figure 7B Examples and Figure 3-4 The embodiments are similar in part, however, Figure 6 and Figure 7A to Figure 7B In the embodiment of the present invention, the memory interface circuit 120 interrupts the STR state of the memory 130 in the time period TS1 (more specifically, at the time point t8) to process the high priority requests RQ4 and RQ5, and then controls the memory 130 to enter the STR state after waiting for a preset time length WT (more specifically, at the time point t11). The detailed process is as follows: Figure 7A to Figure 7B shown. Fig. 7A Steps S410 to S480 and Figure 4 The same, so no further elaboration. Figure 7A to Figure 7B It also includes steps S710 to S750.

[0074] Step S710: After the memory 130 enters the STR state (step S450), the memory interface circuit 120 determines whether the system (ie, the software or hardware of the electronic device 100) needs to access the memory 130. If yes, execute step S720; otherwise, execute step S460. Figure 3 , this step may correspond to time point t7. At time point t7, the system has a need for urgent access to the memory 130 (request RQ4, for example, issued by a time-sensitive functional circuit). In some embodiments, when the system needs urgent access to the memory 130, the computing circuit 110 notifies the memory interface circuit 120 by means of a hardware signal RG (for example, write register). The memory interface circuit 120 may perform the judgment of step S710 according to the hardware signal RG.

[0075] Before the current time period ends (ie, when the result of step S460 is No), the memory interface circuit 120 continues to execute step S710 .

[0076] Step S720: The memory interface circuit 120 controls the memory 130 to exit the STR state (ie, exit the self-refresh mode SR) and enter the idle mode IDL. This step may correspond to Figure 3 time point t8.

[0077] Step S730: the memory 130 processes the request, for example, processes request RQ4.

[0078] Step S740: After the memory 130 has processed the current request (e.g., request RQ4), the memory interface circuit 120 determines whether there are any requests to be processed. If so, the memory 130 then processes the request (step S730); otherwise, step S750 is executed. Figure 3 In the example of FIG. 1 , because the memory 130 has a request RQ5 (generated at time point t9) to be processed after processing the request RQ4, the memory 130 then processes the request RQ5, and then the memory interface circuit 120 determines in the next step S740 that there is no request to be processed (the result of step S740 is no, corresponding to Figure 6 time point t10).

[0079] Step S750: The memory interface circuit 120 determines whether the waiting time WT has been reached. Step S750 is similar to step S440. Please refer to the description of step S440. When the waiting time is greater than or equal to the preset time WT (step S750 is yes), the memory interface circuit 120 controls the memory 130 to enter the STR state (step S450, corresponding to Figure 6 time point t11).

[0080] In summary, Figure 6 and Figure 7A to Figure 7B In the embodiment of the present invention, the memory interface circuit 120 not only periodically controls the memory 130 to enter the STR state to save power, but also takes into account the ability to process important packets (e.g., requests RQ4 and RQ5), thereby improving the stability and operational flexibility of the electronic device 100. Furthermore, because the entry and exit of the memory 130 into the STR state does not involve the switching of the system operating medium, the suspension of the functional circuit, the system suspension, the system recovery, and the recovery of the functional circuit, in the present application, the sleep and wake-up of the memory 130 does not need to leave the system kernel (i.e., it does not need to switch to the user space), which greatly improves the response speed of the memory 130 in the STR state. Therefore, even if the memory 130 is in the sleep state, when the computing circuit 110 and the functional circuit of the electronic device 100 need to access the memory 130, the memory 130 can respond quickly.

[0081] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. A memory interface circuit, characterized in that: The invention is applied to an electronic device, wherein the electronic device comprises a computing circuit and a memory, wherein the memory interface circuit couples the computing circuit and the memory and comprises: a command storage circuit for storing at least one command; a state machine, coupled to the command storage circuit, for managing a current mode of the memory; and a memory control circuit, coupled to the state machine, for switching the current mode of the memory; The memory control circuit controls the memory to periodically operate in a first mode and a second mode, and the memory does not process the at least one command in the first mode.

2. The memory interface circuit according to claim 1, wherein: The memory control circuit comprises: a counter for generating a count value; and A control unit is coupled to the counter and is used for controlling the memory to exit the first mode according to the count value.

3. The memory interface circuit according to claim 2, wherein: The control unit also controls the memory to operate in a time period according to the count value, and when the count value is equal to a preset value, the time period ends, and the control unit controls the memory to exit the first mode.

4. The memory interface circuit according to claim 1, wherein: The memory operates in the first mode or the second mode in a time period, the memory processes the at least one command in the second mode, and the memory control circuit includes: a counter for generating a count value according to a number of the at least one command processed by the memory in the second mode; and A control unit is coupled to the counter, and is used for controlling the memory to exit the second mode and enter the first mode during the time period according to the count value.

5. The memory interface circuit according to claim 4, wherein: When the count value is equal to a preset value, the control unit controls the memory to exit the second mode and enter the first mode.

6. The memory interface circuit according to claim 1, wherein: The memory operates in the first mode or the second mode in a time period, the memory processes the at least one command in the second mode, and the memory control circuit controls the memory to exit the second mode and enter the first mode after waiting for a preset period of time in the second mode of the time period.

7. The memory interface circuit according to claim 6, wherein: During the preset time period, the memory does not process any command.

8. The memory interface circuit according to claim 6, wherein: The time period is a first time period, the memory also operates in a second time period, and a first duration of the first mode in the first time period is greater than or equal to a second duration of the first mode in the second time period.

9. The memory interface circuit according to claim 6, wherein: The time period is a first time period, the memory also operates in a second time period, and a first duration of the second mode in the first time period is less than or equal to a second duration of the second mode in the second time period.

10. The memory interface circuit according to claim 1, wherein: The memory operates in the first mode or the second mode in a time period, the memory processes the at least one command in the second mode, and the memory control circuit also controls the memory to exit the first mode and enter the second mode according to a hardware signal in the first mode of the time period to process the at least one command.

11. A memory control method, characterized in that: Applied to a memory interface circuit, the memory interface circuit stores at least one command and includes a first counter and a second counter, the first counter and the second counter generate a first count value and a second count value respectively, the method includes: Controlling a memory to exit a first mode and enter a second mode according to the first count value; and controlling the memory to exit the second mode and enter the first mode according to the second count value; The memory does not process the at least one command in the second mode.

12. The method according to claim 11, characterized in that Also includes: controlling the memory to operate in a time period according to the second count value; as well as When the second count value is equal to a preset value, the time period ends and the memory is controlled to exit the second mode.

13. The method according to claim 11, characterized in that Also includes: The second counter is reset periodically.

14. The method according to claim 11, characterized in that The memory processes the at least one command in the first mode, and the first count value is a number of the at least one command processed by the memory in the first mode.

15. The method according to claim 14, characterized in that Also includes: When the first count value is equal to a preset value, the memory is controlled to exit the first mode and enter the second mode.

16. The method according to claim 11, characterized in that The memory operates in the first mode or the second mode in a time period, and the memory processes the at least one command in the first mode, and the method further includes: After waiting for a preset time period in the first mode of the time period, the memory is controlled to exit the first mode and enter the second mode.

17. The method according to claim 16, characterized in that During the preset time period, the memory does not process any command.

18. The method according to claim 16, characterized in that The time period is a first time period, the memory also operates in a second time period, and a first duration of the second mode in the first time period is greater than or equal to a second duration of the second mode in the second time period.

19. The method according to claim 16, characterized in that The time period is a first time period, the memory also operates in a second time period, and a first duration of the first mode in the first time period is less than or equal to a second duration of the first mode in the second time period.

20. The method of claim 11, wherein: The memory operates in the first mode or the second mode in a time period, and the memory processes the at least one command in the first mode, and the method further includes: In the second mode of the time period, the memory is controlled according to a hardware signal to exit the second mode and enter the first mode to process the at least one command.

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