Device comprising clock input buffer

Abstract

Embodiments of the present disclosure provide an apparatus including a clock input buffer. The apparatus includes: first and second input transistors of a first type and first and second load transistors of a second type coupled in series, respectively; at least one resistor coupled to a gate node of the load transistor; and first and second capacitance devices. Gate nodes of the first and second input transistors are coupled to first and second inputs, respectively. The first input transistor and the first load transistor are coupled to a first output. The second input transistor and the second load transistor are coupled to a second output. The gate nodes of the first and second load transistors are coupled to a bias voltage through the resistor. The first and second capacitive devices are coupled to the first and second inputs and the gate nodes of the first and second load transistors, respectively.

Description

Technical Field

[0001] The present disclosure relates to devices including clock input buffers. Background Art

[0002] Clock input buffers are commonly used to provide input to various circuits. In one example, in conjunction with a memory device such as a dynamic random access memory (DRAM), a clock input buffer can receive an external clock signal and output an internal clock signal as a reference clock signal to, for example, latch input data.

[0003] There is a need for a clock input buffer that can properly operate at higher frequencies without increasing current consumption. Summary of the invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: first and second input transistors of a first type, the gate nodes of the first and second input transistors being coupled to first and second inputs, respectively; first and second load transistors of a second type being coupled in series to the first and second input transistors, respectively, the first input transistor and the first load transistor being coupled to a first output, the second input transistor and the second load transistor being coupled to a second output; at least one resistor being coupled to the gate nodes of the first and second load transistors, the gate nodes of the first and second load transistors being coupled to a bias voltage through the at least one resistor; a first capacitive device being coupled to the first input and the gate node of the first load transistor; and a second capacitive device being coupled to the second input and the gate node of the second load transistor.

[0005] On the other hand, the present disclosure provides a clock input buffer, which includes: first and second input transistors of a first type, the gate nodes of the first and second input transistors are coupled to the first and second inputs of the clock input buffer, respectively; and first and second load transistors of a second type, which are coupled in series to the first and second input transistors, respectively, the first input transistor and the first load transistor are coupled to the first output of the clock input buffer, and the second input transistor and the second load transistor are coupled to the second output of the clock input buffer; wherein the gate nodes of the first and second load transistors are coupled to a bias voltage through at least one resistor, and wherein the first and second inputs are coupled to the gate nodes of the first and second load transistors through first and second capacitors, respectively.

[0006] On the other hand, the present disclosure provides a clock input buffer, which includes: first and second input transistors of a first type, whose gate nodes are coupled to the first and second inputs of the clock input buffer, respectively; and first and second load transistors of a second type, which are coupled in series to the first and second input transistors, respectively, the first input transistor and the first load transistor are coupled to the first output of the clock input buffer, and the second input transistor and the second load transistor are coupled to the second output of the clock input buffer; wherein the gate nodes of the first and second load transistors are coupled to a bias voltage through at least one resistor, and wherein the first and second inputs are coupled to the gate nodes of the first and second load transistors, respectively, through third and fourth transistors of the first type. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an example semiconductor system according to an embodiment of the present disclosure.

[0008] Figure 2 is a circuit diagram of an example clock input buffer.

[0009] Figure 3A and 3B is a circuit diagram of an example clock input buffer according to an embodiment of the present disclosure.

[0010] Figure 4A and 4B Example waveforms at a lower operating frequency and at a higher operating frequency according to an embodiment of the present disclosure are respectively described.

[0011] Figure 5 is a circuit diagram of an example bias voltage generator according to an embodiment of the present disclosure.

[0012] Figure 6 is a circuit diagram of an example clock input buffer according to an embodiment of the present disclosure.

[0013] Fig. 7A and 7B is a circuit diagram of an example clock input buffer according to an embodiment of the present disclosure.

[0014] Fig. 8A and 8B is a circuit diagram of an example clock input buffer according to an embodiment of the present disclosure.

[0015] Fig. 9 Depicted is a schematic configuration of an example semiconductor system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Various example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects of the embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structural changes, logical changes, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0017] In the description, common or related elements and substantially the same elements are indicated by the same symbols, and their description will be reduced or omitted. In the figures, for ease of description, some of the same symbols may be omitted for the same or substantially the same elements. In the figures, the size and size ratio of each unit may not necessarily match the actual size and size ratio in the embodiment.

[0018] Figure 1 is a block diagram of an example semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a dynamic random access memory (DRAM) device. In some embodiments of the present disclosure, the semiconductor device 100 may be included in a semiconductor memory device. The DRAM device may include an interface die and a plurality of core dies stacked on the interface die. In some embodiments, the DRAM device may be a high bandwidth memory (HBM) or a hybrid memory cube (HMC). In some embodiments, the DRAM device may be a double data rate (DDR) DRAM. The DDR DRAM may be a low power DDR (LPDDR) DRAM. Figure 1 In the example diagram of FIG. 1 , certain components are shown as being located on the interface (IF) die 130, while other components are shown as part of each of the core dies 140. For clarity, only a single core die 140 and its components are shown; however, there may be multiple core dies (e.g., 2, 4, 6, 8, 16, or more) each having components similar to each other. Figure 1 The semiconductor device 100 of FIG. 1 shows a particular arrangement of components between the IF die 130 and the core die 140; however, other arrangements may be used in other embodiments (e.g., in some embodiments, the refresh control circuit 116 may be on the IF die 130). For illustration purposes, the core die 140 is drawn as a rectangular box that is smaller than the IF die 130; however, the core die 140 and the IF interface 130 may have any size relationship to each other. For example, the core die 140 and the IF die 130 may be approximately the same size.

[0019] The semiconductor device 100 includes a memory array 118 on each of the core dies 140. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown to include 8 memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by the row decoder 108, and the selection of the bit lines BL is performed by the column decoder 110, each of which may also be located on each of the core dies. Figure 1 In an embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank, and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit lines BL are coupled to corresponding sense amplifiers (SAMPs) of the memory array 118. Data read from the bit lines BL are amplified by the sense amplifiers SAMPs and transmitted to the read / write amplifier (RWAMP) 120 through complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B) coupled to the RWAMP 120. Conversely, write data output from the RWAMP 120 is transmitted to the sense amplifiers SAMPs through complementary main data lines MIOT / B, transfer gates TG, and complementary local data lines LIOT / B, and is written in memory cells MC coupled to the bit lines BL.

[0020] The semiconductor device 100 may employ a plurality of external terminals positioned on the IF die 130, including a command and address (CA) terminal coupled to a command and address bus to receive commands and addresses as well as a CS signal, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0021] The clock terminals on the IF die 130 are supplied with external clocks CK and / CK provided to the input circuit 112. The external clocks CK and / CK may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input and output (IO) circuit 122 to time the operation of the circuits included in the IO circuit 122, for example, to the data receiver to time the reception of the write data.

[0022] The internal clock LCLK may include a read clock (RCLK) for controlling the timing of a read operation and a write clock (WCLK) for controlling the timing of a write operation. The internal clock may be delivered to the IO circuit 122. In some examples, the internal clock may also be delivered to internal components of the core die 140, such as the RWAMP 120.

[0023] The memory address may be supplied to the CA terminal of the IF die 130. The memory address supplied to the CA terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded memory bank address BADD, which may indicate the memory bank containing the decoded row address XADD and column address YADD in the memory array 118. A command may be supplied to the CA terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the memory cells to be accessed.

[0024] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102 of the IF die 130. The command decoder 106 includes circuits for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal to select a word line and a column command signal to select a bit line.

[0025] The semiconductor device 100 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are supplied in time with the activation command and the read command, read data is read from the memory cell corresponding to the row address and the column address in the memory array 118. The read command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the data read from the memory array 118 is provided to the RWAMP 120. The read data is output from the data terminal DQ to the outside of the semiconductor device 100 via the IO circuit 122.

[0026] The semiconductor device 100 may receive an access command as a write command. When the write command is received and the memory address, row address, and column address are supplied in time with the activation command and the write command, the write data is supplied to the RWAMP 120 through the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, and the command decoder 106 provides an internal command so that the write data is received by the data receiver in the IO circuit 122. A write clock may also be provided to the external clock terminal for timing the reception of the write data by the data receiver of the IO circuit 122. The write data is supplied to the RWAMP 120 via the IO circuit 122.

[0027] The semiconductor device 100 may also receive a command that causes it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be issued externally to the semiconductor device 100. In some embodiments, the self-refresh mode command may be periodically generated by a component of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command.

[0028] Power supply potentials VDD and VSS are supplied to the power supply terminals of the IF die 130. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials such as VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0029] A power supply potential VDDQ is also supplied to the power supply terminal of the IF die 130. The power supply potential VDDQ is supplied to the IO circuit 122. In an embodiment of the present disclosure, the power supply potential VDDQ supplied to the power supply terminal may be the same potential as the power supply potential VDD supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potential VDDQ supplied to the power supply terminal may be a different potential from the power supply potential VDD supplied to the power supply terminal. The power supply potential VDDQ supplied to the power supply terminal is used for the IO circuit 122 so that the power supply noise generated by the IO circuit 122 does not propagate to other circuit blocks.

[0030] Figure 2is a circuit diagram of an example clock input buffer 200. The clock input buffer 200 may be included in or coupled to a semiconductor device, such as the semiconductor device 100. The clock input buffer 200 may be at least part of the clock input buffer 112 and / or the internal clock generator 114 of the semiconductor device 100. The clock input buffer 200 may be a differential amplifier. The term "coupled" herein may include "connected".

[0031] The clock input buffer 200 includes p-channel metal oxide semiconductor (PMOS) transistors M1 and M2 and resistors R1 and R2. The PMOS transistor M1 is coupled in series with the resistor R1. The PMOS transistor M2 is coupled in series with the resistor R2. The sources of M1 and M2 are commonly coupled to a positive power supply VDD. The drains of M1 and M2 are coupled to the terminals of R1 and R2 on one side, respectively. The drains of M1 and M2 and the terminals of R1 and R2 are commonly coupled to outputs / OUT and OUT, respectively. In some examples, the drains of M1 and M2 and the terminals of R1 and R2 are commonly coupled to an output node to provide output clock signals / OUT and OUT, respectively. The terminals of R1 and R2 are coupled to a negative power supply or ground VSS on the other side. The gates of M1 and M2 are coupled to inputs IN and / IN, respectively. In some examples, the gates of M1 and M2 are coupled to input nodes to receive input clock signals IN and / IN, respectively.

[0032] The voltage value of the common mode of the input IN and / IN can be significantly lower than the voltage value of the positive power supply VDD as the supply source of the constant current Is. For example, the voltage value of the common mode of IN and / IN can be 0.2V or about 0.2V or 0.4V or about 0.4V, while the voltage value of VDD can be 1.05V or about 1.05V. The PMOS transistor coupled to such input and power supply is used as the input element of the differential amplifier. The resistors R1 and R2 coupled to the outputs OUT and / OUT are the loads of the differential amplifier. This differential amplifier can also be called a resistor-load differential amplifier.

[0033] In the case where the memory device is a DDR DRAM (e.g., LPDDR DRAM), for example, an external clock such as a differential clock may be provided to the inputs IN and / IN from the DDR data interface. In one example, the external differential clock is input to M1 and M2, respectively, and the internal differential clock output from the differential amplifier is used to latch the external data input DQ. The differential clocks may be complementary. In some examples, the differential clocks may be differential forwarding clocks WCK and / WCK. WCK and / WCK may be complementary. In some embodiments, WCK and / WCK may be input to Figure 1 Terminals of the IF die 130 of the semiconductor device 100 are shown in FIG.

[0034] However, in a resistor-load differential amplifier, the required or expected output amplitude may not be obtained at high frequencies. For example, when IN rises (i.e., IN changes from low to high) and / IN falls (i.e., / IN changes from high to low), the M1 resistance increases and the M2 resistance decreases, respectively. Because the operating current Is provided by VDD is constant, the M1 current decreases and the M2 current increases accordingly. This causes the / OUT level coupled to M1 and R1 to decrease and the OUT level coupled to M2 and R2 to increase. Similarly but inversely, when IN falls and / IN rises, / OUT increases and OUT decreases. At high frequencies, this output amplitude reduction occurs further and more extensively, possibly beyond a tolerable range. Therefore, in order to obtain the output amplitude at high frequencies as required or desired, the operating current may need to be increased, which increases current consumption.

[0035] Some embodiments of the present disclosure described in detail below address the above-mentioned unexpected, incorrect output amplitude at high frequencies without increasing current consumption.

[0036] Figure 3A and 3B 3 are circuit diagrams of example clock input buffers 300 and 310, respectively, according to embodiments of the present disclosure. In some embodiments, clock input buffers 300 and / or 310 may be included in or coupled to a semiconductor device, such as semiconductor device 100. In some embodiments, clock input buffers 300 and / or 310 may be at least part of clock input buffer 112 and / or internal clock generator 114 of semiconductor device 100. Clock input buffer 300 may be a differential amplifier. The term "coupled" herein may include "connected".

[0037] refer to Figure 3A , the clock input buffer 300 includes n-channel metal oxide semiconductor (NMOS) transistors M3 and M4 as loads of the differential amplifier instead of the resistors R1 and R2 of the clock input buffer 200. The clock input buffer 300 further includes capacitors (capacitor / condenser) C1 and C2 and resistors R3 and R4, as shown in FIG. Figure 3A . PMOS transistors M1 and M2 remain as input elements of the differential amplifier. M1 and M2 may also be referred to as input PMOS transistors. NMOS transistors M3 and M4 serve as loads of the differential amplifier. M3 and M4 may also be referred to as load NMOS transistors. This differential amplifier may also be referred to as a MOS-load differential amplifier. In some embodiments, capacitors C1 and C2 may be replaced by PMOS transistors used as capacitive devices (also referred to as capacitive elements). For example, referring to Figure 3BThe clock input buffer 310 includes NMOS transistors M3 and M4 as the load of the differential amplifier, and further includes resistors R3 and R4. In addition, the PMOS transistors M5 and M6 are configured as capacitors (capacitor / condenser), such as Figure 3B . PMOS transistors M5 and M6 may be low threshold voltage (Vt) PMOS transistors. For example, Vt may be -0.2V. In some embodiments, the MOS transistors may be metal-insulator-silicon (MIS) transistors. The insulator may be a non-oxide insulator.

[0038] For both clock input buffers 300 and 310, a PMOS transistor M1 is coupled in series with an NMOS transistor M3. The source of M1 is coupled to a positive power supply source VDD. The gate of M1 is coupled to an input node N1 to receive an input IN. Node N1 may also be referred to as a gate node of M1. In some examples, there may be a separate gate node of M1 coupled to input node N1. The source of M3 is coupled to a negative power supply or ground VSS. The drains of M1 and M3 are coupled to each other. The drains of M1 and M3 are also commonly coupled to an output node N5 to provide an output / OUT.

[0039] Similarly for both clock input buffers 300 and 310, PMOS transistor M2 is coupled in series with NMOS transistor M4. The source of M2 is coupled to a positive power supply source VDD. The gate of M2 is coupled to input node N2 to receive input / IN. Node N2 may also be referred to as the gate node of M2. In some examples, there may be a separate gate node of M2 coupled to input node N2. The source of M4 is coupled to a negative power supply or ground VSS. The drains of M2 and M4 are coupled to each other. The drains of M2 and M4 are also commonly coupled to output node N6 to provide output OUT. In some embodiments, IN and / IN may be external differential clocks, and OUT and / OUT may be internal differential clocks.

[0040] For example, capacitors C1 and C2 ( Figure 3A ) and PMOS transistors M5 and M6 ( Figure 3B ) is coupled to input nodes N1 and N2 and gates or gate nodes N3 and N4 of M3 and M4. In some examples where there is a gate node of M1 coupled to input node N1 and a gate node of M2 coupled to input node N2, the terminals of the capacitive device may be coupled to such gate nodes of M1 and M2, respectively, on one side, and the terminals of the capacitive device may be coupled to N3 and N4 of M3 and M4, respectively, on the other side. Gate nodes N3 and N4 of M3 and M4 are coupled to a bias voltage Vnb through R3 and R4, respectively. R3 and R4 are coupled in series between M3 and M4. Vnb may be, for example, Figure 5The bias voltage generator 500 according to an embodiment of the present disclosure shown in FIG. 5 generates a bias voltage Vnb. The bias voltage generator 500 includes at least one diode-connected NMOS transistor M50 coupled to VDD and VSS to generate a bias voltage Vnb. For example, Vnb may be 0.5V.

[0041] In some examples, clock input buffers 300 and 310 operate at a higher frequency than clock input buffer 200. Compared to clock input buffer 200, resistors R1 and R2, which are loads of the differential amplifier of clock input buffer 200, are replaced by NMOS transistors M3 and M4, which are loads of the differential amplifiers of clock input buffer 300 and clock input buffer 310. M3 and M4 may also be referred to as NMOS loads or simply as MOS loads. Gate nodes N3 and N4 of MOS loads M3 and M4 are coupled to bias voltage Vnb through resistors R3 and R4 coupled in series, respectively. Inputs IN and / IN are coupled to N3 and N4 of M3 and M4 through capacitive devices, such as capacitors C1 and C2 of clock input buffer 300 or PMOS transistors M5 and M6 of clock input buffer 310, respectively.

[0042] Figure 4A and 4B Example waveforms at a lower operating frequency and at a higher operating frequency according to an embodiment of the present disclosure are respectively described. The solid lines are waveforms of the clock input buffer 300 and the clock input buffer 310. The dotted lines are waveforms of the clock input buffer 200. For example, the lower operating frequency may be 1.6 GHz. For example, the higher operating frequency may be 4.8 GHz.

[0043] exist Figure 4A and 4B At both the lower operating frequencies (where the bit time is longer) and the higher operating frequencies (where the bit time is shorter) described in FIG. 1 , when IN rises (i.e., IN changes from low (e.g., 0.0V) to high (e.g., 0.4V)), the resistance of M1 increases and the current flowing at M1 decreases. Therefore, the IR drop across M3 decreases, and thus / OUT decreases. At the same time, the voltage level of the gate node N3 of M3 is increased due to the voltage across C1 ( Figure 3A ) or M5( Figure 3B ) coupling and the resistance of M3 decreases. Therefore, the IR drop across M3 is further reduced, and thus / OUT further decreases. Therefore, due to the effect of the increase in M1 resistance due to the increase in IN and the decrease in M3 resistance due to the increase in N1 voltage level caused by capacitive coupling, the decrease in / OUT level is further accelerated. Therefore, / OUT (illustrated by a solid line) decreases more steeply, and the output amplitudes of clock input buffers 300 and 310 become greater than the output amplitudes of clock input buffers 200 (illustrated by a dotted line).

[0044] Likewise, when / IN drops (i.e., / IN changes from high (e.g., 0.4V) to low (e.g., 0.0V)), the resistance of M2 decreases and the current flowing at M2 increases. Therefore, the IR drop across M4 increases, and thus OUT rises. At the same time, the voltage level of the gate node N4 of M4 increases due to the voltage across C2 ( Figure 3A ) or M6( Figure 3B ) coupling and drops from Vnb and the resistance of M4 increases. Therefore, the IR drop across M4 further increases, and thus OUT further rises. Therefore, due to the effect of the M2 resistance decreasing due to the drop in / IN and the M4 resistance increasing due to the drop in the N4 voltage level caused by the capacitive coupling, the rise in the OUT level is further accelerated. Therefore, OUT (illustrated by the solid line) rises more steeply, and the output amplitudes of the clock input buffers 300 and 310 become greater than the output amplitude of the clock input buffer 200 (illustrated by the dotted line).

[0045] Furthermore, in some embodiments, the resistors R3 and R4 may be configured such that the time constant obtained by multiplying the resistance values ​​of R3 and R4 by the capacitance values ​​of nodes N3 and N4, respectively, is greater at higher operating frequencies ( Figure 4B ) is one-quarter (or approximately one-quarter) or one-half (or approximately one-half) of the bit time. Using this resistor design, when the input transitions from low to high or from high to low, the slope of each of the N3 and N4 voltage levels flattens or becomes flatter at a specific time instead of continuing to rise, and the corresponding slope of each of / OUT and OUT becomes less steep. This avoids excessive overshoot of both the node and the output at the end of the input transition. Especially at higher operating frequencies, this suppresses or mitigates interference with the next input transition while achieving a size of the clock "eye" of the clock input buffer 300 that is significantly larger than the size of the clock "eye" of the clock input buffer 200. Therefore, faster transitions and avoidance of larger overshoots enable faster operating frequencies of the clock input buffer 300 than the clock input buffer 200.

[0046] Furthermore, at both the lower operating frequency and the higher operating frequency, the VDD power of the clock input buffer 300 is not increased from the VDD power of the clock input buffer 200 , and thus the current consumption is not increased.

[0047] Figure 6 is a circuit diagram of an example clock input buffer 600 according to an embodiment of the present disclosure. Figure 6In the embodiment of the present invention, the coupling capacitor device is realized by a pair of PMOS transistors M5 and M7 and another pair of PMOS transistors M6 and M8. PMOS transistors M5 to M8 can be low Vt PMOS transistors. In the pair of M5 and M7, the source and drain are coupled to each other at the middle node N7. The gate of M5 is coupled to the node N1. The gate of M7 is coupled to the node N3 of M3 and R3. In the pair of M6 and M8, the source and drain are coupled to each other at the middle node N8. The gate of M6 is coupled to the node N2. The gate of M8 is coupled to the node N4 of M4 and R4. The clock input buffer 600 further includes resistors R5 and R6 coupled to the middle nodes N7 and N8, respectively. The source and drain of M5 and M7 are coupled to the power supply VDD through the middle node N7 and the resistor R5. The source and drain of M6 and M8 are coupled to the power supply VDD through the middle node N8 and the resistor R6. Intermediate nodes N7 and N8 are biased at power supply VDD through resistors R5 and R6, respectively. Resistor R5 is provided to make N3, M5, and M7 high when IN is high. Resistor R6 is provided to make N4, M6, and M8 high when / IN is high.

[0048] In the case where the bias voltage Vnb is lower than the expected design voltage, such as 0.5V, the circuit configuration of the clock input buffer 600 may be used more advantageously than the clock input buffer 300. This may also be more advantageous in the case where the threshold voltage Vt of each of the PMOS transistors is higher than, for example, |-0.2V|. One non-limiting example case may be that a PMOS transistor with a low Vt, such as -0.2V, may not be available due to process design and a PMOS transistor with a high Vt, such as |-0.4V|, is used instead. In addition, if M5 and M6, which are directly coupled to the gate nodes N3 and N4 as in the clock input buffer 300, are not in the strong inversion region (where Vgs>Vt) when operating, then the clock input buffer 600 may be more advantageous than the clock input buffer 300.

[0049] Fig. 7A and 7B1 and 10 are circuit diagrams of example clock input buffers 700 and 710 according to embodiments of the present disclosure, respectively. The clock input buffer 700 may be the same or substantially the same as the clock input buffer 300, except that the clock input buffer 700 is applied to a continuous time linear equalizer (CTLE) amplifier. The clock input buffer 710 may be the same or substantially the same as the clock input buffer 310, except that the clock input buffer 710 is applied to a continuous time linear equalizer (CTLE) amplifier. In the clock input buffers 200, 300, 310 and 600, VDD is shared between the input transistors M1 and M2. In the clock input buffers 700 and 710, each of which is a CTLE amplifier, two power supplies VDD are used to provide constant currents Is1 and Is2 to the input transistors M1 and M2, respectively. Is1 and Is2 may have the same current value. The clock input buffers 700 and 710 further include a resistor R7 and a capacitor C3 coupled in parallel between the two voltage / current paths. In a CTLE amplifier, the source of each of the input transistors M1 and M2 may be degraded through resistor R7 and capacitor C3 with current sources Is1 and Is2. During source degeneration, the current paths may be separated or coupled at the resistor and capacitor.

[0050] As described above, the clock input buffers 300 , 310 , 600 , 700 , and 710 may operate at a high frequency without increasing current consumption compared to the clock input buffer 200 .

[0051] Fig. 8A and 8B 800 and 810, respectively, are circuit diagrams of example clock input buffers 800 and 810 according to embodiments of the present disclosure. In some embodiments, the clock input buffer 800 may be included in or coupled to a semiconductor device, such as the semiconductor device 100. In some embodiments, the clock input buffer 800 may be at least part of the clock input buffer 112 and / or the internal clock generator 114 of the semiconductor device 100. The clock input buffer 800 may be a differential amplifier. In some embodiments, the clock input buffer 810 may be included in or coupled to a semiconductor device, such as the semiconductor device 100. In some embodiments, the clock input buffer 810 may be at least part of the clock input buffer 112 and / or the internal clock generator 114 of the semiconductor device 100. The clock input buffer 810 may be a differential amplifier. The term "coupled" herein may include "connected".

[0052] With respect to the circuit configuration of the clock input buffers 300 and 310, the clock input buffers 800 and 810 have a circuit configuration with a VDD side and a VSS side. The clock input buffers 800 and 810 include NMOS transistors M9 and M10 as input transistors, wherein the gates of the input transistors are coupled to the inputs IN and / IN, respectively, and the sources of the input transistors are commonly coupled to a negative power supply or ground VSS. The clock input buffers 800 and 810 include PMOS transistors M11 and M12 as load transistors (or MOS loads), wherein the sources of the load transistors are coupled to the respective positive power supplies VDD and the gates of the load transistors are commonly coupled to a bias positive voltage Vpb (different from the bias negative voltage Vnb in the clock input buffers 300 and 310) through respective resistors R5 and R6. For example, the value of VDD may be 1.1V or approximately 1.1V. For example, Vpb may be 0.6V or approximately 0.6V. The voltage value of the common mode of the inputs IN and / IN may be at or about 0.8 V. In some embodiments, for example, the input clock signals to IN and / IN may be data strobe signals DQS and / DQS, which are complementary and used to clock the capture of input data for write operations of a DRAM (e.g., DDR DRAM).

[0053] NMOS transistor M9 is coupled in series with PMOS transistor M11, wherein the drains of NMOS transistor M9 and PMOS transistor M11 are coupled to each other. The drains of M9 and M11 are also coupled to output node N5 to provide output / OUT. NMOS transistor M10 is coupled in series with PMOS transistor M12, wherein the drains of NMOS transistor M10 and PMOS transistor M12 are coupled to each other. The drains of M10 and M12 are also coupled to output node N6 to provide output OUT.

[0054] Similar to clock input buffers 300 and 310, clock input buffers 800 and 810 include capacitive devices. For example, clock input buffer 800 includes capacitors C4 and C5 ( Fig. 8A ), and the clock input buffer 810 includes NMOS transistors M13 and M14 ( Figure 8B ). NMOS transistors M13 and M14 may be low Vt NMOS transistors. For example, Vt may be 0.2V. The capacitive device is coupled to input nodes N1 and N2 on one side (which may also be the gate nodes of M9 and M10) and to nodes N3 and N4 on the other side (which may also be the gate nodes of M11 and M12). Nodes N3 and N4 are coupled to Vpb through R3 and R4, respectively. Vpb may be connected to Figure 5The bias voltage generator 500 is generated by a generator similar to the bias voltage generator 500. In some embodiments, M13 and M14 may include a pair of NMOS transistors and another pair of NMOS transistors, respectively, in a manner similar to the pair of M5 and M7 and the pair of M6 and M8 of the clock input buffer 600.

[0055] Using this circuit configuration, similar to the clock input buffers 300 , 310 , 600 , 700 , and 710 , the clock input buffers 800 and 810 may operate at a high frequency without increasing current consumption compared to the clock input buffer 200 .

[0056] Fig. 9 900 according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the semiconductor system 900 includes a semiconductor memory device 901. In an embodiment of the present disclosure, the semiconductor memory device 901 may include Figure 1 The semiconductor device 100 of FIG. 900 may also include a central processing unit (CPU) and a memory controller 904, which may be a controller chip, on an interposer 905 on a package substrate 908. The interposer 905 may include one or more power lines 910 that may supply a power supply voltage from the package substrate 908. The interposer 905 may include a plurality of channels 911 that may interconnect the CPU and the memory controller 904 with the semiconductor memory device 901. The semiconductor memory device 901 may be a DRAM. The DRAM may be a DDR DRAM. The memory controller 904 may provide a clock signal, a command signal, and may further transmit and receive a data signal. The plurality of channels 911 may transmit data signals between the memory controller and the memory device 901.

[0057] The semiconductor memory device 901 may include a plurality of dies (or chips) 902 including at least one interface (IF) die (or chip) 903 and a plurality of memory core dies (or chips) 906 stacked on each other. In some embodiments, each of the plurality of memory core dies 906 may include a core die 140, and the IF die 903 may include the IF die 130 of the semiconductor device 100. In some embodiments, the clock input buffers 300, 310, 600, 700, 710, 800, and 810 may be implemented in the IF die 903.

[0058] The number of memory core die 906 may not be limited to 4 in the illustrated example, and may be more or less as the case may be. Each of the memory core die 906 may include a plurality of memory cells and a circuit system for accessing the memory cells. For example, the memory cells may be DRAM cells. The memory cells may be arranged in an array. The semiconductor memory device 901 may include a conductive path 907, which couples the IF die 903 and the memory core die 906 by penetrating the IF die 903 and the memory core die 906. The IF die 903 may be coupled to the interposer 905 via an interconnect 909. For example, the interconnect 909 may be a microbump having a bump pitch of less than about or less than 100 microns and exposed to the outside of the IF die 903. A portion of each of the interconnects 909 may be coupled to one or more power lines 910. Another portion of each of the interconnects 909 may be coupled to one or more of the channels 911.

[0059] DRAM is just one example, and the embodiments and descriptions herein are not intended to be limited to DRAM. Memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory may also be applied as the semiconductor memory device 901. Furthermore, a device including a logic IC such as a microprocessor and an application specific integrated circuit (ASIC) in addition to a memory may also be suitable as a semiconductor device according to an embodiment of the present invention.

[0060] Although various embodiments of the present disclosure have been described in detail, it will be appreciated by those skilled in the art that embodiments of the present disclosure may extend beyond the explicitly described embodiments to other alternative embodiments and / or uses and modifications and equivalents thereof. In addition, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the described embodiments. It is also contemplated that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments and that they still fall within the scope of the present disclosure. It will be appreciated that the various features and aspects of the embodiments may be combined or substituted with one another to form different modes of the embodiments. Therefore, it is desired that the scope of the present disclosure should not be limited by the specific embodiments described above.

Claims

1. A device comprising: first and second input transistors of a first type, the gate nodes of the first and second input transistors being coupled to the first and second inputs, respectively; first and second load transistors of a second type, coupled in series to the first and second input transistors, respectively, the first input transistor and the first load transistor being coupled to a first output, the second input transistor and the second load transistor being coupled to a second output; at least one resistor coupled to gate nodes of the first and second load transistors, the gate nodes of the first and second load transistors being coupled to a bias voltage through the at least one resistor; a first capacitive device coupled to the first input and the gate node of the first load transistor; and A second capacitive device is coupled to the second input and the gate node of the second load transistor.

2. The apparatus of claim 1, wherein the first and second capacitive devices comprise capacitors.

3. The apparatus of claim 1, wherein the first and second capacitive devices comprise MIS transistors.

4. The apparatus of claim 1, wherein the first and second capacitive devices comprise low threshold voltage MOS transistors.

5. The device according to claim 1, wherein The first capacitive device is coupled to the gate node of the first input transistor and the gate node of the first load transistor, and The second capacitive device is coupled to the gate node of the second input transistor and the gate node of the second load transistor.

6. The apparatus of claim 1, wherein the at least one resistor comprises a plurality of resistors coupled in series between the gate nodes of the first and second load transistors.

7. The apparatus of claim 6, wherein a common node of the series coupled resistors is coupled to the bias voltage.

8. The apparatus of claim 1, wherein the input transistors of the first type comprise PMOS transistors and the load transistors of the second type comprise NMOS transistors.

9. The apparatus of claim 1 , wherein the first capacitive means comprises a first pair of MOS transistors between the first input of the apparatus and the gate node of the first load transistor, and the second capacitive means comprises a second pair of MOS transistors between the second input of the apparatus and the gate node of the second load transistor.

10. The apparatus of claim 1 , wherein the apparatus comprises a clock input buffer comprising the first and second input transistors, the first and second load transistors, the at least one resistor, and the first and second capacitive devices and configured to receive an external clock signal at the first and second inputs and output an internal clock signal at the first and second outputs.

11. The apparatus of claim 10, wherein the clock input buffer is a differential amplifier.

12. The apparatus of claim 1, further comprising a bias voltage generator configured to generate the bias voltage.

13. A clock input buffer, comprising: first and second input transistors of a first type, the gate nodes of the first and second input transistors being coupled to first and second inputs of the clock input buffer, respectively; and first and second load transistors of a second type, which are serially coupled to the first and second input transistors, respectively, the first input transistor and the first load transistor are coupled to a first output of the clock input buffer, and the second input transistor and the second load transistor are coupled to a second output of the clock input buffer; wherein the gate nodes of the first and second load transistors are coupled to a bias voltage through at least one resistor, and Wherein the first and second inputs are coupled to the gate nodes of the first and second load transistors through first and second capacitors, respectively.

14. The clock input buffer of claim 13, wherein the first capacitor is coupled to the gate nodes of the first input transistor and a first load transistor, and the second capacitor is coupled to the gate nodes of the second input transistor and a second load transistor.

15. The clock input buffer of claim 13 configured to receive complementary clock signals at the first and second inputs.

16. A clock input buffer, comprising: first and second input transistors of a first type, the gate nodes of the first and second input transistors being coupled to first and second inputs of the clock input buffer, respectively; and first and second load transistors of a second type, which are serially coupled to the first and second input transistors, respectively, the first input transistor and the first load transistor are coupled to a first output of the clock input buffer, and the second input transistor and the second load transistor are coupled to a second output of the clock input buffer; wherein the gate nodes of the first and second load transistors are coupled to a bias voltage through at least one resistor, and Wherein the first and second inputs are coupled to the gate nodes of the first and second load transistors through third and fourth transistors of the first type, respectively.

17. The clock input buffer of claim 16, wherein the input transistors of the first type comprise PMOS transistors, the load transistors of the second type comprise NMOS transistors, and the third and fourth transistors of the first type comprise PMOS transistors.

18. A clock input buffer according to claim 16, wherein the third transistor of the first type comprises a first pair of PMOS transistors between the first input of the clock input buffer and the gate node of the first load transistor, and the fourth transistor of the first type comprises a second pair of PMOS transistors between the second input of the clock input buffer and the gate node of the second load transistor.

19. The clock input buffer of claim 16, wherein the first and second inputs are configured to receive complementary clock signals at the first and second inputs.

20. The clock input buffer of claim 16, wherein the input transistors of the first type comprise NMOS transistors, the load transistors of the second type comprise PMOS transistors, and the third and fourth transistors of the first type comprise NMOS transistors.

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