A RRAM circuit and its operation method
By setting a plurality of first MOS switches in the RRAM circuit and controlling their voltage changes, the problem of voltage difference in the RRAM array during reset operation is solved, the Reset effect is improved, and the misoperation is avoided, and the memory performance is improved.
Patent Information
- Application Number
- CN202411837265.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-08
AI Technical Summary
During reset operation of existing RRAM arrays, the selected local source line voltage is one threshold voltage lower than the Reset voltage, resulting in poor Reset effect and may misoperate unselected transistors.
By setting a plurality of first MOS switches in the RRAM circuit and controlling the voltage variation thereof, the voltage of the first word line connected to the selected transistor is increased until the voltage of the first source line is equal to the voltage on the second source line, thereby avoiding the voltage difference during Reset operation.
Improves the effect of RRAM circuit in Reset operation, avoids misoperation, and improves overall memory performance.
Smart Images
Figure CN119785848A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of circuit technology, and more particularly to a RRAM circuit and an operation method thereof. Background Art
[0002] Resistive random access memory (RRAM) is a new type of non-volatile memory, which has the advantages of fast reading and writing speed, simple structure, small unit area and high density, and therefore has received widespread attention and application.
[0003] The existing RRAM array mainly adopts a 2T2R structure, and the source lines SL of the cells controlled by the same word line WL are connected together, and then connected to the global SL through the NMOS switch controlled by the WL. However, during the reset operation of the traditional RRAM array, the voltage of the selected local source line LSL is lower than the reset voltage by a threshold voltage Vth, which will cause the reset effect of the selected transistor to deteriorate, and at the same time cause the unselected transistor to perform a Set operation (misoperation). Summary of the invention
[0004] The present disclosure provides a RRAM circuit and an operation method thereof to at least solve the above technical problems existing in the prior art.
[0005] According to a first aspect of the present disclosure, there is provided an RRAM circuit, the RRAM circuit comprising:
[0006] A memory array, the memory array comprising m×n memory cells, each of the memory cells comprising two transistors connected to each other, and two memristors respectively connected to the two transistors;
[0007] A plurality of first word lines, gates of all transistors in a same column are connected to the same first word line;
[0008] A plurality of first MOS switches, one end of each of the first MOS switches being connected to a first word line;
[0009] a plurality of second word lines, each of the second word lines being connected to the other end of the first MOS switch;
[0010] a plurality of first source lines, sources of two transistors of the memory cells in the same column are connected to the same first source line;
[0011] a plurality of second MOS switches, wherein a gate of each second MOS switch is connected to the first word line in the same column, and a source of each second MOS switch is connected to the first source line in the same column;
[0012] A second source line, drains of all the second MOS switches are commonly connected to the second source line; wherein,
[0013] The second word line connected to the selected transistor is connected to a first voltage, and the gate voltage on the first MOS switch changes with time sequence, so that the voltage of the first word line connected to the selected transistor increases;
[0014] The second source line is connected to a second voltage;
[0015] When the voltage of the first word line connected to the selected transistor rises to a predetermined voltage, the voltage of the first source line connected to the selected transistor is equal to the second voltage.
[0016] In one possible implementation, it further includes:
[0017] A plurality of bit lines, all memristors in the same row are connected to the same bit line.
[0018] In one possible implementation, it further includes:
[0019] A buffer, gates of all the first MOS switches are commonly connected to the buffer.
[0020] In one possible implementation manner, the second word line connected to the selected transistor is connected to a first voltage, and the gate voltage on the first MOS switch changes with time sequence, so that the voltage of the first word line connected to the selected transistor increases, including:
[0021] In a first time period, the gate of the first MOS switch is connected to a first switch voltage, and when the second word line connected to the selected transistor is connected to the first voltage, the voltage of the first word line connected to the selected transistor increases to a third voltage;
[0022] In the second time period, when the gate voltage of the first MOS switch increases from the first switch voltage to the second switch voltage, the voltage of the first word line connected to the selected transistor increases from the third voltage to the fourth voltage.
[0023] In one embodiment, during a third time period, the gate voltage of the first MOS switch is pulled down from the second switch voltage to the third switch voltage, and when the second source line is connected to the second voltage and the bit line connected to the unselected transistor is connected to the fifth voltage, the voltage of the first word line connected to the selected transistor is increased from the fourth voltage to the sixth voltage.
[0024] In one possible implementation, the predetermined voltage is equal to a sixth voltage.
[0025] According to a second aspect of the present disclosure, a method for operating an RRAM circuit is provided, wherein the method is applied to the RRAM circuit in any one of the above embodiments, and the method includes:
[0026] Connecting a first voltage to the second word line connected to the selected transistor;
[0027] Controlling the gate voltage of the first MOS switch to change with time sequence, so that the voltage of the first word line connected to the selected transistor increases;
[0028] Connecting a second voltage to the second source line;
[0029] When the voltage of the first word line connected to the selected transistor rises to a predetermined voltage, the voltage of the first source line connected to the selected transistor is equal to the second voltage.
[0030] In one possible implementation manner, the step of connecting the second word line connected to the selected transistor to a first voltage; and controlling the gate voltage on the first MOS switch to change with time sequence so that the voltage of the first word line connected to the selected transistor increases, comprises:
[0031] In a first time period, a first switch voltage is connected to the gate of the first MOS switch, and when the second word line connected to the selected transistor is connected to the first voltage, the voltage of the first word line connected to the selected transistor is increased to a third voltage;
[0032] In the second time period, when the gate voltage of the first MOS switch increases from the first switch voltage to the second switch voltage, the voltage of the first word line connected to the selected transistor increases from the third voltage to the fourth voltage.
[0033] In one embodiment, it also includes: in a third time period, the gate voltage of the first MOS switch is pulled down from the second switch voltage to the third switch voltage, when the second source line is connected to the second voltage and the bit line connected to the unselected transistor is connected to the fifth voltage, the voltage of the first word line connected to the selected transistor is increased from the fourth voltage to the sixth voltage.
[0034] In one possible implementation, the predetermined voltage is equal to the sixth voltage.
[0035] The RRAM circuit and the operation method thereof disclosed in the present invention provide a plurality of first MOS switches between a first word line and a second word line, and control the voltage change of the first MOS switches so that the voltage of the first word line connected to the selected transistor is increased. When the voltage of the first word line connected to the selected transistor is high enough, the voltage of the first source line connected to the selected transistor can be made equal to the voltage on the second source line. In this way, during the Reset operation, there is no voltage difference between the voltage of the selected first source line and the Reset voltage, so that the Reset operation effect of the selected transistor is better.
[0036] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:
[0038] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.
[0039] Figure 1 A schematic diagram of a RRAM circuit provided by an embodiment of the present disclosure;
[0040] Figure 2 It is the timing diagram of the RRAM circuit during the Reset operation;
[0041] Figure 3 A schematic diagram of the RRAM circuit provided by an embodiment of the present disclosure when working in Set;
[0042] Figure 4 It is the timing diagram of the RRAM circuit during the Set operation process;
[0043] Figure 5 The present invention provides a flowchart of an operation method of a RRAM circuit according to an embodiment of the present invention. DETAILED DESCRIPTION
[0044] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.
[0045] The present disclosure provides an RRAM circuit. Figure 1 A schematic diagram of a RRAM circuit provided by an embodiment of the present disclosure, such as Figure 1 As shown, the RRAM circuit includes:
[0046] The memory array includes m×n memory cells 10 , each memory cell 10 includes two transistors 11 connected to each other and two memristors 12 respectively connected to the two transistors 11 .
[0047] Among them, there are 2n transistors and 2n memristors in total for n columns of storage cells.
[0048] The RRAM circuit further includes: a plurality of first word lines LWL, and the gates of all transistors 11 in the same column are connected to the same first word line LWL.
[0049] like Figure 1 As shown, the gates of all transistors 11 in column 1 are connected to the same first word line LWL <0> , the gates of all transistors 11 in the second column are connected to the same first word line LWL <1> , until the gates of all transistors 11 in the 2nth column are connected to the same first word line LWL<2n-1>.
[0050] In one embodiment, the first word line LWL is a local word line.
[0051] The RRAM circuit further includes: a plurality of first MOS switches 21, one end of each first MOS switch 21 being connected to a first word line LWL;
[0052] The buffer 22 , the gates of all the first MOS switches 21 are commonly connected to the buffer 22 .
[0053] The first MOS switch may be an NMOS switch.
[0054] All first MOS switches 21 are driven by buffers 22 .
[0055] The RRAM circuit further includes: a plurality of second word lines GWL, each of which is connected to the other end of the first MOS switch 21 .
[0056] The first word line LWL and the second word line GWL in the same column are connected via a first MOS switch 21. Figure 1 As shown, the first word line LWL in column 1 <0> The second word line GWL <0> Connect the first word line LWL of the second column <1> The second word line GWL <1> The connection is continued until the first word line LWL<2n-1> in the 2n-th column is connected to the second word line GWL<2n-1>.
[0057] In one embodiment, the second word line GWL is a global word line.
[0058] The RRAM circuit further includes: a plurality of first source lines LSL, and sources of two transistors 11 of the memory cells 10 in the same column are connected to the same first source line LSL.
[0059] like Figure 1 As shown, the sources of the two transistors 11 of the memory cell 10 in the first column are connected to the first source line LSL. <0> , the sources of the two transistors 11 of the memory cell 10 in the second column are connected to the first source line LSL <1> , until the sources of the two transistors 11 of the memory cell 10 in the nth column are connected to the first source line LSL <n-1>.
[0060] In one embodiment, the first source line LSL is a local source line.
[0061] The RRAM circuit further includes: a plurality of second MOS switches 30, wherein a gate of each second MOS switch 30 is connected to a first word line LWL of the same column, and a source of each second MOS switch 30 is connected to a first source line LSL of the same column;
[0062] The drains of all the second MOS switches 30 are commonly connected to the second source line SL.
[0063] like Figure 1 As shown, the gate of the first second MOS switch 30 is connected to the first word line LWL of the first column. <0> The gate of the second MOS switch 30 is connected to the first word line LWL of the second column. <1> , until the gate of the 2nth second MOS switch 30 is connected to the first word line LWL<2n-1> of the 2nth column.
[0064] Sources of two adjacent second MOS switches are connected to the same first source line LSL.
[0065] The RRAM circuit further includes: a plurality of bit lines BL, and all memristors 12 in the same row are connected to the same bit line BL.
[0066] The Reset operation process of the RRAM circuit according to the embodiment of the present disclosure will be described in detail below.
[0067] During the RRAM circuit reset operation, some transistors in the storage array may be selected for reset.
[0068] In one embodiment, the second word line GWL connected to the selected transistor 11 is connected to the first voltage, and the gate voltage on the first MOS switch 21 changes with the sequence, so that the voltage of the first word line LWL connected to the selected transistor 11 increases;
[0069] The second source line SL is connected to a second voltage;
[0070] When the voltage of the first word line LWL connected to the selected transistor 11 rises to a predetermined voltage, the voltage of the first source line LSL connected to the selected transistor 11 is equal to the second voltage.
[0071] In one embodiment, the second word line GWL connected to the selected transistor 11 is connected to the first voltage, and the gate voltage on the first MOS switch 21 changes with the sequence, so that the voltage of the first word line LWL connected to the selected transistor 11 increases, including:
[0072] In the first time period, the gate of the first MOS switch 21 is connected to the first switch voltage, and when the second word line GWL connected to the selected transistor 11 is connected to the first voltage, the voltage of the first word line LWL connected to the selected transistor 11 increases to a third voltage;
[0073] In the second time period, when the gate voltage of the first MOS switch 21 increases from the first switch voltage to the second switch voltage, the voltage of the first word line LWL connected to the selected transistor 11 increases from the third word line voltage to the fourth voltage.
[0074] In one embodiment, during the third time period, the gate voltage of the first MOS switch 21 is pulled down from the second switch voltage to the third switch voltage, and when the second source line SL is connected to the second voltage and the bit line BL connected to the unselected transistor 11 is connected to the fifth voltage, the voltage of the first word line LWL connected to the selected transistor 11 is increased from the fourth voltage to the sixth voltage.
[0075] In one embodiment, the predetermined voltage is equal to the sixth voltage.
[0076] Figure 2 This is the timing diagram of the RRAM circuit during the Reset operation process.
[0077] Specifically, Figure 1 and Figure 2 As shown, for example, the cell A1 in the first row and the first column is selected as the cell for performing the Reset operation, wherein the cell in this embodiment is composed of a transistor and a memristor connected to the transistor.
[0078] In the first time period t1, the buffer applies a voltage of 1.8V to the first MOS switch IOSEL, and the voltage of the bit line BL connected to the selected cell is kept at 0V during the Reset operation. The second word line GWL connected to the selected cell is selected by decoding. <0> =1, unselected second word line GWL =0, then VGWL <0> jumps to 2.5V, then the first word line LWL connected to the selected cell <0> The voltage is clamped at 1.8V-Vth, where Vth is the threshold voltage of the MOS tube.
[0079] In the second time period t2, IOSEL jumps from 1.8V to 2.5V, then LWL <0> The voltage is clamped at 2.5V-Vth.
[0080] In the third time period t3, IOSEL is pulled down from 2.5V to 1.8V, at which time the first MOS switch is turned off, and LWL <0> In the floating state, the bit line BL connected to the unselected cell ( Figure 1 The voltage of the second source line SL jumps to 2.5V, and the unselected cell ( Figure 1 The Cgs (junction capacitance) of the transistor in the cell in the dashed box A2 will be LWL <0> The voltage is coupled to 2.5-Vth+Vcouple, where Vcouple is the voltage on the junction capacitor. <0> When the voltage of VLSL is high enough, <0> = VSL = 2.5V, so during the Reset operation, LSL <0> There is no voltage difference between the selected cell voltage and the Reset voltage, so that the Reset operation effect of the selected cell is better; and the unselected cell ( Figure 1 The voltage of the bit line BL of the cell in the dashed box A2 is connected to the voltage of the first source line LSL. <0> The voltages are equal and no Set operation (misoperation) will occur.
[0081] The disclosed embodiment also describes in detail the Set operation process of the RRAM circuit.
[0082] Figure 3 A schematic diagram of the RRAM circuit provided by the embodiment of the present disclosure when working in Set. Figure 4 This is the timing diagram of the RRAM circuit during the Set operation process.
[0083] like Figure 3 and Figure 4 As shown, when the Set is working, at least one unit is still selected as the unit for the Set to work, for example, the unit A1 in the first row and the first column is selected as the unit for the Set to work.
[0084] When Set is working, the voltage of the bit line BL connected to the selected cell is always kept at 1.8V, the voltage of the bit line BL (Unselected BL) of the unselected cell is 0V, and the voltage of the second source line SL is also 0V. <0> When the voltage of jumps to 2.5V, the first word line LWL connected to the selected cell <0> The voltage is clamped at 1.8V-Vth, at which time LWL <0> The voltage of VLSL increases, making <0> = VSL = 0V, so that the Set operation of the selected unit is better, and the unselected unit ( Figure 1 The voltage of the bit line BL of the cell in the dashed box A2 is connected to the voltage of the first source line LSL. <0> The voltages are equal and no erroneous operation will occur.
[0085] The present disclosure also provides an operating method of an RRAM circuit, which is applied to the RRAM circuit in any one of the above embodiments. Figure 5 A flowchart of an operation method of a RRAM circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the method includes:
[0086] Step 501: Connecting a first voltage to a second word line connected to a selected transistor;
[0087] Step 502: controlling the gate voltage on the first MOS switch to change with time sequence, so that the voltage of the first word line connected to the selected transistor increases;
[0088] Step 503: Connecting a second voltage to the second source line;
[0089] Step 504: When the voltage of the first word line connected to the selected transistor increases to a predetermined voltage, the voltage of the first source line connected to the selected transistor is equal to the second voltage.
[0090] The Reset operation process of the RRAM circuit according to the embodiment of the present disclosure will be described in detail below.
[0091] During the RRAM circuit reset operation, some transistors in the storage array may be selected for reset.
[0092] like Figure 1 and Figure 2 As shown, in one embodiment, a first voltage is connected to the second word line GWL connected to the selected transistor 11; and the gate voltage on the first MOS switch 21 is controlled to change with time sequence so that the voltage of the first word line LWL connected to the selected transistor 11 increases, including:
[0093] In the first time period, the gate of the first MOS switch 21 is connected to the first switch voltage, and when the second word line GWL connected to the selected transistor 11 is connected to the first voltage, the voltage of the first word line LWL connected to the selected transistor 11 increases to a third voltage;
[0094] In the second time period, when the gate voltage of the first MOS switch 21 increases from the first switch voltage to the second switch voltage, the voltage of the first word line LWL connected to the selected transistor 11 increases from the third voltage to the fourth voltage.
[0095] In one embodiment, during the third time period, the gate voltage of the first MOS switch 21 is pulled down from the second switch voltage to the third switch voltage, and when the second source line SL is connected to the second voltage and the bit line BL connected to the unselected transistor 11 is connected to the fifth voltage, the voltage of the first word line LWL connected to the selected transistor 11 is increased from the fourth voltage to the sixth voltage.
[0096] In one embodiment, the predetermined voltage is equal to the sixth voltage.
[0097] Specifically, Figure 1 and Figure 2 As shown, for example, the cell A1 in the first row and the first column is selected as the cell for performing the Reset operation, wherein the cell in this embodiment is composed of a transistor and a memristor connected to the transistor.
[0098] In the first time period t1, the buffer applies a voltage of 1.8V to the first MOS switch IOSEL, and the voltage of the bit line BL connected to the selected cell is kept at 0V during the Reset operation. The second word line GWL connected to the selected cell is selected by decoding. <0> =1, unselected second word line GWL =0, then VGWL <0> jumps to 2.5V, then the first word line LWL connected to the selected cell <0> The voltage is clamped at 1.8V-Vth, where Vth is the threshold voltage of the MOS tube.
[0099] In the second time period t2, IOSEL jumps from 1.8V to 2.5V, then LWL <0> The voltage is clamped at 2.5V-Vth.
[0100] In the third time period t3, IOSEL is pulled down from 2.5V to 1.8V, at which time the first MOS switch is turned off, and LWL <0> In the floating state, the bit line BL connected to the unselected cell ( Figure 1 The voltage of the second source line SL jumps to 2.5V, and the unselected cell ( Figure 1 The Cgs (junction capacitance) of the transistor in the cell in the dashed box A2 will be LWL <0> The voltage is coupled to 2.5-Vth+Vcouple, where Vcouple is the voltage on the junction capacitor. <0> When the voltage of VLSL is high enough, <0> = VSL = 2.5V, so during the Reset operation, LSL <0> There is no voltage difference between the selected cell voltage and the Reset voltage, so that the Reset operation effect of the selected cell is better; and the unselected cell ( Figure 1 The voltage of the bit line BL of the cell in the dashed box A2 is connected to the voltage of the first source line LSL. <0> The voltages are equal and no Set operation (misoperation) will occur.
[0101] The disclosed embodiment also describes in detail the Set operation process of the RRAM circuit.
[0102] Specifically, Figure 3 and Figure 4 As shown, when the Set is working, at least one unit is still selected as the unit for the Set to work, for example, the unit A1 in the first row and the first column is selected as the unit for the Set to work.
[0103] When Set is working, the voltage of the bit line BL connected to the selected cell is always kept at 1.8V, the voltage of the bit line BL (Unselected BL) of the unselected cell is 0V, and the voltage of the second source line SL is also 0V. <0> When the voltage of jumps to 2.5V, the first word line LWL connected to the selected cell <0> The voltage is clamped at 1.8V-Vth, at which time LWL <0> The voltage of VLSL increases, making <0> = VSL = 0V, so that the Set operation of the selected unit is better, and the unselected unit ( Figure 1 The voltage of the bit line BL of the cell in the dashed box A2 is connected to the voltage of the first source line LSL. <0> The voltages are equal and no erroneous operation will occur.
[0104] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.
[0105] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means two or more, unless otherwise clearly and specifically defined.
[0106] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A RRAM circuit, characterized in that: The RRAM circuit comprises: A memory array, the memory array comprising m×n memory cells, each of the memory cells comprising two transistors connected to each other, and two memristors respectively connected to the two transistors; A plurality of first word lines, gates of all transistors in a same column are connected to the same first word line; A plurality of first MOS switches, one end of each of the first MOS switches being connected to a first word line; a plurality of second word lines, each of the second word lines being connected to the other end of the first MOS switch; a plurality of first source lines, sources of two transistors of the memory cells in the same column are connected to the same first source line; a plurality of second MOS switches, wherein a gate of each second MOS switch is connected to the first word line in the same column, and a source of each second MOS switch is connected to the first source line in the same column; A second source line, drains of all the second MOS switches are commonly connected to the second source line; wherein, The second word line connected to the selected transistor is connected to a first voltage, and the gate voltage on the first MOS switch changes with time sequence, so that the voltage of the first word line connected to the selected transistor increases; The second source line is connected to a second voltage; When the voltage of the first word line connected to the selected transistor rises to a predetermined voltage, the voltage of the first source line connected to the selected transistor is equal to the second voltage.
2. The RRAM circuit according to claim 1, wherein: Also includes: A plurality of bit lines, all memristors in the same row are connected to the same bit line.
3. The RRAM circuit according to claim 1, wherein: Also includes: A buffer, gates of all the first MOS switches are commonly connected to the buffer.
4. The RRAM circuit according to claim 2, wherein: The second word line connected to the selected transistor is connected to a first voltage, and the gate voltage on the first MOS switch changes with time sequence, so that the voltage of the first word line connected to the selected transistor increases, including: In a first time period, the gate of the first MOS switch is connected to a first switch voltage, and when the second word line connected to the selected transistor is connected to the first voltage, the voltage of the first word line connected to the selected transistor increases to a third voltage; In the second time period, when the gate voltage of the first MOS switch increases from the first switch voltage to the second switch voltage, the voltage of the first word line connected to the selected transistor increases from the third voltage to the fourth voltage.
5. The RRAM circuit according to claim 4, characterized in that: In the third time period, the gate voltage of the first MOS switch is pulled down from the second switch voltage to the third switch voltage, and when the second source line is connected to the second voltage and the bit line connected to the unselected transistor is connected to the fifth voltage, the voltage of the first word line connected to the selected transistor is increased from the fourth voltage to the sixth voltage.
6. The RRAM circuit according to claim 5, characterized in that: The predetermined voltage is equal to a sixth voltage.
7. A method for operating a RRAM circuit, characterized in that: The RRAM circuit according to any one of claims 1 to 6, wherein the method comprises: Connecting a first voltage to the second word line connected to the selected transistor; Controlling the gate voltage of the first MOS switch to change with time sequence, so that the voltage of the first word line connected to the selected transistor increases; Connecting a second voltage to the second source line; When the voltage of the first word line connected to the selected transistor rises to a predetermined voltage, the voltage of the first source line connected to the selected transistor is equal to the second voltage.
8. The method according to claim 7, characterized in that The method of connecting the second word line connected to the selected transistor to a first voltage and controlling the gate voltage on the first MOS switch to change with time sequence so that the voltage of the first word line connected to the selected transistor increases includes: In a first time period, a first switch voltage is connected to the gate of the first MOS switch, and when the second word line connected to the selected transistor is connected to the first voltage, the voltage of the first word line connected to the selected transistor is increased to a third voltage; In the second time period, when the gate voltage of the first MOS switch increases from the first switch voltage to the second switch voltage, the voltage of the first word line connected to the selected transistor increases from the third voltage to the fourth voltage.
9. The method according to claim 8, characterized in that Also includes: In the third time period, the gate voltage of the first MOS switch is pulled down from the second switch voltage to the third switch voltage, and when the second source line is connected to the second voltage and the bit line connected to the unselected transistor is connected to the fifth voltage, the voltage of the first word line connected to the selected transistor is increased from the fourth voltage to the sixth voltage.
10. The method according to claim 9, characterized in that The predetermined voltage is equal to the sixth voltage.