Memory device and operating method thereof, memory system

Abstract

The present disclosure provides a memory device and an operating method thereof, a memory system, the memory device including a memory array and a peripheral circuit; the memory array including a first finger storage region and a second finger storage region; the first finger storage region and the second finger storage region including a plurality of strings of memory cells; each string of memory cells including a first bottom select transistor; the first bottom select transistor in the first finger storage region having a first threshold voltage, the first bottom select transistor in the second finger storage region having a second threshold voltage; the first threshold voltage being less than the second threshold voltage; the peripheral circuit configured to: in a first pre-charge phase for program verification of the first finger storage region, apply a first bias voltage to the first bottom select transistor; in a first sensing phase after the first pre-charge phase, apply a second bias voltage to the first bottom select transistor; the first bias voltage being less than the second bias voltage; the second bias voltage being less than the second threshold voltage and greater than the first threshold voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] To meet the demands for higher memory integration, three-dimensional memories, including memory cells arranged in three dimensions, have been proposed. However, as memory integration increases further, the number of memory cells connected by the same word line in a three-dimensional memory also increases, reducing the efficiency of programming these memory cells and negatively impacting the performance of the memory device. Summary of the Invention

[0003] In view of the above, this disclosure provides a memory device and its operation method, and a memory system, in order to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a memory device, including a memory array and peripheral circuitry coupled to the memory array; wherein,

[0006] The storage array includes a first finger storage region and a second finger storage region; both the first finger storage region and the second finger storage region include multiple memory cell strings; each memory cell string includes a first bottom-select transistor; the first bottom-select transistor in the first finger storage region has a first threshold voltage, and the first bottom-select transistor in the second finger storage region has a second threshold voltage; the first threshold voltage is less than the second threshold voltage; the peripheral circuitry is configured as follows:

[0007] During the first pre-charge phase of performing programming verification operations on the memory cells in the first memory region, a first bias voltage is applied to the first bottom selection transistor;

[0008] In a first sensing phase following the first pre-charging phase, a second bias voltage is applied to the first bottom selection transistor; the first bias voltage is less than the second bias voltage; the second bias voltage is less than the second threshold voltage and greater than the first threshold voltage.

[0009] In one alternative implementation, each of the memory cell strings further includes a second bottom select transistor, wherein the second bottom select transistor in the first finger memory region has a third threshold voltage, and the second bottom select transistor in the second finger memory region has a fourth threshold voltage; the third threshold voltage is greater than the fourth threshold voltage.

[0010] The peripheral circuit is further configured to apply a first on-state voltage to the second bottom selection transistor during the first pre-charge phase and the first sensing phase; the first on-state voltage is greater than the third threshold voltage.

[0011] In an alternative implementation, each of the memory cell strings further includes a third bottom select transistor; the third bottom select transistor is located between the first bottom select transistor and the second bottom select transistor; the third bottom select transistor has a fifth threshold voltage;

[0012] The peripheral circuit is further configured to apply a second on-state voltage to the third bottom selection transistor during the first pre-charge phase and the first sensing phase; the second on-state voltage is greater than the fifth threshold voltage.

[0013] In one alternative implementation, the first bias voltage is greater than or equal to the negative second turn-on voltage, and the second bias voltage is less than the second turn-on voltage.

[0014] In an alternative implementation, the memory array further includes a common source line connected to each of the memory cell strings, and each of the memory cell strings further includes a fourth bottom-select transistor, the fourth bottom-select transistor being closer to the common source line than the first bottom-select transistor and the second bottom-select transistor; the fourth bottom-select transistor has a sixth threshold voltage;

[0015] The peripheral circuit is further configured to apply a third on-state voltage to the fourth bottom selection transistor during the first pre-charge phase and the first sensing phase; the third on-state voltage is greater than the sixth threshold voltage.

[0016] In one alternative implementation, the first bias voltage is greater than or equal to the negative third turn-on voltage, and the second bias voltage is less than the third turn-on voltage.

[0017] In an alternative implementation, the peripheral circuitry is further configured as follows:

[0018] In the second pre-charge phase of the programming verification operation of the memory cell in the second finger memory area, a fourth turn-on voltage is applied to the first bottom selection transistor and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage.

[0019] In the second sensing phase following the second pre-charging phase, the fourth turn-on voltage is applied to the first bottom-select transistor, and the fourth bias voltage is applied to the second bottom-select transistor; the third bias voltage is less than the fourth bias voltage; the fourth bias voltage is less than the third threshold voltage and greater than the fourth threshold voltage.

[0020] In one alternative implementation, each of the memory cell strings further includes a top selection transistor; the peripheral circuitry is also configured to:

[0021] During the first pre-charge phase, the top selection transistor in the first finger storage area is turned on;

[0022] During the first sensing phase, the unselected top selection transistors in the first finger memory area are turned off, and the selected top selection transistors in the first finger memory area are turned on.

[0023] During the first pre-charge phase and the first sensing phase, the top selection transistor in the second finger memory area is turned off.

[0024] In a second aspect, embodiments of this disclosure provide a memory system, including:

[0025] At least one memory device according to any of the above embodiments;

[0026] A controller is coupled to and configured to control the memory device.

[0027] Thirdly, embodiments of this disclosure provide a method for operating a memory device, including:

[0028] In the first pre-charge phase of performing programming verification operations on the memory cells in the first memory region, a first bias voltage is applied to the first bottom selection transistor in each memory cell string;

[0029] In the first sensing phase following the first pre-charge phase, a second bias voltage is applied to the first bottom select transistor; the first bias voltage is less than the second bias voltage; the second bias voltage is less than the second threshold voltage of the first bottom select transistor in the second finger memory area and greater than the first threshold voltage of the first bottom select transistor in the first finger memory area.

[0030] In one optional implementation, the operation method further includes:

[0031] During the first pre-charge phase and the first sensing phase, a first on-state voltage is applied to the second bottom select transistor in each of the memory cell strings; the third threshold voltage of the second bottom select transistor in the first finger memory region is greater than the fourth threshold voltage of the second bottom select transistor in the second finger memory region; the first on-state voltage is greater than the third threshold voltage.

[0032] In one optional implementation, the operation method further includes:

[0033] During the first pre-charge phase and the first sensing phase, a second turn-on voltage is applied to a third bottom-select transistor located between the first bottom-select transistor and the second bottom-select transistor; the second turn-on voltage is greater than a fifth threshold voltage of the third bottom-select transistor.

[0034] In one alternative implementation, the first bias voltage is greater than or equal to the negative second turn-on voltage, and the second bias voltage is less than the second turn-on voltage.

[0035] In one optional implementation, the operation method further includes:

[0036] During the first pre-charge phase and the first sensing phase, a third turn-on voltage is applied to a fourth bottom-select transistor that is closer to the common source line than the first bottom-select transistor and the second bottom-select transistor; the third turn-on voltage is greater than the sixth threshold voltage of the fourth bottom-select transistor.

[0037] In one alternative implementation, the first bias voltage is greater than or equal to the negative third turn-on voltage, and the second bias voltage is less than the third turn-on voltage.

[0038] In one optional implementation, the operation method further includes:

[0039] In the second pre-charge phase of programming and verifying the memory cells in the second finger memory region, a fourth turn-on voltage is applied to the first bottom selection transistor, and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage.

[0040] In the second sensing phase following the second pre-charging phase, the fourth turn-on voltage is applied to the first bottom-select transistor, and the fourth bias voltage is applied to the second bottom-select transistor; the third bias voltage is less than the fourth bias voltage; the fourth bias voltage is less than the third threshold voltage and greater than the fourth threshold voltage.

[0041] In one optional implementation, the operation method further includes:

[0042] During the first pre-charge phase, the top selection transistor in the first finger memory area is turned on;

[0043] During the first sensing phase, the unselected top selection transistors in the first finger memory area are turned off, and the selected top selection transistors in the first finger memory area are turned on.

[0044] During the first pre-charge phase and the first sensing phase, the top selection transistor in the second finger memory area is turned off.

[0045] In the technical solution provided in this disclosure, the memory array in the memory device includes a first finger memory region and a second finger memory region divided based on the threshold voltage of a first bottom-select transistor. The peripheral circuit is configured to apply a first bias voltage to the first bottom-select transistor during the pre-charging phase of programming and verifying the memory cells in the first finger memory region, and to apply a second bias voltage to the first bottom-select transistor during the sensing phase after the pre-charging phase. The first bias voltage is lower than the second bias voltage. This can reduce the tendency of the voltage on the first bottom-select transistor to drift upward due to the coupling effect, so that the actual voltage on the first bottom-select transistor can be stabilized near the second bias voltage, and the first bottom-select transistor in the second finger memory region is kept in the off state. This reduces the drift of the threshold voltage of the memory cells in the second finger memory region due to the hot carrier injection effect, thereby improving the efficiency of the programming and verification operation and further improving the efficiency and reliability of the programming operation. Attached Figure Description

[0046] Figure 1 A schematic diagram of an exemplary system with a memory system provided in the embodiments of this disclosure;

[0047] Figure 2 A schematic diagram of an exemplary memory card with a memory system provided for embodiments of this disclosure;

[0048] Figure 3 A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this disclosure;

[0049] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuitry provided for embodiments of this disclosure;

[0050] Figure 5 A schematic cross-sectional view of a storage array including strings of storage cells, provided for an embodiment of this disclosure;

[0051] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuitry, provided for embodiments of this disclosure;

[0052] Figure 7 A schematic diagram of a memory array in a memory device provided in an embodiment of this disclosure;

[0053] Figure 8 A schematic diagram showing the distribution of threshold voltages of the first bottom-select transistor and the second bottom-select transistor provided in an embodiment of this disclosure;

[0054] Figure 9 Circuit diagram of the memory array provided in the embodiments of this disclosure Figure 1 ;

[0055] Figure 10 A voltage curve for performing programming verification operations on memory cells in the first memory region, provided in an embodiment of this disclosure;

[0056] Figure 11 Circuit diagram of the memory array provided in the embodiments of this disclosure Figure 2 ;

[0057] Figure 12 Voltage curve two for performing programming verification operations on memory cells in the first memory area, provided in this embodiment of the disclosure;

[0058] Figure 13 Voltage curves for programming verification operations on memory cells in the second finger memory area provided in embodiments of this disclosure;

[0059] Figure 14 This is a flowchart illustrating the operation method of a memory device provided in an embodiment of this disclosure. Detailed Implementation

[0060] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0061] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0062] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0063] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0065] Figure 1 This is a schematic diagram of an exemplary system with a memory device provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host device 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to or receive data from the memory system 102.

[0066] In some embodiments, memory controller 104 is coupled to memory device 103 and host device 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host device 101. In some embodiments, memory controller 104 is designed to operate in low duty cycle environments, such as in Secure Digital Memory Card (SD card), Compact Flash Card (CFC), Universal Serial Bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in Solid State Drives (SSDs) or Embedded Multi-Media Cards (eMMCs).

[0067] The memory controller 104 can be configured to control the operation of the memory device 103, such as read, erase, and program operations. The memory controller 104 can also be configured to manage various functions relating to data stored or to be stored in the memory device 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 104 is also configured to process error correction codes relating to data read from or written to the memory device 103. The memory controller 104 can also perform any other suitable functions, such as formatting the memory device 103.

[0068] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0069] In such Figure 2In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a universal flash storage (UFS) card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The host device 101) is coupled to the memory card connector 202. In such a... Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to host devices (e.g., Figure 1 The SSD connector 204 is coupled to the host device 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0070] Figure 4 The circuit diagram of an exemplary memory device 300 including peripheral circuitry is provided for some embodiments. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0071] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0072] like Figure 4 As shown, each memory cell string 304 may include a bottom select gate (BSG) 307 at its source end and a top select gate (TSG) 306 at its drain end. The bottom select gate 307 and top select gate 306 can be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 within the same memory block 303 can be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 within the same memory block 303 have a common source (ACS). According to some embodiments, the top select gate 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselection voltage (e.g., 0V) to the corresponding top select transistor 306 via one or more top select lines (TSLs) and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselection voltage (e.g., 0V) to the corresponding bottom select transistor 307 via one or more bottom select lines (BSLs) 309.

[0073] like Figure 4As shown, the memory cell string 304 can be organized into multiple memory blocks 303, each of which can have a common source line (CSL) 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0074] Figure 5 This is a cross-sectional schematic diagram of a storage array including strings of storage cells, provided as an embodiment of this disclosure. (See attached diagram.) Figure 5 As shown, the memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 stacked alternately in sequence, and a channel structure 403 perpendicularly penetrating the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be stacked alternately, and two adjacent gate layers 401 are separated by an insulating layer 402. The number of memory cells included in the memory array is mainly related to the logarithm of the number of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0075] The constituent materials of the gate layer 401 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory cell string. The gate layer 401 at the top of the stacked structure 400 may extend laterally as a top select line, the gate layer 401 at the bottom of the stacked structure 400 may extend laterally as a bottom select line, and the gate layer 401 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0076] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0077] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating fill layer. In some embodiments, the channel layer includes silicon, for example, polysilicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the channel layer, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0078] Return to reference Figure 4 The peripheral circuitry 302 can be coupled to the memory array 301 via bit lines 311, word lines 312, common-source line 310, bottom select line 309, and top select line 308. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit lines 311, word lines 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, additional components may be included. Figure 6 Additional peripheral circuitry not shown.

[0079] Page buffer / sensor amplifier 501 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 505. In one example, page buffer / sensor amplifier 501 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 501 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cells coupled to the selected word line. In yet another example, page buffer / sensor amplifier 501 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 502 can be configured to be controlled by control logic unit 505 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 504.

[0080] The row decoder / word line driver 503 can be configured to be controlled by the control logic unit 505 and to select / deselect memory blocks of the memory array 301 and to select / deselect word lines of the memory blocks. The row decoder / word line driver 503 can also be configured to drive word lines using word line voltages generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 503 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 504 can be configured to be controlled by the control logic unit 505 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0081] Control logic unit 505 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 506 can be coupled to control logic unit 505 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 507 can be coupled to control logic unit 505 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic unit 505, as well as to buffer status information received from control logic unit 505 and relay it to memory controller. Flash interface 507 can also be coupled to column decoder / bit line driver 502 via data bus 508 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0082] As the integration of memory devices continues to increase and the density of memory arrays continues to increase, the number of memory cells connected to the same word line also increases. When one or more memory cells need to be selected for programming operations, the coupling effect between the memory cell string containing the unselected memory cells connected to the selected word line and the selected word line will cause the voltage settling time on the selected word line to increase, thereby reducing programming efficiency. In addition, the current required to make the selected word line reach the target voltage increases, resulting in an increase in peak current during programming operations and an increase in the power consumption of the memory device.

[0083] In this regard, embodiments of the present disclosure provide a memory device, which includes a memory array and peripheral circuitry coupled to the memory array.

[0084] Figure 7 A schematic diagram of a storage array provided as a specific example of this disclosure, such as... Figure 7 As shown, the storage array includes a first finger storage area 10 and a second finger storage area 20 connected to the common source line CSL. Both the first finger storage area 10 and the second finger storage area 20 include multiple storage cell strings. For example, the first finger storage area 10 includes storage cell strings Str0, Str1, Str2 and Str3, and the second finger storage area 20 includes storage cell strings Str4, Str5, Str6 and Str7.

[0085] It should be noted that, Figure 7 This example only illustrates a storage array comprising two finger storage areas, each containing four strings of storage cells, but the present disclosure is not limited thereto. In other embodiments, the storage array may include more than two finger storage areas, each containing more than four strings of storage cells. The present disclosure does not limit the number of finger storage areas in the storage array or the number of strings of storage cells in each finger storage area.

[0086] In this disclosure embodiment, reference continues to be made to Figure 7 Each memory cell string includes multiple bottom select transistors: a first bottom select transistor BSG1, a second bottom select transistor BSG2, a third bottom select transistor BSG3, and a fourth bottom select transistor BSG4. The gates of bottom select transistors located in the same row are connected to the same bottom select line, meaning that the external circuit can apply voltage to the bottom select transistors located in the same row through the bottom select line.

[0087] In some embodiments, each memory cell string further includes a top select transistor (TSG), a memory cell connected to word lines WL1, WL2, and WL3, and a pseudo memory cell connected to a pseudo word line (DW).

[0088] It should be noted that, Figure 7The number of the first bottom selection transistor BSG1, the second bottom selection transistor BSG2, the third bottom selection transistor BSG3, and the fourth bottom selection transistor BSG4, the number of the top selection transistor TSG, and the number of word lines and pseudo word lines are merely examples, and this disclosure does not limit the specific number of these structures.

[0089] In some embodiments, the first bottom select transistor BSG1 located in the first finger storage region 10 has a first threshold voltage Vt1, the first bottom select transistor BSG1 located in the second finger storage region 20 has a second threshold voltage Vt2, and the first threshold voltage Vt1 is less than the second threshold voltage Vt2.

[0090] In some embodiments, the second bottom select transistor BSG2 located in the first finger storage region 10 has a third threshold voltage Vt3, the second bottom select transistor BSG2 located in the second finger storage region 20 has a fourth threshold voltage Vt4, and the third threshold voltage Vt3 is greater than the fourth threshold voltage Vt4.

[0091] In a specific example, such as Figure 8As shown, the first threshold voltage Vt1 and the fourth threshold voltage Vt4 can be in the range of -4V to -2V, and the second threshold voltage Vt2 and the third threshold voltage Vt3 can be in the range of 2V to 4V. When it is only necessary to turn on the memory cell string in the first finger memory area 10, a bias voltage can be applied to the first bottom selection transistor BSG1, and a turn-on voltage can be applied to the other bottom selection transistors. Specifically, the bias voltage can have any voltage value in the range of -2V to 2V. The first threshold voltage Vt1 of the first bottom selection transistor BSG1 in the first finger memory area 10 is lower than the bias voltage, and the second threshold voltage Vt2 of the first bottom selection transistor BSG1 in the second finger memory area 20 is higher than the bias voltage. The first bottom selection transistor BSG1 in the first finger memory area 10 is turned on, the first bottom selection transistor BSG1 in the second finger memory area 20 is turned off, and the other bottom selection transistors are all turned on. Thus, the memory cell string in the second finger memory area 20 can be in a floating state, and only the memory cells in the first finger memory area 10 can be operated. Similarly, when it is only necessary to turn on the memory cell string in the second finger memory area 20, a bias voltage can be applied to the second bottom selection transistor BSG2, and a turn-on voltage can be applied to the other bottom selection transistors. The third threshold voltage Vt3 of the second bottom selection transistor BSG2 in the first finger memory area 10 is higher than the bias voltage, and the fourth threshold voltage Vt4 of the second bottom selection transistor BSG2 in the second finger memory area 20 is lower than the bias voltage. The second bottom selection transistor BSG2 in the first finger memory area 10 is turned off, and the second bottom selection transistor BSG2 in the second finger memory area 20 is turned on. All other bottom selection transistors are turned on. Thus, the memory cell string in the first finger memory area 10 can be in a floating state, so that only the memory cells in the second finger memory area 20 can be operated.

[0092] In the example above, the first bottom select transistor BSG1, located in the same row, has two different threshold voltages. Correspondingly, the second bottom select transistor BSG2, located in the same row, also has two different threshold voltages. This allows the memory array to be divided into a first finger memory region 10 and a second finger memory region 20. By applying a bias voltage to the first bottom select transistor BSG1 or the second bottom select transistor BSG2, individual operation can be achieved for either the first finger memory region 10 or the second finger memory region 20. That is, only one finger memory region can be selected, while the memory cell strings in the unselected finger memory regions can be in a floating state. This reduces the coupling effect of the unselected memory cell strings on the selected word line, shortens the word line voltage setup time, and reduces the peak current, thereby improving operating efficiency while reducing the power consumption of the memory device.

[0093] In some embodiments, each memory cell string includes a third bottom-select transistor BSG3 located between the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2, and a fourth bottom-select transistor BSG4 located closer to the common source line CSL than the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2. The third bottom-select transistors BSG3 located in the first finger memory region 10 and the second finger memory region 20 each have a fifth threshold voltage Vt5, and the fourth bottom-select transistors BSG4 located in the first finger memory region 10 and the second finger memory region 20 each have a sixth threshold voltage Vt6.

[0094] In some specific examples, before programming the memory cells, the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2 can be programmed first to the first threshold voltage Vt1 and the third threshold voltage Vt3 in the first memory region 10, and the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2 in the second memory region 20 can be programmed second to the second threshold voltage Vt2 and the fourth threshold voltage Vt4, respectively. During this process, the third bottom-select transistor BSG3, located between the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2, can buffer the electric field between the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2 during the programming verification operation, and the fourth bottom-select transistor BSG4 can act as a bottom-turn-off during the programming operation.

[0095] In a specific example, Figure 9 for Figure 7 The simplified circuit diagram corresponding to the memory array shown is as follows: Figure 10 Voltage curves when performing programming verification operations on memory cells in the first memory area 10.

[0096] Combined with reference Figure 7 and Figure 9Storage cell string 110 and storage cell string 111 can be any two storage cell strings in the first reference storage area 10. Storage cell string 110 is the storage cell string containing the storage cell requiring programming verification, i.e., storage cell string 110 is the selected storage cell string in the reference storage area, which includes a top selection transistor TSG1. Storage cell string 111 is the unselected storage cell string in the selected reference storage area, which includes a top selection transistor TSG2. Storage cell string 210 can be any storage cell string in the second reference storage area 20. Storage cell string 210 is the unselected storage cell string in the reference storage area, which includes a top selection transistor TSG3. Here, the gates of top selection transistors TSG1, TSG2, and TSG3 are respectively connected to three different top selection lines.

[0097] In this embodiment of the disclosure, word line WL1 is the selected word line, and word lines WL2 and WL3 are unselected word lines. In other embodiments, word line WL2 or word line WL3 may also be selected word lines.

[0098] In some embodiments, such as Figure 10 As shown, the programming verification operation performed on the selected memory cell in the first memory area 10 includes two stages: a first pre-charge stage P1 and a first sensing stage P2. The first sensing stage P2 is the stage after the first pre-charge stage P1 in which multiple sensing operations are performed on the selected memory cell in the first memory area 10.

[0099] In some embodiments, during the first pre-charge phase P1, the peripheral circuitry is configured to: apply a turn-on voltage Vpass to the top-select transistor in the first finger memory region 10 to turn on the top-select transistor in the first finger memory region 10, i.e., both the top-select transistor TSG1 in memory cell string 110 and the top-select transistor TSG2 in memory cell string 111 are turned on; and apply a ground voltage Vss to the top-select transistor in the second finger memory region 20 to turn off the top-select transistor in the second finger memory region 20, i.e., the top-select transistor in memory cell string 210 is turned off. TSG3 is turned off; an on-state voltage Vpass is applied to the unselected word lines WL2 / WL3 and the pseudo-word line DW; a first on-state voltage Vpass1 is applied to the second bottom select transistor BSG2, which is greater than the third threshold voltage Vt3; a second on-state voltage Vpass2 is applied to the third bottom select transistor BSG3, which is greater than the fifth threshold voltage Vt5; a third on-state voltage Vpass3 is applied to the fourth bottom select transistor BSG4, which is greater than the sixth threshold voltage Vt6.

[0100] It should be noted that, in Figure 12In the example shown, the starting voltages of word lines WL1, WL2, and WL3, as well as the pseudo-word line DW, are all the power supply voltage Vdd, which can shorten the voltage build-up time on the word lines, but this disclosure is not limited thereto. In other embodiments, the starting voltages of word lines WL1, WL2, and WL3, as well as the pseudo-word line DW, can all be the ground voltage Vss. In this case, it is necessary to apply a conduction voltage to the selected word line WL1 during the first pre-charge phase P1 to turn on the unselected memory cell string in the first memory area 10.

[0101] In the embodiments of this disclosure, apart from the first turn-on voltage Vpass1, the second turn-on voltage Vpass2, the third turn-on voltage Vpass3, and the fourth turn-on voltage Vpass4, which have specific limitations on their relative magnitudes, other turn-on voltages Vpass refer to the voltages that enable the corresponding memory cells or transistors to turn on, and this disclosure does not limit their specific magnitudes.

[0102] In some embodiments, during the first pre-charge phase P1, the peripheral circuit is configured to apply a higher voltage to the bottom selection transistors other than the first bottom selection transistor BSG1 so that all other bottom selection transistors are in the on state. At this time, the voltage applied to the first bottom selection transistor BSG1 needs to be sufficient to turn on the first bottom selection transistor BSG1 located in the first finger memory region 10 and turn off the first bottom selection transistor BSG1 located in the second finger memory region 20. Thus, the memory cell strings in the first finger memory region 10 are all in the on state, the channel is coupled to the common source line CSL, and the common source line CSL is coupled to the ground voltage Vss. This allows the channel voltage in the first finger memory region 10 to be set to the ground voltage Vss, while the channels of the memory cell strings in the second finger memory region 20 are in a floating state, and the channel voltage is coupled to a higher voltage by the gate voltage.

[0103] In this embodiment of the disclosure, the peripheral circuit is configured to perform a pre-charge operation only on the memory cell strings in the first finger memory region 10 during the first pre-charge phase P1. On the one hand, by performing a pre-charge operation on all memory cell strings in the first finger memory region 10, the channel voltage of the unselected memory cell strings in the first finger memory region 10 can be set to the ground voltage Vss. Thus, in the subsequent first sensing phase P2, taking the unselected memory cell string 111 as an example, when the memory cell connected to the selected word line WL1 in the memory cell string 111 is in the off state, the voltage of the channel between the top selection transistor TSG2 and the memory cell, as well as the voltage of the channel between the memory cell and the first bottom selection transistor BSG1, are both kept at the ground voltage Vss, and a large voltage difference will not be generated near the channel of the memory cell. This can effectively reduce the hot carrier injection (HCI) effect caused by the large voltage difference and reduce the threshold voltage drift generated by the unselected memory cell during the programming operation of the selected memory cell. On the other hand, during the first pre-charge phase P1, the memory cell strings in the second finger memory area 20 are all in a floating state, which can reduce the coupling effect between the memory cell strings in the second finger memory area 20 and the selected word line WL1, thereby shortening the voltage establishment time on the word line WL1 and improving the efficiency of the programming verification operation.

[0104] In some embodiments, such as Figure 10 As shown, in the first pre-charge phase P1, to turn on the first bottom-select transistor BSG1 located in the first finger storage region 10 and turn off the first bottom-select transistor BSG1 located in the second finger storage region 20, the peripheral circuit can be configured to apply a second bias voltage Vbias2 to the first bottom-select transistor BSG1. The second bias voltage Vbias2 is less than the second threshold voltage Vt2 and greater than the first threshold voltage Vt1. However, in this case, as... Figure 10 As shown by the dashed line in the voltage curve corresponding to the first bottom select transistor BSG1, during the first pre-charge phase P1, when the external circuit applies a higher voltage to the bottom select transistors other than the first bottom select transistor BSG1, during the voltage rise period, due to the coupling effect between the bottom select lines, the voltage on the first bottom select transistor BSG1 may be coupled to a higher voltage, which may exceed the second threshold voltage Vt2, causing the first bottom select transistor BSG1 in the second finger memory area 20 to be unable to be completely turned off.

[0105] like Figure 11As shown, in the above embodiment, taking the memory cell string 210 in the second finger memory area 20 as an example, since the voltage on the first bottom select transistor BSG1 is coupled to a higher voltage, the first bottom select transistor BSG1 in the memory cell string 210 cannot be completely turned off, and the memory cell in the memory cell string 210 connected to the selected word line WL1 is still in the off state, causing the channel between the memory cell and the first bottom select transistor BSG1 to be coupled to the common source line CSL, and the channel voltage is set to the ground voltage Vss. The channel between the memory cell and the top select transistor TSG3 is still in the floating state, and the channel voltage is still coupled to a higher voltage by the gate voltage. In this case, a large voltage difference will be generated in the channel near the memory cell, and the threshold voltage of the memory cell may drift due to the hot carrier injection effect.

[0106] In some embodiments, the peripheral circuitry is configured to: apply a first bias voltage Vbias1 to the first bottom select transistor BSG1 during a first precharge phase P1 in which a programming verification operation is performed on the memory cells in the first pointer memory region 10; and apply a second bias voltage Vbias2 to the first bottom select transistor BSG2 during a first sensing phase P2 after the first precharge phase P1, wherein the first bias voltage Vbias1 is less than the second bias voltage Vbias2.

[0107] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative second turn-on voltage Vpass2, and the second bias voltage Vbias2 is less than the second turn-on voltage Vpass2.

[0108] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative third turn-on voltage Vpass3, and the second bias voltage Vbias2 is less than the third turn-on voltage Vpass3.

[0109] In a specific example, such as Figure 12As shown, in the voltage curve corresponding to the first bottom select transistor BSG1, the solid line represents the voltage applied to the first bottom select transistor BSG1 by the external circuit, and the dashed line represents the actual voltage on the first bottom select transistor BSG1. During the first pre-charge phase P1, a lower first bias voltage Vbias1 is applied to the first bottom select transistor BSG1. This reduces the upward drift of the voltage on the first bottom select transistor BSG1 caused by the coupling effect between the bottom select lines, thus stabilizing the actual voltage on the first bottom select transistor BSG1 near the second bias voltage Vbias2. The first bottom select transistor BSG1 in the second finger memory region 20 remains off, reducing the drift of the threshold voltage of the memory cells in the second finger memory region 20 caused by the hot carrier injection effect. This improves the efficiency of the programming verification operation while further enhancing the reliability of the memory device programming operation.

[0110] In the example above, the peripheral circuit applies a first bias voltage Vbias1 with a fixed voltage value to the first bottom selection transistor BSG1 and continues until the first pre-charge phase P1 ends, but this disclosure is not limited thereto.

[0111] In some embodiments, the peripheral circuit may stop applying the first bias voltage Vbias1 to the first bottom selection transistor BSG1 before the first pre-charge phase P1 ends, and the voltage applied by the peripheral circuit to the first bottom selection transistor BSG1 begins to gradually rise from the first bias voltage Vbias1 to the second bias voltage Vbias2.

[0112] In some embodiments, the voltage value of the first bias voltage Vbias1 can also be continuously varied. It can be gradually reduced to a minimum value by the ground voltage Vss in the initial stage of the first pre-charge stage P1, and then gradually increased to a maximum value from the minimum value. Alternatively, other suitable variation methods can be used to dynamically adjust the actual voltage on the first bottom select transistor BSG1.

[0113] It is understandable that the coupling effect on the voltage of the first bottom select transistor BSG1 is mainly concentrated in the initial stage of the first precharge phase P1, that is, the stage in which the voltage on the bottom select line and word line connected with other bottom select transistors is established. In this stage, the voltage on the bottom select line and word line gradually rises from the initial voltage to a higher turn-on voltage. The voltage change rate is large, which will enhance the coupling effect and cause the voltage on the first bottom select transistor BSG1 to drift upward. Therefore, the first bias voltage Vbias1 can be applied to the first bottom select transistor BSG1 only in the first precharge phase P1 or in the initial stage of the first precharge phase P1.

[0114] In some embodiments, continue to refer to Figure 12 In the first sensing phase P2 following the first pre-charging phase P1, the peripheral circuit is configured to: apply a second bias voltage Vbias2 to the first bottom selection transistor BSG1; continue to apply a first turn-on voltage Vpass1 to the second bottom selection transistor BSG2, apply a second turn-on voltage Vpass2 to the third bottom selection transistor BSG3, and apply a third turn-on voltage Vpass3 to the fourth bottom selection transistor BSG4; turn off the unselected top selection transistor TSG2 in the first finger memory area 10; turn off the top selection transistor TSG3 in the second finger memory area 20; keep the selected top selection transistor TSG1 in the first finger memory area 10 on; continue to apply the turn-on voltage Vpass to the unselected word lines WL2 / WL3 and pseudo word lines; and sequentially apply a first verification voltage Vpv1, a second verification voltage Vpv2, and a third verification voltage Vpv3 ​​to the selected word line WL1 to perform a sensing operation on the selected memory cell.

[0115] Here, the first sensing stage P2 includes three sensing operations as an example, but this disclosure is not limited to this. In other embodiments, the sensing stage may include only two sensing operations or more than three sensing operations.

[0116] In some embodiments, such as Figure 12 As shown, the peripheral circuit is further configured as follows: In the first preparation stage P3 after the first sensing stage P2, a conduction voltage Vpass is applied to the selected word line WL1 to turn on the selected memory cell, and the accumulated electrons in the selected memory cell string channel can be discharged; In the second preparation stage P4 after the first preparation stage P3, a power supply voltage Vdd is applied to the word line WL1 to gradually reduce the voltage on the word line WL1 from the conduction voltage Vpass to the power supply voltage Vdd, and the remaining electrons in the channel are discharged from the bit line direction; In the third preparation stage P5 after the second preparation stage P4, a power supply voltage Vdd is applied to the word line WL2, word line WL3 and pseudo word line DW, and a ground voltage Vss is applied to the other selection lines to restore the voltage of the word lines and each selection line to the voltage before the programming verification operation.

[0117] In another specific example, Figure 13 The voltage curve during the programming verification operation of the memory cells in the second finger memory area 20, such as Figure 13As shown, the peripheral circuit is further configured to: in the second pre-charge phase P6, which performs programming verification operations on the memory cells in the second finger storage area 20, apply a fourth on-state voltage Vpass4 to the first bottom selection transistor BSG1 and apply a third bias voltage Vbias3 to the second bottom selection transistor BSG2; the fourth on-state voltage Vpass4 is greater than the second threshold voltage Vt2; in the second sensing phase P7 after the second pre-charge phase P6, apply the fourth on-state voltage Vpass4 to the first bottom selection transistor BSG1 and apply a fourth bias voltage Vbias4 to the second bottom selection transistor BSG2; the third bias voltage Vbias3 is less than the fourth bias voltage Vbias4; the fourth bias voltage Vbias4 is less than the third threshold voltage Vt3 and greater than the fourth threshold voltage Vt4.

[0118] In this embodiment of the present disclosure, similar to the programming verification operation performed on the memory cells in the first finger memory region 10, when performing the programming verification operation on the memory cells in the second finger memory region 20, the peripheral circuit first applies a lower third bias voltage Vbias3 to the second bottom select transistor BSG2. This can reduce the tendency of the voltage on the second bottom select transistor BSG2 to drift upward due to the coupling effect between the bottom select lines or the coupling effect between the pseudo word line and the bottom select line. As a result, the actual voltage on the second bottom select transistor BSG2 can be stabilized near the fourth bias voltage Vbias4. The second bottom select transistor BSG2 in the first finger memory region 10 remains in the off state, reducing the drift of the threshold voltage of the memory cells in the first finger memory region 10 due to the hot carrier injection effect. This can improve the efficiency of the programming verification operation and improve the programming efficiency, while further improving the reliability of the memory device programming operation.

[0119] It should be noted that, in the embodiments disclosed herein, the peripheral circuit is configured to perform programming operations including multiple programming cycles on the memory cells in the first finger memory area 10 or the second finger memory area 20. Each programming cycle may include a programming pulse application operation and a programming verification operation. For multiple programming cycles, the programming pulse applied to the selected word line may be incremental, and the verification voltage applied to the selected word line may also be different. Figure 12 and Figure 13 The voltage curve is shown when a programming verification operation is performed on the memory cell. The example above only takes the programming verification operation in a programming cycle as an example. Before the programming verification operation, the peripheral circuit is also configured to perform a programming pulse application operation.

[0120] In this embodiment, the specific composition and functional implementation of the peripheral circuit can be referred to the foregoing description of... Figure 6As described above, in the peripheral circuit, the control logic unit can control the row decoder / word line driver to apply the voltage generated by the voltage generator to the top selection transistor, bottom selection transistor, word line, and pseudo word line in the above embodiment via the row decoder / word line driver.

[0121] Based on a concept similar to the memory devices described above, this disclosure also provides a memory system comprising: at least one memory device as described in any of the foregoing embodiments; and a controller coupled to and configured to control the memory device. For the specific composition and functional implementation of the memory system, please refer to the preceding description. Figures 1 to 7 For the sake of brevity, the description will not be repeated here.

[0122] Based on the same concept as the memory device described above, this disclosure also provides a method for operating a memory device. Figure 14 This is a flowchart illustrating the operation method of the memory device, which includes the following steps:

[0123] Step S1000: In the first pre-charge stage of performing programming verification operation on the memory cells in the first pointer memory area, a first bias voltage is applied to the first bottom selection transistor in each memory cell string;

[0124] Step S2000: In the first sensing phase after the first pre-charging phase, a second bias voltage is applied to the first bottom select transistor; the first bias voltage is less than the second bias voltage; the second bias voltage is less than the second threshold voltage of the first bottom select transistor in the second finger memory area and greater than the first threshold voltage of the first bottom select transistor in the first finger memory area.

[0125] Combined with reference Figure 7 , Figure 12 and Figure 14 Step S1000 includes: in a first pre-charge phase P1, during which a programming verification operation is performed on the memory cells in the first finger memory region 10, applying a first bias voltage Vbias1 to the first bottom selection transistor BSG1. Step S2000 includes: in a first sensing phase P2 following the first pre-charge phase P1, applying a second bias voltage Vbias2 to the first bottom selection transistor BSG1, wherein the first bias voltage Vbias1 is less than the second bias voltage Vbia2, and the second bias voltage Vbia2 is less than the second threshold voltage Vt2 of the first bottom selection transistor BSG1 in the second finger memory region 20 and greater than the first threshold voltage Vt1 of the first bottom selection transistor in the first finger memory region 10.

[0126] In some embodiments, the method of operating the memory device further includes: applying a first on-state voltage Vpass1 to the second bottom select transistor BSG2 in each memory cell string during a first pre-charge phase P1 and a first sensing phase P2; the third threshold voltage Vt3 of the second bottom select transistor BSG2 in the first memory region 10 is greater than the fourth threshold voltage Vt4 of the second bottom select transistor BSG2 in the second memory region 20; and the first on-state voltage Vpass1 is greater than the third threshold voltage Vt3.

[0127] In some embodiments, the method of operating the memory device further includes: during a first pre-charge phase P1 and a first sensing phase P2, applying a second on-state voltage Vpass2 to a third bottom-select transistor BSG3 located between a first bottom-select transistor BSG1 and a second bottom-select transistor BSG2; the second on-state voltage Vpass2 being greater than a fifth threshold voltage of the third bottom-select transistor BSG3.

[0128] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative second turn-on voltage Vpass2, and the second bias voltage Vbias2 is less than the second turn-on voltage Vpass2.

[0129] In some embodiments, the method of operating the memory device further includes: during a first pre-charge phase P1 and a first sensing phase P2, applying a third turn-on voltage Vpass3 to a fourth bottom-select transistor BSG4 that is closer to the common source line CSL than the first bottom-select transistor BSG1 and the second bottom-select transistor BSG2; the third turn-on voltage Vpass3 is greater than the sixth threshold voltage Vt6 of the fourth bottom-select transistor BSG4.

[0130] In some specific examples, the first bias voltage Vbias1 is greater than or equal to the negative third turn-on voltage Vpass3, and the second bias voltage Vbias2 is less than the third turn-on voltage Vpass3.

[0131] In some embodiments, the method of operating the memory device further includes: in a first pre-charge phase P1, turning on top selection transistors TSG1 and TSG2 in the first finger memory region 10; in a first sensing phase P2, turning off the unselected top selection transistor TSG2 in the first finger memory region 10 and turning on the selected top selection transistor TSG1 in the first finger memory region 10; and in the first pre-charge phase P1 and the first sensing phase P2, turning off the top selection transistor TSG3 in the second finger memory region 20.

[0132] In some embodiments, in conjunction with reference Figure 7 and Figure 13The method of operating the memory device further includes: in a second pre-charge stage P6 for verifying the programming of memory cells in the second memory region 20, applying a fourth on-state voltage Vpass4 to the first bottom-select transistor BSG1 and applying a third bias voltage Vbias3 to the second bottom-select transistor BSG2; the fourth on-state voltage Vpass4 is greater than the second threshold voltage Vt2; in a second sensing stage P7 after the second pre-charge stage P6, applying the fourth on-state voltage Vpass4 to the first bottom-select transistor BSG1 and applying a fourth bias voltage Vbias4 to the second bottom-select transistor BSG2; the third bias voltage Vbias3 is less than the fourth bias voltage Vbias4; the fourth bias voltage Vbias4 is less than the third threshold voltage Vt3 and greater than the fourth threshold voltage Vt4.

[0133] In this embodiment, only one finger memory region can be selected for programming operations including programming verification operations to improve programming efficiency. Taking the programming verification operation of the memory cell in the first finger memory region 10 as an example, in the first pre-charge stage P1 of the programming verification operation, a lower first bias voltage Vbias1 can be applied to the first bottom selection transistor BSG1 to reduce the upward drift of the voltage on the first bottom selection transistor BSG1 caused by the coupling effect between the bottom selection lines. This stabilizes the actual voltage on the first bottom selection transistor BSG1 near the second bias voltage Vbias2, and the first bottom selection transistor BSG1 in the second finger memory region 20 remains in the off state. This reduces the drift of the threshold voltage of the memory cell in the second finger memory region 20 caused by the hot carrier injection effect, thereby improving the reliability of the memory device programming operation while improving the efficiency of the programming verification operation.

[0134] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0135] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0136] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, characterized in that, The memory device includes a memory array and peripheral circuitry coupled to the memory array; wherein, The storage array includes a first finger storage region and a second finger storage region; both the first finger storage region and the second finger storage region include multiple memory cell strings; each memory cell string includes a first bottom-select transistor; the first bottom-select transistor in the first finger storage region has a first threshold voltage, and the first bottom-select transistor in the second finger storage region has a second threshold voltage; the first threshold voltage is less than the second threshold voltage; the peripheral circuitry is configured as follows: During the first pre-charge phase of performing programming verification operations on the memory cells in the first memory region, a first bias voltage is applied to the first bottom selection transistor; In a first sensing phase following the first pre-charging phase, a second bias voltage is applied to the first bottom selection transistor; the first bias voltage is less than the second bias voltage; the second bias voltage is less than the second threshold voltage and greater than the first threshold voltage.

2. The memory device according to claim 1, characterized in that, Each of the memory cell strings further includes a second bottom select transistor, wherein the second bottom select transistor in the first finger memory region has a third threshold voltage, and the second bottom select transistor in the second finger memory region has a fourth threshold voltage; the third threshold voltage is greater than the fourth threshold voltage; The peripheral circuit is further configured to apply a first on-state voltage to the second bottom selection transistor during the first pre-charge phase and the first sensing phase; the first on-state voltage is greater than the third threshold voltage.

3. The memory device according to claim 2, characterized in that, Each of the memory cell strings further includes a third bottom select transistor; the third bottom select transistor is located between the first bottom select transistor and the second bottom select transistor; the third bottom select transistor has a fifth threshold voltage; The peripheral circuit is further configured to apply a second on-state voltage to the third bottom selection transistor during the first pre-charge phase and the first sensing phase; the second on-state voltage is greater than the fifth threshold voltage.

4. The memory device according to claim 3, characterized in that, The first bias voltage is greater than or equal to the negative second turn-on voltage, and the second bias voltage is less than the second turn-on voltage.

5. The memory device according to claim 2, characterized in that, The memory array further includes a common source line connected to each of the memory cell strings, and each of the memory cell strings further includes a fourth bottom select transistor, which is closer to the common source line than the first bottom select transistor and the second bottom select transistor; the fourth bottom select transistor has a sixth threshold voltage; The peripheral circuit is further configured to apply a third on-state voltage to the fourth bottom selection transistor during the first pre-charge phase and the first sensing phase; the third on-state voltage is greater than the sixth threshold voltage.

6. The memory device according to claim 5, characterized in that, The first bias voltage is greater than or equal to the negative third turn-on voltage, and the second bias voltage is less than the third turn-on voltage.

7. The memory device according to claim 2, characterized in that, The peripheral circuit is also configured to: In the second pre-charge phase of the programming verification operation of the memory cell in the second finger memory area, a fourth turn-on voltage is applied to the first bottom selection transistor and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage. In the second sensing phase following the second pre-charge phase, the fourth turn-on voltage is applied to the first bottom selection transistor, and the fourth bias voltage is applied to the second bottom selection transistor. The third bias voltage is less than the fourth bias voltage; the fourth bias voltage is less than the third threshold voltage but greater than the fourth threshold voltage.

8. The memory device according to claim 1, characterized in that, Each of the memory cell strings also includes a top selection transistor; the peripheral circuitry is further configured to: During the first pre-charge phase, the top selection transistor in the first finger storage area is turned on; During the first sensing phase, the unselected top selection transistors in the first finger memory area are turned off, and the selected top selection transistors in the first finger memory area are turned on. During the first pre-charge phase and the first sensing phase, the top selection transistor in the second finger memory area is turned off.

9. A memory system, characterized in that, include: At least one memory device as described in any one of claims 1 to 8; A controller is coupled to and configured to control the memory device.

10. A method of operating a memory device, characterized in that, include: In the first pre-charge phase of performing programming verification operations on the memory cells in the first memory region, a first bias voltage is applied to the first bottom selection transistor in each memory cell string; In the first sensing phase following the first pre-charge phase, a second bias voltage is applied to the first bottom selection transistor; The first bias voltage is less than the second bias voltage; The second bias voltage is less than the second threshold voltage of the first bottom select transistor in the second finger memory area and greater than the first threshold voltage of the first bottom select transistor in the first finger memory area.

11. The method of operating the memory device according to claim 10, characterized in that, The operation method further includes: During the first pre-charge phase and the first sensing phase, a first on-state voltage is applied to the second bottom select transistor in each of the memory cell strings; the third threshold voltage of the second bottom select transistor in the first finger memory region is greater than the fourth threshold voltage of the second bottom select transistor in the second finger memory region; the first on-state voltage is greater than the third threshold voltage.

12. The method of operating the memory device according to claim 11, characterized in that, The operation method further includes: During the first pre-charge phase and the first sensing phase, a second turn-on voltage is applied to a third bottom-select transistor located between the first bottom-select transistor and the second bottom-select transistor; the second turn-on voltage is greater than a fifth threshold voltage of the third bottom-select transistor.

13. The method of operating the memory device according to claim 12, characterized in that, The first bias voltage is greater than or equal to the negative second turn-on voltage, and the second bias voltage is less than the second turn-on voltage.

14. The method of operating the memory device according to claim 11, characterized in that, The operation method further includes: During the first pre-charge phase and the first sensing phase, a third turn-on voltage is applied to a fourth bottom-select transistor that is closer to the common source line than the first bottom-select transistor and the second bottom-select transistor; the third turn-on voltage is greater than the sixth threshold voltage of the fourth bottom-select transistor.

15. The method of operating the memory device according to claim 14, characterized in that, The first bias voltage is greater than or equal to the negative third turn-on voltage, and the second bias voltage is less than the third turn-on voltage.

16. The method of operating the memory device according to claim 11, characterized in that, The operation method further includes: In the second pre-charge phase of programming and verifying the memory cells in the second finger memory region, a fourth turn-on voltage is applied to the first bottom selection transistor, and a third bias voltage is applied to the second bottom selection transistor; the fourth turn-on voltage is greater than the second threshold voltage. In the second sensing phase following the second pre-charging phase, the fourth turn-on voltage is applied to the first bottom-select transistor, and the fourth bias voltage is applied to the second bottom-select transistor; the third bias voltage is less than the fourth bias voltage; the fourth bias voltage is less than the third threshold voltage and greater than the fourth threshold voltage.

17. The method of operating the memory device according to claim 10, characterized in that, The operation method further includes: During the first pre-charge phase, the top selection transistor in the first finger memory area is turned on; During the first sensing phase, the unselected top selection transistors in the first finger memory area are turned off, and the selected top selection transistors in the first finger memory area are turned on. During the first pre-charge phase and the first sensing phase, the top selection transistor in the second finger memory area is turned off.

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