Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a forming method thereof. A first plasma treatment process is first performed to form hydrogen-oxygen bonds on the sidewalls of an NMOS device, the sidewalls of a PMOS device and the surface of a shallow trench isolation structure. A second plasma treatment process is then performed, wherein the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds to generate characteristic reaction groups, and then a mask layer is formed. The characteristic reaction groups react with water in the mask layer to generate free hydroxide ions. In an exposure process, light passes through the mask layer and enters the shallow trench isolation structure for multiple reflections. When the photoacid generated in the mask layer at the bottom of a trench between adjacent NMOS devices and PMOS devices exceeds a preset value, the free hydroxide ions react with the excess photoacid generated by overexposure to make the photoacid in the mask layer meet the preset value. An unexpected effect is that the problem of side cutting in the mask layer is significantly improved, and the yield of the product is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the process of integrated circuit manufacturing, it is usually necessary to perform ion implantation on the corresponding source / drain (S / D) region. Before ion implantation, the implantation region needs to be defined using a yellow light process. The yellow light process includes performing an exposure process and a development process in the yellow light region. In the exposure process of the yellow light process, after light enters the shallow trench isolation (STI) structure of the device, multiple reflections will be performed, resulting in overexposure of the photoresist at the bottom of the trench between adjacent gates, and after subsequent development, the bottom 100 of the patterned photoresist will have an undercut problem, such as Figure 1 As shown, the blocking function of the photoresist layer in the subsequent ion implantation is affected, and the source region or drain region formed thereby exceeds the preset area, resulting in a reduction in product yield. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor structure and a method for forming the same, so as to solve the problem of side cutting at the bottom of the photoresist.

[0004] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0005] Providing a substrate, on which an NMOS device located in a P-well region and a PMOS device located in an N-well region are formed, a shallow trench isolation structure is formed between adjacent P-well regions and N-well regions, and the NMOS device and the PMOS device respectively include a gate and sidewalls located on both sides of the gate;

[0006] Performing a first plasma treatment process to form hydrogen-oxygen bonds on the sidewalls and on the surface of the shallow trench isolation structure;

[0007] Performing a second plasma treatment process, wherein the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds on the sidewall and the surface of the shallow trench isolation structure to generate characteristic reactive groups;

[0008] forming a mask layer, wherein the mask layer covers the sidewalls of the NMOS device and the PMOS device and fills the channel between the adjacent NMOS device and the PMOS device, and the characteristic reactive groups generate free hydroxide ions with water in the mask layer;

[0009] An exposure process is performed, light passes through the mask layer and enters the shallow trench isolation structure for multiple reflections, the photoacid generated in the mask layer at the bottom of the trench between the adjacent NMOS device and the PMOS device exceeds a preset value, and the free hydroxide ions react with the photoacid to neutralize the photoacid in the mask layer to meet the preset value.

[0010] Optionally, the sidewalls of the NMOS device include at least a silicon oxide layer and a silicon nitride layer, and the sidewalls of the PMOS device include at least a silicon oxide layer and a silicon nitride layer, and the shallow trench isolation structure includes a silicon oxide layer.

[0011] Optionally, the gas in the first plasma treatment process is N2O, and the N2O reacts with the silicon oxide layer and the silicon nitride layer to generate hydrogen-oxygen bonds.

[0012] Optionally, the gas in the second plasma treatment process is NH3, and the NH3 reacts with the hydrogen-oxygen bonds to generate water and the characteristic reactive groups.

[0013] Optionally, a flow rate of NH3 gas in the second plasma treatment process is 300 sccm to 1000 sccm.

[0014] Optionally, the characteristic reactive groups include at least Si2NH and Si3N.

[0015] Optionally, the process time in the second plasma treatment process is greater than or equal to 20 seconds.

[0016] Optionally, the power of the second plasma treatment process is 200 watts to 600 watts.

[0017] Optionally, a distance between the plasma source and the substrate in the second plasma treatment process is 200 mils to 1200 mils.

[0018] Based on the same inventive concept, the present invention further provides a semiconductor structure, which is prepared by any of the above-mentioned methods for forming a semiconductor structure.

[0019] In the method for forming a semiconductor structure provided by the present invention, a first plasma treatment process is first performed to form hydrogen-oxygen bonds on the side walls of an NMOS device, on the side walls of a PMOS device, and on the surface of a shallow trench isolation structure, and then a second plasma treatment process is performed, wherein the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds on the side walls of the NMOS device, on the side walls of the PMOS device, and on the surface of the shallow trench isolation structure to generate characteristic reactive groups, and then a mask layer is formed, wherein the characteristic reactive groups on the side walls of the NMOS device, on the side walls of the PMOS device, and on the surface of the shallow trench isolation structure react with water in the mask layer to generate free hydroxide ions, and in an exposure process, light passes through the mask layer and enters the shallow trench isolation structure for multiple reflections, and the photoacid generated in the mask layer at the bottom of a trench between adjacent NMOS devices and PMOS devices exceeds a preset value, and the free hydroxide ions react with the excess photoacid generated by overexposure to make the photoacid in the mask layer meet the preset value. The present invention has unexpected effects, can significantly improve the problem of mask layer side cutting, ensure the quality of the patterned mask layer formed after development, provide a blocking effect for the non-ion implantation area in the subsequent ion implantation process, so as to form a source and drain area in a preset area, which is beneficial to improving the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0021] Figure 1 It is a SEM image of the bottom side cut of the photoresist in the prior art.

[0022] Figure 2 It is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0023] Figure 3 It is a schematic diagram of the structure of the semiconductor structure after the sidewalls are formed according to an embodiment of the present invention.

[0024] Figure 4 It is a schematic diagram of a semiconductor structure after a first plasma treatment process is performed according to an embodiment of the present invention.

[0025] Figure 5 It is a schematic diagram of a semiconductor structure after a second plasma treatment process is performed according to an embodiment of the present invention.

[0026] Figure 6 It is a schematic diagram of a semiconductor structure when a mask layer is formed and an exposure process is performed according to an embodiment of the present invention.

[0027] Figure 7 It is an XPS analysis chart of an embodiment of the present invention.

[0028] Figure 8yes Figure 7 Enlarged view of N1S in the middle.

[0029] Fig. 9 is a SEM image of a semiconductor structure according to an embodiment of the present invention.

[0030] In the accompanying drawings: 100-photoresist side cut; 10-substrate; 11-shallow trench isolation structure; 12a-P well region; 12b-N well region; 13-pocket doping region; 14-lightly doped ion implantation region; 15-NMOS device; 15a-gate oxide layer; 15b-hafnium oxide layer; 15c-blocking layer; 15d-gate; 15e-first side wall; 15f-second side wall; 15g-third side wall; 16-PMOS device; 17-silicon germanium layer; 18-metal silicide layer; 19-mask layer; 19a-photoacid; 20-mask plate. DETAILED DESCRIPTION

[0031] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0032] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] Figure 2 FIG. 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 2 As shown, this embodiment provides a method for forming a semiconductor structure, comprising:

[0034] Step S10, providing a substrate, on which an NMOS device located in a P-well region and a PMOS device located in an N-well region are formed, a shallow trench isolation structure is formed between adjacent P-well regions and N-well regions, and the NMOS device and the PMOS device respectively include a gate and sidewalls located on both sides of the gate;

[0035] Step S20, performing a first plasma treatment process to form hydrogen-oxygen bonds on the sidewalls and on the surface of the shallow trench isolation structure;

[0036] Step S30, performing a second plasma treatment process, wherein the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds on the sidewall and the surface of the shallow trench isolation structure to generate characteristic reactive groups;

[0037] Step S40, forming a mask layer, wherein the mask layer covers the sidewalls of the NMOS device and the PMOS device and fills the channel between the adjacent NMOS device and the PMOS device, and the characteristic reactive groups generate free hydroxide ions with water in the mask layer;

[0038] Step S50, performing an exposure process, light passes through the mask layer and enters the shallow trench isolation structure for reflection, the photoacid generated in the mask layer at the bottom of the trench between the adjacent NMOS device and the PMOS device exceeds a preset value, and the free hydroxide ions react with the photoacid to neutralize the photoacid in the mask layer so that the photoacid meets the preset value.

[0039] Figure 3 It is a schematic diagram of the structure of the semiconductor structure after the sidewalls are formed according to an embodiment of the present invention. Figure 4 It is a schematic diagram of a semiconductor structure after a first plasma treatment process is performed according to an embodiment of the present invention. Figure 5 It is a schematic diagram of a semiconductor structure after a second plasma treatment process is performed according to an embodiment of the present invention. Figure 6 1 is a schematic diagram of a semiconductor structure when a mask layer is formed and an exposure process is performed according to an embodiment of the present invention. Figures 3 to 6 The specific embodiments of the present invention are described in detail.

[0040] like Figure 3As shown, a substrate 10 is provided. The substrate 10 may be a single crystal silicon or polycrystalline silicon substrate, or may be made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or may be a composite structure such as a silicon-on-insulator substrate. Those skilled in the art may select a suitable type of semiconductor substrate according to the requirements of the semiconductor device, and the type of the semiconductor substrate shall not limit the protection scope of the present invention.

[0041] Please continue to refer to Figure 3 The substrate 10 includes a deep N well region (DNW), a P well region 12a and an N well region 12b are formed in the deep N well region, and a shallow trench isolation structure 11 for isolating the P well region 12a and the N well region 12b. The material of the shallow trench isolation structure 11 is, for example, silicon oxide.

[0042] In this embodiment, pocket doping regions 13 and lightly doped ion implantation regions 14 are formed in both the P-well region 12a and the N-well region 12b, and source and drain electrodes are subsequently formed on the lightly doped ion implantation regions 14. The pocket doping regions 13 and the lightly doped ion implantation regions 14 are used to reduce the threshold voltage of the device.

[0043] An NMOS device 15 is formed on the P-well region 12a, and a PMOS device 16 is formed on the N-well region 12b. The NMOS device 15 includes a gate dielectric layer, a barrier layer 15c, a gate 15d and a sidewall stacked in sequence from bottom to top. The material of the gate dielectric layer includes one or a combination of an oxide layer and a hafnium oxide layer. In the present embodiment, the material of the gate dielectric layer includes a gate oxide layer 15a and a hafnium oxide layer 15b. The gate oxide layer 15a can be formed by a thermal oxidation process and the hafnium oxide layer 15b can be formed by an atomic layer deposition process. The material of the hafnium oxide layer 15b can effectively improve the gate leakage current due to its high dielectric constant. In order to prevent the metal ions (hafnium ions) in the hafnium oxide layer 15b from entering the gate 15d, in a preferred embodiment, a barrier layer 15c is formed on the hafnium oxide layer 15b, and the material of the barrier layer 15c is, for example, titanium nitride. The material of the gate 15d is, for example, polysilicon, and the gate 15d can be formed by a chemical vapor deposition process. The sidewalls at least include a silicon oxide layer and a silicon nitride layer. In this embodiment, a first sidewall 15e, a second sidewall 15f, and a third sidewall 15g are included. The material of the first sidewall 15e and the third sidewall 15g is, for example, silicon nitride, and the material of the second sidewall 15f is, for example, silicon oxide. The first sidewall 15e, the second sidewall 15f, and the third sidewall 15g can all be formed by a chemical vapor deposition process. The PMOS device 16 also includes a gate dielectric layer, a barrier layer, a gate, and sidewalls on both sides of the gate stacked in sequence from bottom to top. The materials and functions of the various layers of the PMOS device 16 are the same as those of the various layers of the NMOS device 15, and will not be repeated here.

[0044] Furthermore, a germanium silicon layer 17 and a metal silicide layer 18 on the germanium silicon layer 17 are formed in the N-well region 12b on both sides of the PMOS device 16. The germanium silicon layer 17 can be formed by an epitaxial growth process. The germanium silicon layer 17 has a compressive stress, so the germanium silicon layer 17 can improve the mobility of channel holes. The formation process of the metal silicide layer 18 on the germanium silicon layer 17 includes, for example, first forming a metal silicide blocking layer (Salicide Block, SAB), the metal silicide blocking layer covers the PMOS device 16 and the NMOS device 15 and exposes the germanium silicon layer 17, and then forming the metal silicide layer 18 on the exposed germanium silicon layer 17. After the metal silicide layer 18 is formed, the remaining metal silicide blocking layer can be removed.

[0045] like Figure 4 As shown, a first plasma treatment process is performed to form hydrogen-oxygen bonds on the sidewalls of the NMOS device 15 and the sidewalls of the PMOS device 16 and the surface of the shallow trench isolation structure 11. Specifically, the gas in the first plasma treatment process can be N2O, and the N2O plasma reacts with the silicon oxide layer and the silicon nitride layer in the sidewalls of the NMOS device 15 and the sidewalls of the PMOS device 16 and the silicon oxide on the surface of the shallow trench isolation structure to generate hydrogen-oxygen bonds. The hydrogen-oxygen bonds generated in this step are chemical bonds in a non-free state. In this embodiment, the power (Power) of the first plasma treatment process is, for example, 200 W to 600 W, the gas flow (flow) of N2O is, for example, 400 sccm to 1000 sccm, the spacing (Spacing) between the plasma source and the substrate 10 is, for example, 200 mils to 1200 mils, and the process time (Treat time) of the first plasma treatment process is, for example, 10 seconds to 30 seconds. The first plasma treatment process is helpful in solving the problem of white edges after photoresist development in the exposure process, that is, it can improve edge roughness. However, the hydrogen-oxygen bonds generated by the first plasma treatment process on the side wall surface of the NMOS device 15, the side wall surface of the PMOS device 16 and the surface of the shallow trench isolation structure are non-free chemical bonds, and it is difficult to solve the problem of photoresist undercut caused by multiple reflections of light entering the shallow trench isolation structure in the exposure process.

[0046] like Figure 5As shown, a second plasma treatment process is performed, and the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds on the sidewall surface of the NMOS device 15, the sidewall surface of the PMOS device 16, and the surface of the shallow trench isolation structure 11 to generate characteristic reactive groups. Specifically, the spacing (spacing) between the plasma source and the substrate 10 in the second plasma treatment process is, for example, 200 mils to 1200 mils. The process time in the second plasma treatment process is greater than or equal to 20 seconds. The power in the second plasma treatment process is, for example, 200 watts to 600 watts. The gas in the second plasma treatment process is NH3, and the NH3 gas flow rate is, for example, 300 sccm to 1000 sccm. The NH3 reacts with the hydrogen-oxygen bonds on the sidewall surface of the NMOS device 15, the sidewall surface of the PMOS device 16, and the surface of the shallow trench isolation structure to generate water and the characteristic reactive groups. The characteristic reactive groups include at least Si2NH and Si3N.

[0047] The reaction chemical formula is:

[0048]

[0049] like Figure 6 As shown, a mask layer 19 is formed, and the mask layer 19 covers the sidewalls of the NMOS device 15 and the sidewalls of the PMOS device 16, and fills the trench between the adjacent NMOS device 15 and the PMOS device 16, that is, the mask layer 19 covers the silicon oxide layer on the shallow trench isolation structure 11. The characteristic reactive groups on the sidewall surface of the NMOS device 15, the sidewall surface of the PMOS device 16 and the surface of the shallow trench isolation structure generate free hydroxide ions with water in the mask layer 19. Specifically, the material of the mask layer 19 is, for example, photoresist, and the characteristic reactive groups react with water (H2O) in the photoresist to generate free hydroxide ions (OH - ), the chemical reaction formula is as follows:

[0050]

[0051] Please continue to refer to Figure 6, performing an exposure process, light passes through the mask plate 20 to reach the mask layer 19 and enters the shallow trench isolation structure 11 for multiple reflections, and the photoacid 19a generated in the mask layer 19 at the bottom of the trench between the adjacent NMOS device 15 and the PMOS device 16 exceeds a preset value, and the preset value of the photoacid 19a is, for example, the amount of photoacid 19a generated when normal yellow light is incident on the mask layer 19 without multiple reflections. The free hydroxide ions generated by the characteristic reactive groups and the water in the mask layer 19 react with the excessive photoacid 19a to make the amount of the photoacid 19a at the bottom of the mask layer 19 meet the preset value, thereby improving the problem of side cutting at the bottom of the mask layer 19 after development, ensuring the quality of the patterned mask layer formed after development, providing a blocking effect for the non-ion implantation area in the subsequent ion implantation process, so as to form a source and drain area in the preset area, and improving the yield of the product.

[0052] This embodiment also provides a semiconductor structure, which is prepared by using any of the above-mentioned methods for forming a semiconductor structure.

[0053] Figure 7 It is an XPS analysis chart of an embodiment of the present invention. Figure 8 yes Figure 7 Enlarged view of N1S in the middle. Figure 7 and Figure 8 The horizontal axis is Binding energy, the unit is electron volt (eV); the vertical axis is intensity (relative photoelectron flux intensity or peak value), the unit is k·count / second (number of counts per second). Figure 7 The peak value of the N element can be seen in the figure. The peak value of the N element can be magnified to obtain Figure 8 After fitting, the components Si2NH and Si3N are obtained. It can be seen that the characteristic reaction groups formed on the sidewall surface of the NMOS device 15, the sidewall surface of the PMOS device 16 and the surface of the shallow trench isolation structure 11 include at least Si2NH and Si3N.

[0054] Fig. 9 is a SEM image of the semiconductor structure of an embodiment of the present invention. Fig. 9 As shown, there is no side cut at the bottom of the mask layer 19. Therefore, the method for forming a semiconductor structure provided in this embodiment can improve the problem of side cut at the bottom of the mask layer 19, ensure the quality of the patterned mask layer formed after development, provide a blocking effect for the non-ion implantation area in the subsequent ion implantation process, so as to form a source and drain area in a preset area, thereby improving the yield of the product.

[0055] In summary, in the method for forming a semiconductor structure provided by an embodiment of the present invention, a first plasma treatment process is first performed to form hydrogen-oxygen bonds on the sidewalls of the NMOS device, the sidewalls of the PMOS device, and the surface of the shallow trench isolation structure; then a second plasma treatment process is performed, and the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds on the sidewalls of the NMOS device, the sidewalls of the PMOS device, and the surface of the shallow trench isolation structure to generate characteristic reactive groups, and then a mask layer is formed, and the characteristic reactive groups on the sidewalls of the NMOS device, the sidewalls of the PMOS device, and the surface of the shallow trench isolation structure react with water in the mask layer to generate free hydroxide ions. In the exposure process, light passes through the mask layer and enters the shallow trench isolation structure for multiple reflections, and the photoacid generated in the mask layer at the bottom of the trench between the adjacent NMOS device and the PMOS device exceeds the preset value, and the free hydroxide ions react with the excess photoacid generated by overexposure to make the photoacid in the mask layer meet the preset value. The present invention has unexpected effects, can significantly improve the problem of mask layer side cutting, ensure the quality of the patterned mask layer formed after development, provide a blocking effect for the non-ion implantation area in the subsequent ion implantation process, so as to form a source and drain area in a preset area, which is beneficial to improving the yield of the product.

[0056] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which an NMOS device located in a P-well region and a PMOS device located in an N-well region are formed, a shallow trench isolation structure is formed between adjacent P-well regions and N-well regions, and the NMOS device and the PMOS device respectively include a gate and sidewalls located on both sides of the gate; Performing a first plasma treatment process to form hydrogen-oxygen bonds on the sidewalls and on the surface of the shallow trench isolation structure; Performing a second plasma treatment process, wherein the gas in the second plasma treatment process reacts with the hydrogen-oxygen bonds on the sidewall and the surface of the shallow trench isolation structure to generate characteristic reactive groups; forming a mask layer, wherein the mask layer covers the sidewalls of the NMOS device and the PMOS device and fills the channel between the adjacent NMOS device and the PMOS device, and the characteristic reactive groups generate free hydroxide ions with water in the mask layer; An exposure process is performed, light passes through the mask layer and enters the shallow trench isolation structure for reflection, the photoacid generated in the mask layer at the bottom of the trench between the adjacent NMOS device and the PMOS device exceeds a preset value, and the free hydroxide ions react with the photoacid to neutralize the photoacid in the mask layer so that the photoacid meets the preset value.

2. The method for forming a semiconductor structure according to claim 1, wherein: The sidewalls of the NMOS device at least include a silicon oxide layer and a silicon nitride layer, and the sidewalls of the PMOS device at least include a silicon oxide layer and a silicon nitride layer, and the shallow trench isolation structure includes a silicon oxide layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The gas in the first plasma treatment process is N2O, and the N2O reacts with the silicon oxide layer and the silicon nitride layer to generate hydrogen-oxygen bonds.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The gas in the second plasma treatment process is NH 3 , and the NH 3 reacts with the hydrogen-oxygen bonds to generate water and the characteristic reactive groups.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The flow rate of NH 3 gas in the second plasma treatment process is 300 sccm to 1000 sccm.

6. The method for forming a semiconductor structure according to claim 1 or 4, characterized in that: The characteristic reactive groups include at least Si2NH and Si3N.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process time of the second plasma treatment process is greater than or equal to 20 seconds.

8. The method for forming a semiconductor structure according to claim 1, wherein: The power of the second plasma treatment process is 200W to 600W.

9. The method for forming a semiconductor structure according to claim 1, wherein: The distance between the plasma source and the substrate in the second plasma treatment process is 200 mils to 1200 mils.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for forming a semiconductor structure according to any one of claims 1 to 9.

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