Packaging substrate and manufacturing method thereof, semiconductor chip and electronic device

Abstract

The present invention relates to the field of packaging technology, and in particular to a packaging substrate and a manufacturing method thereof, a semiconductor chip and an electronic device. The manufacturing method of the packaging substrate includes: providing a packaging substrate, the packaging substrate includes at least two conductive layers, the conductive layer includes a wiring layer and a ground layer, the wiring layer includes a signal line and a pad connected to the signal line; measuring the scattering parameters of the signal line, the scattering parameters are used to evaluate the signal integrity; when the scattering parameters do not meet the preset conditions, removing the preset area of ​​at least one ground layer closest to the pad connected to the signal line to increase the distance between the pad and the reference ground; wherein the vertical projection of the preset area on the packaging substrate covers the vertical projection of the pad connected to the signal line on the packaging substrate. The technical solution of the present invention helps to improve the signal integrity problem of the packaging substrate while saving manufacturing costs.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of packaging technology, and in particular to a packaging substrate and a manufacturing method thereof, a semiconductor chip and an electronic device. Background Art

[0002] With the rapid development and application of large chips such as central processing unit (CPU) and graphics processing unit (GPU), the packaging technology of large chips has also developed towards high-density packaging, high-reliability packaging and low cost. At the same time, the operating frequency of chips is getting higher and higher, and the operating voltage is getting lower and lower, which makes the packaging design more and more difficult, mainly reflected in signal integrity design, power integrity design, electromagnetic interference design, reliability design, etc.

[0003] Among them, the signal integrity (SI) of high-speed signals in chip packaging has become a huge challenge. When the signal operating frequency is low, the interconnection structure composed of bonding wires, pins, frames, solder balls, transmission lines, vias, pads, etc. can complete the performance evaluation of the entire channel by simply calculating its lumped parameters using simple tools. Nowadays, with the extensive application of high-speed interfaces such as SerDes, DDRx, and GDDRx in chip design, the packaging wiring of this part has the characteristics of high routing density and complex structure. Moreover, the operating frequency of these high-speed signals is as high as tens of GHz or even tens of GHz, and the signal transmission in the channel has shown electromagnetic wave characteristics, which has brought unprecedented challenges to packaging design engineers. How to use some effective methods in packaging design without increasing production costs to improve the signal integrity of high-speed signals has become a top priority. Summary of the invention

[0004] The present invention provides a packaging substrate and a manufacturing method thereof, a semiconductor chip and an electronic device, so as to improve the signal integrity problem of the packaging substrate and save the manufacturing cost at the same time.

[0005] In a first aspect, the present invention provides a method for manufacturing a packaging substrate, comprising:

[0006] Providing a packaging substrate, the packaging substrate comprising at least two conductive layers, the conductive layer comprising a wiring layer and a ground layer, the wiring layer comprising a signal line and a pad connected to the signal line;

[0007] measuring a scattering parameter of the signal line, wherein the scattering parameter is used to evaluate signal integrity;

[0008] When the scattering parameter does not meet the preset conditions, remove a preset area of ​​at least one layer of the ground layer closest to the pad connected to the signal line to increase the distance between the pad and the reference ground; wherein the vertical projection of the preset area on the packaging substrate covers the vertical projection of the pad connected to the signal line on the packaging substrate.

[0009] Optionally, the scattering parameter includes at least one of insertion loss and return loss.

[0010] Optionally, when the scattering parameter does not meet a preset condition, removing a preset area of ​​at least one layer of the ground layer closest to the pad connected to the signal line to increase the distance between the pad and the reference ground includes:

[0011] When the scattering parameter does not meet the preset condition, removing a preset area of ​​a target ground layer, wherein the target ground layer is a ground layer that has a vertical overlap area with the pad connected to the signal line and is closest to the pad;

[0012] measuring the scattering parameter of the signal line;

[0013] If the scattering parameter does not meet the preset condition, continue to remove the preset area of ​​the target ground layer, and measure the scattering parameter of the signal line until the scattering parameter meets the preset condition.

[0014] Optionally, the method for manufacturing the packaging substrate further includes:

[0015] If the scattering parameter meets the preset condition, a packaging substrate is manufactured by taking the current packaging substrate as a model.

[0016] Optionally, the pads include at least one of first-type pads, second-type pads and third-type pads, the first-type pads are used to electrically connect bumps, the second-type pads are used to electrically connect solder balls, and the third-type pads are used to connect vias.

[0017] Optionally, the area of ​​the preset region is larger than the area of ​​a vertical projection of the pad to which the signal line is connected on the packaging substrate.

[0018] Optionally, the vertical projection of the preset area on the packaging substrate is a first figure, the vertical projection of the pad connected to the signal line on the packaging substrate is a second figure, the first figure and the second figure are both circles, the centers of the first figure and the second figure coincide, and the diameter of the first figure is n times the diameter of the second figure, 1<n≤2.

[0019] In a second aspect, the present invention provides a packaging substrate, which is manufactured using the packaging substrate manufacturing method described in the first aspect.

[0020] In a third aspect, the present invention provides a semiconductor chip, comprising a chip body and the packaging substrate described in the second aspect, wherein the chip body and the packaging substrate are electrically connected via a bump.

[0021] In a fourth aspect, the present invention provides an electronic device, comprising a printed circuit board and the semiconductor chip described in the third aspect, wherein the printed circuit board and the semiconductor chip are electrically connected via solder balls.

[0022] The packaging substrate and its manufacturing method, semiconductor chip and electronic device provided by the present invention evaluate the signal integrity of the signal path where the signal line and the pad connected to it are located by measuring the scattering parameters of the signal line in the packaging substrate, so as to determine whether the pad connected to the signal line affects the impedance continuity of the signal path. When the scattering parameters of the signal line do not meet the preset conditions, the distance between the pad and the reference ground is increased by removing the preset area of ​​at least one grounding layer closest to the pad connected to the signal line, so as to compensate for the impedance change on the signal path caused by the pad, thereby improving the impedance continuity of the signal path and improving the signal integrity of the high-speed signal transmitted by the packaging substrate. In addition, the present solution does not require the addition of a wiring layer in the packaging substrate, nor does it require the replacement of the dielectric material of the packaging substrate, thereby improving the signal integrity of the high-speed signal without increasing the manufacturing cost.

[0023] It should be understood that the content described in this section is not intended to identify the key or important features of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a schematic flow chart of a method for manufacturing a packaging substrate provided by an embodiment of the present invention;

[0026] Figure 2 is a structural schematic diagram of a packaging substrate provided by an embodiment of the present invention;

[0027] Figure 3 yes Figure 2 A schematic diagram of a top view structure of a conductive layer in FIG.

[0028] Figure 4 yes Figure 2 A schematic diagram of a top view structure of another conductive layer in the embodiment;

[0029] Figure 5 is a flow chart of another method for manufacturing a packaging substrate provided by an embodiment of the present invention;

[0030] Figure 6 is a schematic structural diagram of a semiconductor chip provided by an embodiment of the present invention;

[0031] Figure 7 is a schematic structural diagram of another packaging substrate provided by an embodiment of the present invention;

[0032] Figure 8 is a flow chart of another method for manufacturing a packaging substrate provided by an embodiment of the present invention;

[0033] Fig. 9 yes Figure 7 A schematic diagram of a top view structure of the fourth conductive layer in FIG.

[0034] Fig.10 is a waveform diagram of an insertion loss provided by an embodiment of the present invention;

[0035] Fig.11 yes Figure 7 A schematic diagram of a top view of the structure of the fifth conductive layer;

[0036] Fig.12 yes Figure 7 A schematic diagram of a top view structure of the eighth conductive layer;

[0037] Fig.13 is a waveform diagram of another insertion loss provided by an embodiment of the present invention;

[0038] Fig.14 yes Figure 7 A schematic diagram of a top view structure of an eleventh conductive layer in FIG.

[0039] Fig.15 is a waveform diagram of another insertion loss provided by an embodiment of the present invention;

[0040] Fig.16 It is a waveform diagram of another insertion loss provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] As described in the background art, how to improve the signal integrity of high-speed signals has become a difficult problem in chip packaging design. The inventors have found that the reasons for the above problems are as follows:

[0044] There are two common methods used in the wiring processing of high-speed signals in existing packaging designs: one is to increase the wiring layer of the packaging substrate, reduce the density and length of high-speed signal wiring, and thus reduce the insertion loss of the signal; the other is to use high-frequency, low-loss dielectric materials to reduce the insertion loss of the signal. For the first solution, due to the particularity of the substrate design, in theory, one wiring layer can be added for every four layers of prepreg and copper layers, so this method will greatly increase the production cost of the substrate and increase the complexity of manufacturing. For the second solution, general high-frequency, low-loss materials are relatively expensive, and only a few suppliers can produce them. They are subject to others, which brings certain risks to the later mass production and shipment.

[0045] In view of this, an embodiment of the present invention provides a method for manufacturing a packaging substrate to improve the signal integrity problem of the packaging substrate and save manufacturing costs. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a packaging substrate provided by an embodiment of the present invention. Figure 1 , the method specifically comprises the following steps:

[0046] S110, providing a packaging substrate, the packaging substrate comprising at least two conductive layers, the conductive layer comprising a wiring layer and a ground layer, the wiring layer comprising signal lines and pads connecting the signal lines.

[0047] Specifically, the package substrate can provide electrical connection, protection and support for the semiconductor chip. The conductive layer in the package substrate can be a copper layer, the wiring layer is used to set the signal line, and the ground layer is used for grounding. The signal line in the wiring layer can be used to transmit high-speed signals, such as signals with a rate of ≥16GHz. The pad can electrically connect the signal lines in different conductive layers, or electrically connect the solder ball and the bump.

[0048] S120. Measure scattering parameters of the signal line, where the scattering parameters are used to evaluate signal integrity.

[0049] Among them, the scattering parameters are S parameters, which describe the frequency domain characteristics of the signal transmission channel and can be used to evaluate signal integrity.

[0050] Figure 2 is a structural schematic diagram of a packaging substrate provided by an embodiment of the present invention; Figure 3 yes Figure 2 A schematic diagram of the top view of a conductive layer in FIG. Figure 2 and Figure 3 Exemplarily, the package substrate includes a first conductive layer 101 to a sixth conductive layer 106 and a dielectric layer 20 disposed between adjacent conductive layers, wherein the first conductive layer 101, the third conductive layer 103 and the fifth conductive layer 105 may be ground layers, the second conductive layer 102 and the fourth conductive layer 104 may be wiring layers, and the sixth conductive layer 106 may be a power layer for accessing a power signal. Figure 3 The conductive layer shown is the second conductive layer 102 (i.e., the wiring layer) for illustration, and the conductive layer includes a signal line 11 and a pad 12 electrically connected to each other. By measuring the scattering parameters of the signal line 11, the integrity of the signal transmitted by the signal line 11 can be evaluated to determine whether the impedance of the signal path where the signal line 11 is located is continuous.

[0051] S130. When the scattering parameter does not meet a preset condition, remove a preset area of ​​at least one ground layer closest to the pad connected to the signal line to increase the distance between the pad and the reference ground.

[0052] The vertical projection of the preset area on the packaging substrate covers the vertical projection of the pad connected to the signal line on the packaging substrate.

[0053] In one embodiment, the preset condition includes that the absolute value of the difference between the scattering parameter and the preset standard value is less than or equal to the preset difference value, and the magnitude of the preset standard value and the preset difference value can be set according to the signal integrity requirements of the package substrate. If the absolute value of the difference between the scattering parameter of the signal line 11 measured in step S120 and the preset standard value is less than or equal to the preset difference value, it is determined that the scattering parameter of the signal line 11 meets the preset condition; conversely, if the absolute value of the difference between the scattering parameter of the signal line 11 and the preset standard value is greater than the preset difference value, it is determined that the scattering parameter does not meet the preset condition.

[0054] Figure 4 yes Figure 2 1 is a top view of another conductive layer in the embodiment of the present invention, the conductive layer may be the third conductive layer 103 (ie, the ground layer), wherein the dotted line indicates the corresponding position of the pad 12 in the third conductive layer 103. Figures 2 to 4 Exemplarily, the ground layer closest to the pad 12 connected to the signal line 11 is the third conductive layer 103. When the scattering parameter of the signal line 11 does not meet the preset conditions, the preset area 13 in the third conductive layer 103 can be removed, that is, the preset area 13 in the third conductive layer 103 is hollowed out, and along the direction Z perpendicular to the packaging substrate, the projection of the preset area 13 on the packaging substrate covers the projection of the pad 12 connected to the signal line 11 on the packaging substrate, that is, along the direction Z perpendicular to the packaging substrate, the preset area 13 overlaps with the position of the pad 12, and the position of the pad 12 is located within the preset area 13.

[0055] According to the theory of signal integrity, if the impedance of the signal path is completely matched, there will be no signal reflection, and there will be no signal integrity related problems. The impedance of the package substrate can be calculated as follows:

[0056] Z0=87 / SQRT(εr+1.41)×ln[(5.98h) / (0.8w+t)];

[0057] Wherein, Z0 represents the characteristic impedance of the conductor, εr represents the dielectric constant of the dielectric material, h represents the dielectric thickness between the conductor and the reference plane, w represents the width of the conductor, and t represents the thickness of the conductor. Since the width of the signal line 11 is smaller than the diameter of the pad 12, when the signal is transmitted between the signal line 11 and the pad 12, the impedance of the signal path will change, making the impedance of the signal path discontinuous. By removing the preset area 13 in the third conductive layer 103, the reference ground of the pad 12 is changed from the third conductive layer 103 to the fifth conductive layer 105, which is equivalent to increasing the distance between the pad 12 and the reference ground, which helps to compensate for the impedance change on the signal path caused by the pad 12, so as to improve the impedance continuity of the signal path, thereby improving the signal integrity of the packaging substrate.

[0058] It should be noted that the above embodiment only takes the case of removing the preset area 13 in the third conductive layer 103 as an example. In other embodiments, if the scattering parameter of the signal line 11 does not meet the preset conditions, more ground layers closest to the pad 12 connected to the signal line 11 can be removed, thereby further increasing the distance between the pad 12 and the reference ground. For example, the preset areas in the third conductive layer 103 and the fifth conductive layer 105 can be removed, so that the reference ground of the pad 12 is a farther ground plane, thereby further compensating for the impedance change on the signal path caused by the pad 12. This embodiment does not specifically limit the number of ground layers in the preset area to be removed.

[0059] The technical solution of the embodiment of the present invention measures the scattering parameters of the signal line in the packaging substrate to evaluate the signal integrity of the signal path where the signal line and the pad connected to it are located, so as to determine whether the pad connected to the signal line affects the impedance continuity of the signal path. When the scattering parameters of the signal line do not meet the preset conditions, the distance between the pad and the reference ground is increased by removing the preset area of ​​at least one ground layer closest to the pad connected to the signal line, so as to compensate for the impedance change on the signal path caused by the pad, thereby improving the impedance continuity of the signal path and improving the signal integrity of the high-speed signal transmitted by the packaging substrate. In addition, this solution does not require the addition of a wiring layer in the packaging substrate, nor does it require the replacement of the dielectric material of the packaging substrate, thereby improving the signal integrity of the high-speed signal without increasing the manufacturing cost.

[0060] Based on the above embodiments, this embodiment optimizes the method for manufacturing the packaging substrate. Figure 5 FIG. 1 is a flow chart of another method for manufacturing a packaging substrate provided by an embodiment of the present invention. Figure 5 , the method specifically comprises the following steps:

[0061] S210, providing a packaging substrate, the packaging substrate comprising a plurality of conductive layers, the conductive layers comprising a wiring layer and a ground layer, the wiring layer comprising signal lines and pads connecting the signal lines.

[0062] S220. Measure the scattering parameters of the signal line.

[0063] S230: Determine whether the scattering parameters meet a preset condition.

[0064] If the scattering parameter does not meet the preset condition, step S240 is executed; if the scattering parameter meets the preset condition, step S250 is executed.

[0065] Optionally, the scattering parameter includes at least one of insertion loss and return loss.

[0066] In one embodiment, the scattering parameter includes an insertion loss, and the insertion loss may be an S21 parameter measured by electronic design automation (EDA) software. If the absolute value of the difference between the insertion loss of the signal line and the preset standard insertion loss is less than or equal to the first preset difference, it is determined that the scattering parameter meets the preset condition; if the absolute value of the difference between the insertion loss of the signal line and the preset standard insertion loss is greater than the first preset difference, it is determined that the scattering parameter does not meet the preset condition. The size of the preset standard insertion loss and the first preset difference can be set according to the signal integrity requirements of the package substrate.

[0067] In another embodiment, the scattering parameter includes a return loss, and the return loss may be an S11 parameter measured by EDA software. If the absolute value of the difference between the return loss of the signal line and the preset standard return loss is less than or equal to the second preset difference, it is determined that the scattering parameter meets the preset condition; if the absolute value of the difference between the return loss of the signal line and the preset standard return loss is greater than the second preset difference, it is determined that the scattering parameter does not meet the preset condition. The size of the preset standard return loss and the second preset difference may be set according to the signal integrity requirements of the package substrate.

[0068] In other embodiments, the scattering parameters include both insertion loss and return loss. If both the insertion loss and the return loss satisfy corresponding preset conditions, it is determined that the scattering parameters satisfy the preset conditions. If either the insertion loss or the return loss does not satisfy the corresponding preset conditions, it is determined that the scattering parameters do not satisfy the preset conditions.

[0069] S240, removing a preset area of ​​a target ground layer, where the target ground layer is a ground layer that has a vertical overlap area with the pad connected to the signal line and is closest to the pad.

[0070] Combination Figures 2 to 4 , exemplarily, when the signal line 11 and the pad 12 connected thereto are located in the second conductive layer 102 (wiring layer), the pad 12 currently connected to the signal line 11 has a vertical overlapping area and the nearest grounding layer to the pad 12 is the third conductive layer 103, i.e., the target grounding layer. The preset area 13 of the third conductive layer 103 is removed, so that the reference ground of the pad 12 is changed from the third conductive layer 103 to the fifth conductive layer 105, so as to increase the distance between the pad 12 and the reference ground, thereby compensating for the impedance change on the signal path caused by the pad 12, so as to improve the impedance continuity of the signal path, thereby improving the signal integrity of the package substrate.

[0071] After removing the preset area 13 of the third conductive layer 103, return to execute steps S220 to S230, measure the current scattering parameters of the signal line 11, and determine whether the scattering parameters meet the preset conditions. If the scattering parameters still do not meet the preset conditions, execute step S240 to continue to remove the preset area of ​​the target ground layer. Since the preset area 13 of the third conductive layer 103 has been removed, and the vertical projection of the preset area 13 on the package substrate covers the vertical projection of the pad 12 on the package substrate, the third conductive layer 103 has no vertical overlap area with the pad 12. The pad 12 currently connected to the signal line 11 has a vertical overlap area and the nearest ground layer to the pad 12 is the fifth conductive layer 105, that is, the current target ground layer is the fifth conductive layer 105. The preset area 13 of the fifth conductive layer 105 is removed, so that the reference ground of the pad 12 is changed from the fifth conductive layer 105 to a farther ground plane, so as to increase the distance between the pad 12 and the reference ground, thereby further compensating for the impedance change on the signal path caused by the pad 12, so as to further improve the impedance continuity of the signal path, thereby improving the signal integrity of the packaging substrate.

[0072] After removing the preset area of ​​the fifth conductive layer 105, if the preset area of ​​the ground layer adjacent to all the pads 12 connected to the signal line 11 in the packaging substrate has been removed, step S250 is executed; if there is still a target ground layer in the packaging substrate that has a vertical overlapping area with the pads 12 connected to the signal line 11 and is closest to the pads 12, the process returns to execute steps S220 to S230, measures the current scattering parameters of the signal line 11, and determines whether the scattering parameters meet the preset conditions; if the scattering parameters still do not meet the preset conditions, step S240 is executed to continue removing the preset area of ​​the target ground layer until the scattering parameters meet the preset conditions, or the preset area of ​​the ground layer adjacent to all the pads 12 connected to the signal line 11 in the packaging substrate is removed.

[0073] S250 , manufacturing a packaging substrate using the current packaging substrate as a model.

[0074] Optionally, steps S210 to S240 may all be performed during the design phase of the packaging substrate, and step S250 may be performed during the actual production phase of the packaging substrate.

[0075] In the design stage of the packaging substrate, by removing the preset areas of each target ground layer so that the scattering parameters of the signal line meet the preset conditions, the current packaging substrate can be used as a model. In the subsequent actual production process of the packaging substrate, the preset areas of each target ground layer in the packaging substrate are removed so that the structure of the packaging substrate is consistent with the structure of the above model, thereby compensating for the impedance changes on the signal path caused by the pad, so as to enhance the impedance continuity of the signal path and improve the signal integrity of the high-speed signal transmitted by the packaging substrate.

[0076] In addition, when the overall thickness of the package substrate is determined, a thinner dielectric layer can also be used. For example, the thickness of the dielectric layer can range from 10 μm to 100 μm, thereby leaving more space for the wiring layer and further improving the impedance continuity of the high-speed signal path. The technical solution of the embodiment of the present invention can improve the signal integrity of the high-speed signal transmitted by the package substrate when the thickness of the dielectric layer is thin, and this solution does not require additional wiring layers in the package substrate, nor does it require replacement of the dielectric material of the package substrate, which helps to save production costs.

[0077] Combination Figures 2 to 4 On the basis of the above embodiments, optionally, the area of ​​the preset area 13 is larger than the area of ​​the vertical projection of the pad 12 connected to the signal line 11 on the packaging substrate, and the vertical projection of the preset area 13 on the packaging substrate covers the vertical projection of the pad 12 connected to the signal line 11 on the packaging substrate, so that the pad 12 connected to the signal line 11 has no vertical overlapping area with the corresponding ground layer, so as to ensure that the pad 12 can use the farther ground layer as a reference ground.

[0078] In one embodiment, the vertical projection of the preset area 13 on the package substrate is a first figure, and the vertical projection of the pad 12 connected to the signal line 11 on the package substrate is a second figure, the first figure and the second figure are both circular, the centers of the first figure and the second figure coincide, and the diameter of the first figure is n times the diameter of the second figure, 1<n≤2. Optionally, n=1.1.

[0079] In other embodiments, the first figure and the second figure can be any figures, ensuring that the area of ​​the first figure is larger than the area of ​​the second figure, and the vertical projection of the preset area 13 on the packaging substrate covers the vertical projection of the pad 12 connected to the signal line 11 on the packaging substrate.

[0080] Figure 6 is a schematic structural diagram of a semiconductor chip provided by an embodiment of the present invention; Figure 7 Schematic diagram of another packaging substrate provided by an embodiment of the present invention. Figure 6 and Figure 7 , taking a specific packaging substrate structure as an example, the technical solution of the present invention is further explained.

[0081] Optionally, the pads 12 in the package substrate include at least one of first, second and third type pads, the first type pads are used to electrically connect the bumps 200 , the second type pads are used to electrically connect the solder balls 400 , and the third type pads are used to connect vias.

[0082] Exemplarily, one side surface of the packaging substrate 100 is electrically connected to the chip body 300 (i.e., the silicon wafer) through the bump 200, and the other side surface of the packaging substrate 100 is electrically connected to the printed circuit board 500 through the solder ball 400. The signal output by the chip body 300 is transmitted to the wiring layer in the packaging substrate 100 through the bump 200, and is transmitted to the printed circuit board 500 through the solder ball 400. Figure 7 A 12-layer package substrate stack structure is shown, specifically including a first conductive layer 101 to a twelfth conductive layer 1012. The first conductive layer 101 is used to set a first type of pad, so that the package substrate 100 and the chip body 300 are electrically connected through the first type of pad and the bump 200. The twelfth conductive layer 1012 is used to set a second type of pad, so that the package substrate 100 and the printed circuit board 500 are electrically connected through the second type of pad and the solder ball 400. In one embodiment, in order to utilize the package substrate 100 to transmit high-speed signals with a transmission rate greater than or equal to 16Gbs, the first conductive layer 101, the third conductive layer 103 and the fifth conductive layer 105 are set as ground layers, the second conductive layer 102 and the fourth conductive layer 104 are wiring layers, the sixth conductive layer 106 is a power layer, and the seventh conductive layer 107 to the twelfth conductive layer 1012 are alternately arranged ground layers and power layers, for example, the seventh conductive layer 107, the ninth conductive layer 109, and the eleventh conductive layer 1011 are power layers, and the eighth conductive layer 108, the tenth conductive layer 1010 and the twelfth conductive layer 1012 are ground layers. A plurality of vias are provided in the package substrate, for example, the first via 31 and the second via 32 are both layer-changing vias, specifically blind buried vias (BBvia), and the third via 33 is a core board via, specifically a through hole (PTH). The pads 12 connected to the first via 31, the second via 32 and the third via 33 are all third-type pads.

[0083] Since the diameter of each pad in the packaging substrate is larger than the diameter of the via and the width of the signal line, the impedance of the signal path will change when the signal is transmitted between the signal line and the pad 12 connected to it, causing discontinuity in the impedance of the signal path. Therefore, when the scattering parameters of any signal line do not meet the preset conditions, a preset area of ​​at least one ground layer closest to the pad 12 connected to the signal line can be removed to increase the distance between the pad 12 and the reference ground, wherein the pad 12 can be a first-type pad, a second-type pad or a third-type pad.

[0084] Optionally, when the scattering parameters of the signal line do not meet the preset conditions, the preset area of ​​at least one ground layer closest to the first type of pad and / or the second type of pad connected to the signal line is preferentially removed. The reason for this setting is that, compared with the third type of pad, the first type of pad and the second type of pad are larger in size and have a greater impact on the impedance of the signal channel. Removing the preset area of ​​the ground layer adjacent to the first type of pad or the second type of pad has a greater effect on improving the impedance continuity of the signal path. If the preset areas of the ground layer adjacent to the first type of pad and the second type of pad connected to the signal line are removed, and the scattering parameters of the signal line still do not meet the preset conditions, the preset area of ​​at least one ground layer closest to the third type of pad connected to the signal line will continue to be removed, thereby further improving the impedance continuity of the signal path.

[0085] Figure 8 FIG. 1 is a flow chart of another method for manufacturing a packaging substrate provided by an embodiment of the present invention. Figure 8 , the method specifically comprises the following steps:

[0086] S310, performing stacking and wiring design of the packaging substrate.

[0087] S320, performing signal path impedance detection on the signal lines in the wiring layer.

[0088] By performing signal path impedance detection on the signal line in the wiring layer, it is possible to determine whether there is a problem with the impedance of the signal line itself, so as to eliminate the influence of the signal line's own factors on the scattering parameters.

[0089] S330, measuring the scattering parameters of the signal line, and determining whether the scattering parameters meet a preset condition.

[0090] Exemplarily, in this embodiment, the S21 parameter, that is, the insertion loss, is used as the scattering parameter. The S21 parameter of the signal line is measured using EDA impedance evaluation software to determine whether the scattering parameter meets the preset conditions.

[0091] If the scattering parameter meets the preset condition, step S390 is executed; if the scattering parameter does not meet the preset condition, step S340 is executed.

[0092] S340, removing a preset area in a ground layer that is closest to the pad connected to the signal line.

[0093] Specifically, the preset areas in a ground layer adjacent to various types of pads connected to the signal lines can be removed, for example, the preset areas in a ground layer closest to the pads of the blind buried vias connected to the signal lines, the preset areas in a ground layer closest to the pads of the through holes connected to the signal lines, the preset areas in a ground layer closest to the pads of the bumps connected to the signal lines, and the preset areas in a ground layer closest to the pads of the solder balls connected to the signal lines.

[0094] S350, measuring the scattering parameters of the signal line, and determining whether the scattering parameters meet a preset condition.

[0095] If the scattering parameter meets the preset condition, step S390 is executed; if the scattering parameter does not meet the preset condition, step S360 is executed.

[0096] S360, continue to remove the preset areas in the two ground layers closest to the pads connected to the signal lines.

[0097] Specifically, the preset areas in the other two ground layers adjacent to the pads with relatively larger areas can continue to be removed. For example, the preset areas in the two ground layers closest to the pads of the through holes currently connected to the signal lines can be removed, and the preset areas in the two ground layers closest to the pads of the solder balls currently connected to the signal lines can be removed.

[0098] S370, measuring the scattering parameters of the signal line, and determining whether the scattering parameters meet a preset condition.

[0099] If the scattering parameter meets the preset condition, step S390 is executed; if the scattering parameter does not meet the preset condition, step S380 is executed.

[0100] S380. Test other factors that affect the impedance continuity of the signal channel.

[0101] In this embodiment, the number of ground layers removed from the preset area is set to be at most 3 layers. If the scattering parameter still does not meet the preset condition, it is further evaluated whether other factors affect the impedance continuity of the signal channel.

[0102] S390, manufacturing a packaging substrate using the current packaging substrate as a model.

[0103] The technical solution of the embodiment of the present invention can improve the signal integrity of high-speed signals transmitted by the package substrate when the thickness of the dielectric layer is relatively thin, without adding an additional wiring layer in the package substrate, and without replacing the dielectric material of the package substrate, which helps to save manufacturing costs. In addition, this solution uses S parameter simulation to evaluate the characteristics of the signal path, which does not rely on the driving model of the high-speed signal or the model of the receiving end. It has a good reference significance in the early stage of the substrate design finalization, and the signal quality improvement based on EDA simulation can be done quickly and efficiently.

[0104] The following still takes the packaging substrate adopting a 12-layer stacked structure design as an example to further illustrate the manufacturing method of the packaging substrate. Fig. 9 yes Figure 7 A schematic diagram of a top view of the fourth conductive layer in FIG. Figure 7 and Fig. 9 After completing the stacking and wiring design of the packaging substrate, the signal path impedance of the signal lines in each wiring layer is detected. For example, for the first differential signal line 11a and the second differential signal line 11b in the fourth conductive layer 104, the differential impedance of the two is first checked to determine whether there is a problem with the impedance of the signal line itself, so as to eliminate the influence of the signal line's own factors on the scattering parameters.

[0105] After completing the signal path impedance detection, the EDA impedance evaluation software is used to simulate the first differential signal line 11a and the second differential signal line 11b to obtain the differential transmission insertion loss of the pair of differential signal lines. Since the EDA impedance evaluation software cannot model and analyze the vias, the impedance continuity of the signal path is determined by measuring the differential transmission insertion loss of the differential signal lines. Fig.10 is a waveform diagram of an insertion loss provided by an embodiment of the present invention, wherein the horizontal axis represents the bandwidth in GHz, and the vertical axis represents the insertion loss in dB. Fig.10 It can be seen that, without improving the structure of the packaging substrate, within the bandwidth range of 8 GHz, the S21 parameter value of the first differential signal line 11 a and the second differential signal line 11 b is less than or equal to −1.92 dB.

[0106] Fig.11 yes Figure 7 A schematic diagram of a top view of the fifth conductive layer in FIG. Figure 7 , Fig. 9 and Fig.11The two ends of the first differential signal line 11a and the second differential signal line 11b are respectively connected to the corresponding pads 12. By removing the first preset area 13a and the second preset area 13b in the fifth conductive layer 105 corresponding to the positions of the pads 12 of the fourth conductive layer 104, the pads 12 in the fourth conductive layer 104 can refer to a farther ground layer. Fig.12 yes Figure 7 A schematic diagram of a top view of the eighth conductive layer in FIG. Figure 7 , Fig. 9 , Fig.11 and Fig.12 By removing the preset area 13 of the eighth conductive layer 108 corresponding to the position of the pad 12 connected to the first differential signal line 11a and the second differential signal line 11b, the corresponding pad 12 can refer to a farther ground layer.

[0107] Fig.11 and Fig.12 , various pads are shown, including the bump pad 12 and the through-hole pad 12 connected to the first differential signal line 11a and the second differential signal line 11b. After the preset areas of the ground layer adjacent to the bump pad 12 and the through-hole pad 12 are removed, the first differential signal line 11a and the second differential signal line 11b are simulated and tested again to obtain the differential transmission insertion loss. Fig.13 1 is another waveform diagram of insertion loss provided by an embodiment of the present invention, wherein the parameters and units represented by the horizontal and vertical axes are the same as those in FIG. Fig.10 The same below. Fig.13 It can be seen that after removing the preset area of ​​the ground layer adjacent to the bump pad 12 and the through hole pad 12, within the bandwidth range of 8 GHz, the S21 parameter value of the first differential signal line 11a and the second differential signal line 11b is less than or equal to -1.19 dB, so that the signal integrity is improved.

[0108] Fig.14 yes Figure 7 A schematic diagram of a top view of the eleventh conductive layer in FIG. Figure 7 , Fig. 9 and Fig.14 The first differential signal line 11a and the second differential signal line 11b are also electrically connected to the pad 12 of the solder ball. By removing the preset area 13 in the eleventh conductive layer 1011, the pad 12 of the solder ball can reference a farther ground layer. Fig.15 is another waveform diagram of insertion loss provided by an embodiment of the present invention, wherein Fig.15 It can be seen that after removing the preset area of ​​the ground layer adjacent to the pad 12 of the solder ball, the S21 parameter of the first differential signal line 11 a and the second differential signal line 11 b has been increased to −0.86 dB, so that the signal integrity is improved.

[0109] Finally, the preset areas in a ground layer adjacent to the blind buried via pads 12 and the bump pads 12 connected to the first differential signal line 11a and the second differential signal line 11b are removed respectively, and the preset areas in two ground layers adjacent to the relatively large pads 12 (including the through-hole pads 12 and the solder ball pads 12) connected to the first differential signal line 11a and the second differential signal line 11b are removed respectively, and then the first differential signal line 11a and the second differential signal line 11b are simulated and tested again to obtain the differential transmission insertion loss. Fig.16 is another waveform diagram of insertion loss provided by an embodiment of the present invention, wherein Fig.16 It can be seen that after the preset areas in the above-mentioned ground layers are removed, the S21 parameter of the first differential signal line 11a and the second differential signal line 11b has been increased to -0.75dB, which is nearly 1.2dB higher than the S21 parameter in the initial state.

[0110] The technical solution of the embodiment of the present invention adopts S parameter simulation to determine the wiring method of the signal line, which can work in parallel with the back end, which helps to save the time cost of chip design. By removing the preset area in the ground layer adjacent to the pad of the bump and the pad of the blind buried via, it helps to improve the via impedance of the pad of the bump and the blind buried via. By removing the preset area in the multi-layer ground layer adjacent to the pad of the through hole with a relatively large area and the pad of the solder ball, the present solution can control the impedance range of the signal path and reduce the points of impedance discontinuity in the signal path when using a thinner dielectric layer, thereby improving the signal integrity of the high-speed signal.

[0111] Based on the same inventive concept, an embodiment of the present invention further provides a packaging substrate, which can be manufactured using the manufacturing method of the packaging substrate in any of the above embodiments.

[0112] The technical solution of the embodiment of the present invention measures the scattering parameters of the signal line in the packaging substrate to evaluate the signal integrity of the signal path where the signal line and the pad connected to it are located, so as to determine whether the pad connected to the signal line affects the impedance continuity of the signal path. When the scattering parameters of the signal line do not meet the preset conditions, the distance between the pad and the reference ground is increased by removing the preset area of ​​at least one ground layer closest to the pad connected to the signal line, so as to compensate for the impedance change on the signal path caused by the pad, thereby improving the impedance continuity of the signal path and improving the signal integrity of the high-speed signal transmitted by the packaging substrate. In addition, this solution does not require the addition of a wiring layer in the packaging substrate, nor does it require the replacement of the dielectric material of the packaging substrate, thereby improving the signal integrity of the high-speed signal without increasing the manufacturing cost.

[0113] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor chip. Figure 6 The semiconductor chip includes a chip body 300 and a package substrate 100 in the above embodiment (i.e., a package substrate manufactured by the method for manufacturing a package substrate in any of the above embodiments), and the chip body 300 and the package substrate 100 are electrically connected via a bump 200. The semiconductor chip provided by the embodiment of the present invention includes the package substrate in the above embodiment, and thus has a corresponding structure and beneficial effects of the package substrate, which will not be described in detail here.

[0114] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, see Figure 6 The electronic device includes a printed circuit board 500 and the semiconductor chip in the above embodiment, and the printed circuit board 500 and the semiconductor chip are electrically connected through the solder ball 400. The electronic device provided by the embodiment of the present invention includes the semiconductor chip in the above embodiment, and thus has the corresponding structure and beneficial effects of the semiconductor chip, which will not be described in detail.

[0115] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0116] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a packaging substrate, characterized in that: include: Providing a packaging substrate, the packaging substrate comprising at least two conductive layers, the conductive layer comprising a wiring layer and a ground layer, the wiring layer comprising a signal line and a pad connected to the signal line; measuring a scattering parameter of the signal line, wherein the scattering parameter is used to evaluate signal integrity; When the scattering parameter does not meet the preset conditions, remove a preset area of ​​at least one layer of the ground layer closest to the pad connected to the signal line to increase the distance between the pad and the reference ground; wherein the vertical projection of the preset area on the packaging substrate covers the vertical projection of the pad connected to the signal line on the packaging substrate.

2. The method for manufacturing a packaging substrate according to claim 1, characterized in that: The scattering parameter includes at least one of insertion loss and return loss.

3. The method for manufacturing a packaging substrate according to claim 1, characterized in that: When the scattering parameter does not meet the preset condition, removing a preset area of ​​at least one ground layer closest to the pad connected to the signal line to increase the distance between the pad and the reference ground, including: When the scattering parameter does not meet the preset condition, removing a preset area of ​​a target ground layer, wherein the target ground layer is a ground layer that has a vertical overlap area with the pad connected to the signal line and is closest to the pad; measuring the scattering parameter of the signal line; If the scattering parameter does not meet the preset condition, continue to remove the preset area of ​​the target ground layer, and measure the scattering parameter of the signal line until the scattering parameter meets the preset condition.

4. The method for manufacturing a packaging substrate according to claim 3, characterized in that: The method for manufacturing the packaging substrate further includes: If the scattering parameter meets the preset condition, a packaging substrate is manufactured by taking the current packaging substrate as a model.

5. The method for manufacturing a packaging substrate according to claim 1, characterized in that: The pads include at least one of first-type pads, second-type pads and third-type pads, the first-type pads are used to electrically connect to bumps, the second-type pads are used to electrically connect to solder balls, and the third-type pads are used to connect to vias.

6. The method for manufacturing a packaging substrate according to any one of claims 1 to 5, characterized in that: The area of ​​the preset region is larger than the area of ​​a vertical projection of the pad connected to the signal line on the packaging substrate.

7. The method for manufacturing a packaging substrate according to claim 6, characterized in that: The vertical projection of the preset area on the packaging substrate is a first figure, and the vertical projection of the pad connected to the signal line on the packaging substrate is a second figure. The first figure and the second figure are both circles, the centers of the first figure and the second figure coincide, and the diameter of the first figure is n times the diameter of the second figure, 1<n≤2.

8. A packaging substrate, characterized in that: The packaging substrate is manufactured by the manufacturing method of any one of claims 1 to 7.

9. A semiconductor chip, characterized in that: The invention comprises a chip body and the packaging substrate as claimed in claim 8, wherein the chip body and the packaging substrate are electrically connected via bumps.

10. An electronic device, characterized in that: The invention comprises a printed circuit board and the semiconductor chip according to claim 9, wherein the printed circuit board and the semiconductor chip are electrically connected via solder balls.

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