Power module and manufacturing method thereof

Abstract

The invention discloses a power module and a manufacturing method thereof, and relates to the technical field of power modules. The method comprises the following steps: S1, bonding a drain electrode of a power chip to the surface of a substrate through an adhesive; s2, enabling a first mold to be in contact with the surface of the power chip; forming a packaging power module cavity between the first mold and the power chip; then filling a plastic packaging material into the packaging power module cavity to complete a plastic packaging process; s3, the first mold is removed; s4, covering a second mold between the source electrode and the gate electrode on the surface of the power chip, and performing double-sided seed layer sputtering to obtain a seed layer; and S5, the second mold is removed, the power chip with the seed layer is immersed in electroplating liquid for deposition, an electroplating metal layer is formed on the surface of the seed layer of the power chip, and the power module is obtained. According to the method, laser drilling can be avoided, damage caused by laser drilling to an electrode on the surface of the chip is avoided, and the steps of cleaning, activating and the like are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power modules, and in particular to a power module and a manufacturing method thereof. Background Art

[0002] The power chip is the core part of the power module. The power chip is combined with certain functions through solder printing, chip mounting, welding, wire bonding, housing installation, sealing and curing to become a power module that can realize power conversion. When the IGBT module is in normal operation, the chip will generate power loss, which will increase the operating temperature of the IGBT module. During the opening and closing process, due to the large stray inductance parameters of the traditional packaging method, it will generate greater voltage overshoot and oscillation under extremely high di / dt. Due to the mismatch of thermal expansion coefficients between layers inside the module, the material expands and shrinks in different volumes, causing shear stress and bending deformation, which will eventually lead to thermal fatigue failure of the IGBT module.

[0003] Common forms of thermal fatigue failure of IGBT modules include wire bonding failure and solder layer fatigue. Wire bonding failure is mainly caused by the peeling and falling off of the bonding wire and the power chip at the aluminum-silicon interface. When one of the wires falls off, it will accelerate the failure process of the remaining bonding wires. Solder layer fatigue failure refers to the physical layer interface of the chip solder layer and the substrate solder layer under the repeated alternating thermal stress, which causes cracks and voids. Solder layer fatigue will lead to an increase in the thermal resistance of the IGBT module, thereby further increasing the operating junction temperature of the device, accelerating the failure of the power module, and affecting the reliability of the module.

[0004] In order to improve the reliability of IGBT power modules, researchers have mainly conducted research on new packaging processes from the aspects of improving the heat dissipation efficiency of modules and reducing the stray inductance and thermal resistance of packages. They have mainly studied several packaging methods such as press-fitting, three-dimensional interconnection, and chip-embedded packaging. Press-fitting has high requirements for the uniformity and precision control of applied pressure, and there is potential mechanical stress damage, so it is only used in special scenarios. In order to reduce parasitic inductance, researchers have developed a three-dimensional interconnection packaging method, which places the power chip face to face with the chip, realizes electrical interconnection through two DBC substrates and a four-layer PCB, and integrates the current path and capacitor on the PCB board, which greatly reduces the parasitic parameters, but has a complex preparation process and high production cost. Chip-embedded packaging is to embed the power chip on a ceramic substrate or PCB board, and realize the electrical interconnection between the chip and the outer package through laser drilling and metallized micropores. This packaging method can improve the integration of the power module and reduce the parasitic inductance of the module, but it has preparation processes such as laser opening and multi-step photolithography development, which reduces production efficiency and increases production costs. Therefore, it is necessary to propose a new packaging structure to improve the heat dissipation performance of the power module while improving production efficiency and reducing costs. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a power module and a method for manufacturing the same. The power module manufacturing method proposed in the present invention is based on a mold as a masking layer, which can achieve laser-free drilling, thereby avoiding damage to the chip surface electrode caused by laser drilling, and reducing the steps of cleaning and activation. To achieve the above purpose, the technical solution adopted by the present invention is:

[0006] In a first aspect, the present invention provides a method for manufacturing a power module, comprising the following steps:

[0007] S1: bonding the drain electrode of the power chip to the surface of the substrate through an adhesive;

[0008] S2: The first mold is embedded with the substrate and in contact with the surface of the power chip, so as to form a packaged power module cavity between the first mold and the power chip; then, a plastic encapsulation material is filled into the packaged power module cavity, and the plastic encapsulation material is cured and demolded; the first mold is designed according to the structure of the power chip and the substrate and is provided with a positioning hole and a bracket for embedding with the substrate;

[0009] S3: removing the first mold;

[0010] S4: Covering the second mold between the source electrode and the gate electrode on the surface of the power chip to form a masking layer for the sputtering seed layer, and then placing the power chip and the second mold together in a vacuum chamber of a sputtering device to perform double-sided seed layer sputtering;

[0011] S5: removing the second mold, and then immersing the power chip with the seed layer into an electroplating solution containing metal ions for deposition, so as to form an electroplated metal layer on the surface of the seed layer of the power chip, thereby obtaining a power module.

[0012] The manufacturing method of the power module of the present invention is as follows: firstly, the power chip is connected to the substrate, then the chip structure and circuit layout are estimated to design and process the first mold, the source electrode and the gate electrode are shielded by opening holes to prevent the source electrode and the gate electrode from being covered by the subsequent plastic packaging material, then the first mold is aligned with the chip, and the plastic packaging material is filled, and the first mold is removed after curing. Then, the second mold is covered on the surface of the power chip to form a masking layer for the sputtering seed layer, and then the power chip and the second mold are placed together in the vacuum chamber of the sputtering equipment for double-sided seed layer sputtering, and the sputtering time and power are controlled to obtain the seed layer of the required thickness. Then the second mold is removed, and then the power device with the seed layer is immersed in a plating solution containing metal ions, and the metal ions are deposited from the plating solution onto the seed layer to form an electroplated metal layer, thereby realizing the production of the power module.

[0013] The present invention realizes the design and production of the power module through the electroplating process. The technical solution of the present invention has the advantages of no welding, high thermal conductivity, high integration, and wafer-level integration. The present invention uses the first mold and the second mold as a masking layer, avoids the use of wire bonding and a ceramic substrate as a thermal conductive medium, reduces the heterogeneous interface connection and the heat dissipation path length, and increases the reliability and heat dissipation performance of the power module.

[0014] Preferably, in step S1, the adhesive includes at least one of a resin adhesive, a rubber adhesive, a polyvinyl acetate emulsion adhesive, an epoxy resin adhesive, and a UV adhesive.

[0015] More preferably, the resin adhesive includes a phenolic resin adhesive or a urea-formaldehyde resin adhesive.

[0016] More preferably, the rubber adhesive includes styrene-butadiene rubber adhesive or chloroprene rubber adhesive.

[0017] Because the above-mentioned materials contain a large amount of carbon or benzene rings (containing carbon) in their molecular structures, they may undergo thermal decomposition at high temperatures, producing gases such as carbon dioxide, which affects the adhesion performance. When UV glue is used, the cured UV glue is exposed to long-term or high-intensity ultraviolet rays again, and its bonding strength will decrease. This is because under the action of excessive ultraviolet rays, the chemical bonds inside the glue may undergo reactions such as breaking or degradation, causing changes in its structure and performance, thereby reducing the bonding strength. Therefore, the present invention uses the above-mentioned materials as adhesives to make it easier for the power chip to fall off from the substrate surface.

[0018] Preferably, the substrate includes one of a glass substrate, an organic polyimide (PI) substrate, a ceramic substrate, a glass fiber reinforced resin (FR-4) substrate, a BT packaging substrate, an ABF packaging substrate, and a MIS packaging substrate.

[0019] Preferably, in step S2, the molding compound includes at least one of polyimide, phenolic resin and polyparaxylene.

[0020] Preferably, the first mold and the second mold are made of steel, graphite or ceramic.

[0021] Preferably, in step S4, the sputtering time is 0.5-10 min, and the sputtering power is 50-1000 W.

[0022] Preferably, in step S5, the material of the electroplated metal layer may be one of copper, nickel, zinc, silver, chromium and gold.

[0023] Preferably, in step S5, the thickness of the electroplated metal layer is 0.5-50 μm.

[0024] In a second aspect, the present invention also provides a power module manufactured by the above method.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) The present invention can not only completely avoid packaging process flows and operations such as die bonding, wire bonding, and photolithography and development, but also realize wafer-level packaging and double-sided connection and heat dissipation of power chips, thereby greatly improving production efficiency and reducing costs.

[0027] (2) The present invention avoids traditional high-cost processes such as wire bonding, die bonding, photolithography and laser drilling by using temporary adhesives, mask jigs and electroplating processes, and realizes the packaging and manufacturing integration of power devices at the wafer level by first encapsulating and then connecting wiring, thereby meeting the requirements of heat dissipation and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure after the power chip is bonded to the surface of the substrate in the present invention.

[0029] Figure 2 It is a schematic diagram of the structure after the first mold and the substrate are embedded in the present invention.

[0030] Figure 3 It is a structural diagram used to illustrate the first mold of the present invention.

[0031] Figure 4 It is a schematic diagram of the structure after the first mold is removed in Example 1 of the present invention.

[0032] Figure 5 It is a schematic diagram of the structure after the substrate and the power chip are separated in the present invention.

[0033] Figure 6 It is a schematic diagram of the structure after the second mold covers the power chip in the present invention.

[0034] Figure 7 It is a schematic diagram of the structure of the power chip and the second mold after double-sided seed layer sputtering in the present invention.

[0035] Figure 8 It is a schematic diagram of the structure of the present invention after the second mold is removed.

[0036] Fig. 9 It is a structural schematic diagram of forming an electroplated metal layer on the surface of a power chip seed layer in the present invention.

[0037] Fig.10 It is a schematic diagram of the structure of the power module manufactured according to Example 2 of the present invention.

[0038] Fig.11 It is a schematic diagram of the structure of the power module manufactured in Comparative Example 7 of the present invention.

[0039] Figure 1-11 1 is the gate electrode; 2 is the source electrode; 3 is the power chip; 4 is the drain of the power chip; 5 is the adhesive; 6 is the substrate; 7 is the first mold; 8 is the plastic sealant; 9 is the second mold; 10 is the seed layer; 11 is the electroplated metal layer; and 12 is the bottom plate. DETAILED DESCRIPTION

[0040] In order to better illustrate the purpose, technical solutions and advantages of the present invention, the present invention will be further described below in conjunction with specific embodiments, but the protection scope and implementation methods of the present invention are not limited thereto.

[0041] Unless otherwise specified, the materials and reagents used in the following examples are commercially available.

[0042] Example 1

[0043] A method for manufacturing a power module comprises the following steps:

[0044] S1: Power chip connection process

[0045] like Figure 1 As shown, according to the layout design of the power chip, the side of the power chip drain 4 close to the substrate 6 is adhered to the surface of the substrate 6 through the adhesive 5. In this embodiment, the adhesive is a phenolic resin adhesive, and the substrate is a glass substrate.

[0046] In other embodiments, the adhesive may be urea-formaldehyde resin adhesive, styrene-butadiene rubber adhesive, chloroprene rubber adhesive, polyvinyl acetate emulsion adhesive or epoxy resin adhesive; the substrate may be a PI film, a ceramic substrate, an organic polyimide substrate, a glass fiber reinforced resin substrate, a BT packaging substrate, an ABF packaging substrate or an MIS packaging substrate.

[0047] S2: Hole masking and plastic injection process

[0048] The mask jig is designed and processed according to the chip structure and circuit layout, and then the source electrode 2 and the gate electrode 1 are shielded by openings to prevent the source electrode and the gate electrode from being covered by subsequent molding compound. The first mold 7 is then aligned with the power chip and filled with molding compound. After curing, the first mold 7 is removed.

[0049] like Figure 2As shown, the customized first mold 7 is embedded with the substrate 6 through the positioning holes and the bracket, and the first mold 7 as a masking layer is in close contact with the surface of the gate electrode 1 and the source electrode 2. The first mold 7 for forming the opening mask above the electrode is designed according to the chip layout and the distribution of the electrode, and the alignment and nesting of the mold and the power module are achieved by nesting the first mold 7 with the packaging substrate 6. The first mold 7 has the function of being able to align and position according to the substrate, such as Figure 3 The bracket in the design can be embedded in the positioning hole of the substrate, so that a precise opening is formed above the power chip after the subsequent plastic encapsulation compound is filled.

[0050] In this embodiment, the material of the first mold is steel, and its structure is as follows: Figure 3 7 in the figure; in other embodiments, the material of the first mold may be graphite or ceramic. Then, a plastic encapsulation material is poured into the packaged power module chamber, and the plastic encapsulation material seals the bare chip and the substrate by means of flow coating to isolate them from the external environment, and forms a protective layer of plastic encapsulation glue 8 after solidification. In this embodiment, the plastic encapsulation material is phenolic resin, and in other embodiments, it may be polyimide or polyparaxylene.

[0051] like Figure 4 As shown, the first mold 7 is removed. Since the first mold 7 forms a mask above the chip electrodes, a hole is opened on the surface of the power chip 3 without damage.

[0052] S3: Separate the substrate from the power chip

[0053] like Figure 5 As shown, the bonding strength of the adhesive 5 connecting the power chip 3 and the substrate 6 is reduced by high temperature, so that the substrate 6 can be separated from the power chip 3 more easily.

[0054] S4: Gate-source electrical isolation process for power chips

[0055] like Figure 6 As shown, the second mold 9 is customized and designed according to the positions of the source electrode 2 and the gate electrode 1, and the second mold 9 is covered on the surface of the plastic sealant between the gate electrode 1 and the source electrode 2 as a masking layer for realizing electrical isolation of the gate source electrode to avoid electrical contact between the source electrode 2 and the gate electrode 1 during the subsequent electroplating process. In this embodiment, the material of the second mold is steel, and in other embodiments, the material of the second mold can be graphite or ceramic. The second mold is mainly used to achieve precise alignment and opening with the power chip, so a positioning bracket with the same function as the first mold is used to achieve the engagement with the positioning hole on the substrate.

[0056] like Figure 7As shown, the cleaned power chip 3 and the second mold 9 are then placed together in the vacuum chamber of the sputtering equipment for double-sided seed layer sputtering, and the sputtering time is controlled to be 0.5-10min and the power is 50W-1000W to obtain the seed layer 10 of the required thickness, which is 5-100nm.

[0057] S5: Metal Deposition Process

[0058] like Figure 8 , 9 As shown, the second mold 9 is removed, and the power device with the seed layer 10 is immersed in a metal ion electroplating solution, and the metal ions are deposited from the electroplating solution onto the seed layer 10 to form a uniform and dense electroplated metal layer 11. The material of the electroplated metal layer can be copper, gold, nickel, zinc, silver, or chromium, and the thickness is between 0.5 μm and 50 μm. According to different metal types, the electroplating process parameters such as current density, temperature, and electroplating time are adjusted to finally achieve full copper coverage of the power module. The material of the metal layer deposited by the electroplating process in this step is copper, and in other embodiments it can be gold, nickel, zinc, silver, or chromium.

[0059] Among them, ① the main components of copper electroplating solution include copper sulfate (100-250g / L), sulfuric acid (50-200g / L), and also contain additives such as brightener (1-10ml / L), leveler (0.5-5ml / L), etc.; ② gold electroplating solution: generally a solution containing gold salt (such as potassium gold cyanide, 1-10g / L), citric acid (5-50g / L), phosphate buffer (10-100g / L), etc.; ③ nickel electroplating solution is mainly composed of nickel sulfate (200-350g / L), nickel chloride (30-70g / L) and boric acid (30-50g / L). The current density during the electroplating process is 0.5-10A / dm 2 between.

[0060] If you want to use the all-copper power module as a module unit, you can use a grinding wheel or laser to cut the batch-prepared all-copper power module array, and use the cut all-copper module as the smallest unit of the power module.

[0061] Example 2

[0062] A method for manufacturing a power module comprises the following steps:

[0063] S1: Power chip connection process

[0064] First, the metal solder is sintered and connected to the ceramic substrate. This process keeps the drain side of the power chip close to the substrate, so that the drain electrode of the power chip forms a metal connection with the patterned copper layer of the ceramic substrate.

[0065] S2: The hole masking and plastic sealant injection processes are the same as those in Example 1.

[0066] S3: Take away the first mold.

[0067] S4: Gate-source electrical isolation process for power chips

[0068] The second mold (made of steel) is customized according to the positions of the source electrode and the gate electrode. In the same way as the first mold, the second mold is embedded and covered on the surface of the power chip to form a masking layer of the sputtering seed layer, thereby spatially isolating the source electrode and the gate electrode to avoid electrical contact between the source electrode and the gate electrode during the subsequent electroplating process.

[0069] S5: Metal Deposition Process

[0070] The cleaned power chip and the second mold are placed together in the vacuum chamber of the sputtering equipment for seed layer sputtering. The type of sputtered metal is determined by the type of electroplated metal, which can be gold, nickel, zinc, silver, or chromium. The sputtering time is controlled to be 30 seconds to 10 minutes and the power is controlled to be 50 to 1000 W to obtain a seed layer of the desired thickness, which is 5 to 100 nm.

[0071] The second mold is then removed, and the power device with the seed layer is subsequently placed in an electroplating tank, where metal ions are deposited from the electroplating solution onto the seed layer to form a uniform and dense electroplated metal layer (the electroplated metal can be copper, gold, nickel, zinc, silver, or chromium, and the thickness of the electroplated metal layer is between 0.5 μm and 50 μm), thereby achieving the production of an all-copper module. The material of the metal layer deposited by the electroplating process in this step is copper. This module spatially extends the gate, source, and drain of the power chip, which is beneficial for wafer-level power module packaging. The structure of the power module finally manufactured is as follows: Fig.10 shown.

[0072] The method described in this embodiment does not remove the substrate 6 and the bottom plate 13 (the bottom plate is usually a metal flat plate, which is located at the bottom of the power module and mainly plays the role of heat dissipation and mechanical support), and can realize the design and production of a solder-free power module with a thermally conductive substrate.

[0073] Comparative Example 1

[0074] A method for manufacturing a power module is different from the first embodiment in that in step S2, a first mold is not used to engage with a substrate, but a laser is used to open a hole.

[0075] In this comparative example, since the first mold is not used for masking in step S2, but laser drilling is performed instead, not only will the electrodes on the chip surface be damaged, but the production efficiency is low and the cost is high.

[0076] Comparative Example 2

[0077] A method for manufacturing a power module is different from that of Embodiment 1 in that in step S4, no second mold is used to cover the surface of the power chip.

[0078] In this comparative example, since the second mold is not used for masking in step S4, the gate electrode of the power chip and the source electrode of the power chip cannot be electrically isolated, which ultimately results in a failed power module.

[0079] Comparative Example 3

[0080] A method for manufacturing a power module, which differs from Embodiment 1 in that, in step S4, the sputtering time is 15 minutes.

[0081] In this comparative example, the sputtering time is longer than 10 minutes, which causes problems such as changes in film properties, material waste and increased costs, and increased surface roughness. For some materials, sputtering for too long may change the crystal structure of the seed layer.

[0082] Comparative Example 4

[0083] A method for manufacturing a power module, which differs from Embodiment 1 in that, in step S4, the sputtering time is 25 seconds.

[0084] In this comparative example, the sputtering time is less than 30 seconds, resulting in insufficient film thickness, poor coverage, weak adhesion, etc. If the sputtering time is too short, the seed layer thickness will be too thin, so that the subsequently deposited metal layer cannot grow normally in the uncovered area, affecting the performance and reliability of the device.

[0085] Comparative Example 5

[0086] A method for manufacturing a power module, which is different from Embodiment 1 in that, in step S4, the sputtering power is 1100W.

[0087] In this comparative example, the sputtering power is higher than 1000 W, which causes the film quality to deteriorate (manifested as poor crystal quality and reduced film density), substrate damage, and composition deviation. High sputtering power means that the sputtered particles have higher energy, and these high-energy particles may cause physical damage to the substrate when they hit the substrate surface.

[0088] Comparative Example 6

[0089] A method for manufacturing a power module, which differs from Embodiment 1 in that, in step S4, the sputtering power is 40W.

[0090] In this comparative example, the sputtering power is lower than 50 W, resulting in problems such as too low deposition rate, weak film adhesion, and uneven coverage.

[0091] Comparative Example 7

[0092] A method for manufacturing a power module, which differs from Embodiment 1 in that, in step S4, the thickness of the electroplated metal layer is 0.4 μm.

[0093] like Fig.11 As shown, the thickness of the electroplated metal layer 11 in this comparative example is less than 0.5 μm, which results in the source and gate electrodes of the power chip not being able to extend to the module surface, thereby failing to form a fully copper-covered wafer-level package. In addition, too low a thickness will result in the metal layer being unable to conduct large currents, thereby limiting the current capacity and current level of the power module.

[0094] Comparative Example 8

[0095] A method for manufacturing a power module, which differs from Embodiment 1 in that, in step S4, the thickness of the electroplated metal layer is 55 μm.

[0096] In this comparative example, the thickness of the electroplated metal layer is higher than 50 μm, which results in an increase in the electrode thickness of the power module, thereby increasing the parasitic capacitance and series resistance. In addition, the thick electrode may generate greater stress during the manufacturing process or under temperature changes, thereby causing stress problems.

[0097] In summary, the present invention adopts a wafer-level full electroplating manufacturing method to achieve chip gate source drain rearrangement and connection, completely remove the solid crystal and wire bonding process, thereby avoiding the reliability problems caused by the thermal stress mismatch of the heterogeneous interface of traditional wire bonding and chip solid crystal. In addition, the electroplating process of the present invention can obtain a double-sided all-copper connection packaging structure, improve the heat dissipation efficiency of the device and reduce the junction temperature, and the wafer-level electroplating process has high production efficiency and can effectively reduce manufacturing and production costs. At the same time, the present invention introduces a wafer-level mask structure to replace the traditional laser opening and photolithography development process, which can not only avoid the heat loss of high-energy laser to the chip, but also realize the wafer-level one-time opening operation, thereby greatly improving production efficiency and reducing costs.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a power module, characterized in that: The following steps are involved: S1: bonding the drain electrode of the power chip to the surface of the substrate through an adhesive; S2: The first mold is embedded with the substrate and in contact with the surface of the power chip, so as to form a packaged power module cavity between the first mold and the power chip; then, a plastic encapsulation material is filled into the packaged power module cavity, and the plastic encapsulation material is cured and demolded; the first mold is designed according to the structure of the power chip and the substrate and is provided with a positioning hole and a bracket for embedding with the substrate; S3: removing the first mold; S4: Covering the second mold between the source electrode and the gate electrode on the surface of the power chip to form a masking layer for the sputtering seed layer, and then placing the power chip and the second mold together in a vacuum chamber of a sputtering device to perform double-sided seed layer sputtering; S5: removing the second mold, and then immersing the power chip with the seed layer into an electroplating solution containing metal ions for deposition, so as to form an electroplated metal layer on the surface of the seed layer of the power chip, thereby obtaining a power module.

2. The method for manufacturing a power module according to claim 1, wherein: In step S1, the adhesive includes at least one of a resin adhesive, a rubber adhesive, a polyvinyl acetate emulsion adhesive, an epoxy resin adhesive, and a UV adhesive.

3. The method for manufacturing a power module according to claim 2, wherein: The resin adhesive includes a phenolic resin adhesive or a urea-formaldehyde resin adhesive; and / or the rubber adhesive includes a styrene-butadiene rubber adhesive or a chloroprene rubber adhesive.

4. The method for manufacturing a power module according to claim 1, wherein: The substrate includes one of a glass substrate, an organic polyimide substrate, a ceramic substrate, a glass fiber reinforced resin substrate, a BT packaging substrate, an ABF packaging substrate, and a MIS packaging substrate.

5. The method for manufacturing a power module according to claim 1, wherein: In step S2, the molding compound includes at least one of polyimide, phenolic resin, and polyparaxylene.

6. The method for manufacturing a power module according to claim 1, wherein: The first mold and the second mold are made of steel, graphite or ceramic.

7. The method for manufacturing a power module according to claim 1, wherein: In step S4, the sputtering time is 0.5-10 min, and the sputtering power is 50-1000 W.

8. The method for manufacturing a power module according to claim 1, wherein: In step S5, the material of the electroplated metal layer can be one of copper, nickel, zinc, silver, chromium and gold.

9. The method for manufacturing a power module according to claim 1, wherein: In step S5, the thickness of the electroplated metal layer is 0.5-50 μm.

10. A power module manufactured by the method for manufacturing a power module according to any one of claims 1 to 9.

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