Method for manufacturing semiconductor packaging structure and semiconductor structure

Abstract

The embodiment of the present application provides a method for manufacturing a semiconductor packaging structure and a semiconductor structure. The method for manufacturing a semiconductor packaging structure includes: providing a first wafer and a second wafer; the first wafer includes a first circuit; the second wafer includes a second circuit; forming a lead-out structure penetrating the first wafer on the first surface of the first wafer; forming a first bonding layer on the second surface of the first wafer; the first surface of the first wafer and the second surface of the first wafer are two opposite surfaces; forming a second bonding layer on the surface of the second wafer; bonding the first wafer and the second wafer, the first bonding layer and the second bonding layer contact to form a bonding structure; the bonding structure connects the first circuit and the second circuit; wherein the lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit through the bonding structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor packaging structure and a semiconductor structure. Background Art

[0002] With the development of large-scale integrated circuits, the characteristic size of circuits is constantly shrinking, and chips are developing in the three-dimensional (3D) direction and entering the post-Moore era, thus meeting the requirements of high integration, fast transmission speed, and low power consumption. It is necessary to improve the device yield and reliability of three-dimensional stacked chips. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure and a semiconductor structure.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure, the manufacturing method comprising: providing a first wafer and a second wafer; the first wafer comprising a first circuit; the second wafer comprising a second circuit; forming a lead-out structure penetrating the first wafer on a first surface of the first wafer; forming a first bonding layer on a second surface of the first wafer; the first surface of the first wafer and the second surface of the first wafer are two opposite surfaces; forming a second bonding layer on the surface of the second wafer; bonding the first wafer and the second wafer, the first bonding layer and the second bonding layer contacting to form a bonding structure; the bonding structure connecting the first circuit and the second circuit; wherein the lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit via the bonding structure.

[0005] In some embodiments, a lead-out structure penetrating the first wafer is formed on the first side of the first wafer, including: forming a through silicon via penetrating the first wafer on the first side of the first wafer; forming a lead-out pad connected to the through silicon via on the through silicon via; the material of the through silicon via is different from the material of the lead-out pad; wherein the lead-out structure includes the through silicon via and the lead-out pad.

[0006] In some embodiments, a first wafer is provided, including: providing a first substrate; the first substrate including a first circuit; forming a first interconnection structure connected to the first circuit on a first surface of the first substrate; forming a first carrier sheet on the first interconnection structure; flipping the first carrier sheet and thinning the second surface of the first substrate to obtain a first wafer; the first carrier sheet carries the first wafer and exposes the first surface of the first wafer; the first surface of the first substrate and the second surface of the first substrate are two opposite surfaces.

[0007] In some embodiments, a first bonding layer is formed on the second side of the first wafer, including: forming a second carrier sheet on the lead-out pad; flipping the second carrier sheet and removing the first carrier sheet; the second carrier sheet carries the first wafer and exposes the second side of the first wafer; forming a first bonding via contacting the first interconnect structure and a first bonding pad contacting the first bonding via on the second side of the first wafer; wherein the first bonding layer includes the first bonding via and the first bonding pad.

[0008] In some embodiments, bonding the first wafer and the second wafer includes: removing the second carrier sheet after forming the bonding structure.

[0009] In some embodiments, forming a lead-out pad connected to the TSV on the TSV includes: forming a lead-out pad connected to the TSV on the TSV; forming a passivation layer on the lead-out pad; and the passivation layer exposing at least a portion of the surface of the lead-out pad.

[0010] In some embodiments, providing a second wafer includes: providing a second substrate; the second substrate includes a second circuit; and forming a second interconnect structure connected to the second circuit on a first surface of the second substrate.

[0011] In some embodiments, a second bonding layer is formed on the surface of the second wafer, including: forming a second bonding via contacting the second interconnect structure and a second bonding pad contacting the second bonding via on the surface of the second wafer; wherein the second bonding layer includes the second bonding via and the second bonding pad.

[0012] In some embodiments, bonding the first wafer and the second wafer includes: bonding the first wafer and the second wafer using a fusion bonding process or a hybrid bonding process.

[0013] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure, the manufacturing method comprising: providing a first chip and a wafer; the first chip comprises a first circuit; the wafer comprises a second circuit; a lead-out structure penetrating the first chip is formed on the first side of the first chip; a first bonding layer is formed on the second side of the first chip; the first side of the first chip and the second side of the first chip are two opposite surfaces; a second bonding layer is formed on the surface of the wafer; the first chip and the wafer are bonded, and the first bonding layer and the second bonding layer are in contact to form a bonding structure; the bonding structure connects the first circuit and the second circuit; wherein the lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit through the bonding structure.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor structure, which includes: a substrate; a semiconductor packaging structure obtained according to any one of the manufacturing methods provided in the first aspect, or a semiconductor packaging structure obtained according to the manufacturing method provided in the second aspect; the semiconductor packaging structure is located on the substrate and connected to the substrate through a lead-out structure of the semiconductor packaging structure.

[0015] In each embodiment of the present application, the lead-out structure of two wafers (a first wafer and a second wafer) is first made, and then the two wafers are bonded, so as to avoid the influence of the process of forming the lead-out structure due to bubble defects at the bonding interface, which may occur when the bonding structure of the two wafers is made first. For example, after the two wafers are bonded and then the lead-out structure of the two wafers is formed, the presence of bubble defects at the bonding interface may easily cause fragment defects in the process of forming the lead-out structure, thereby affecting the search mark of the subsequent lithography process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1C It is a schematic diagram of the bonding process in the related art;

[0017] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application;

[0018] FIG. 3A to FIG. 3I A schematic cross-sectional view of a manufacturing side of a semiconductor packaging structure provided by an embodiment of the present application;

[0019] Figure 4 A schematic flow chart of another method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will combine the implementation methods and drawings of this application to clearly and completely describe the technical solutions in the implementation methods of this application. The described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0022] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0023] The three-dimensional directions mainly include wafer to wafer stacking (wafer to wafer, W2W), chip to wafer heterogeneous integration (chip to wafer, C2W), and chip to chip heterogeneous integration (chip to chip, C2C).

[0024] Figures 1A to 1C It is a schematic diagram of the bonding process in the related art.

[0025] refer to Figure 1A , bonding the first wafer 102 and the second wafer 202. Figure 1B , the bonding process is prone to bubble defects BUB located at the bonding interface BS, and the back side of the first wafer 102 is thinned. Figure 1C , a lead-out structure 112 is formed on the back side of the thinned first wafer 102. Since the existing bonding process first bonds two wafers (the first wafer 102 and the second wafer 202) and then performs subsequent processes such as back thinning and lead-out structure, the bonding process is prone to bubble defects such as those located at the bonding interface. The bubble defects at the bonding interface will affect the subsequent thinning and lead-out structure processes. For example, back thinning of a wafer with bubble defects at the bonding interface is prone to produce chip defects, which will affect the search mark of the subsequent photolithography process.

[0026] In view of this, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure and a semiconductor structure.

[0027] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application.

[0028] In a first aspect, the present invention provides a method for manufacturing a semiconductor package structure, referring to Figure 2 , the manufacturing method comprises the following steps:

[0029] S101, providing a first wafer and a second wafer; the first wafer includes a first circuit; the second wafer includes a second circuit;

[0030] S102, forming a lead-out structure penetrating the first wafer on a first surface of the first wafer;

[0031] S103, forming a first bonding layer on the second surface of the first wafer; the first surface of the first wafer and the second surface of the first wafer are two opposite surfaces;

[0032] S104, forming a second bonding layer on the surface of the second wafer;

[0033] S105. Bond the first wafer to the second wafer, and the first bonding layer and the second bonding layer are in contact to form a bonding structure; the bonding structure connects the first circuit and the second circuit; wherein the lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit via the bonding structure.

[0034] It should be understood that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0035] FIG. 3A to FIG. 3I A cross-sectional schematic diagram of a manufacturing method of a semiconductor packaging structure provided in an embodiment of the present application. FIG. 3A to FIG. 3I The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; FIG. 3A to FIG. 3I The steps shown in the figure can be adjusted in sequence according to actual needs.

[0036] Here and below, for the convenience of describing the embodiments of the present application, the first direction and the second direction are represented as two orthogonal directions parallel to the wafer plane; the third direction is a direction perpendicular to the wafer plane or the third direction is a direction parallel to the wafer thickness (or the direction of multiple wafers stacked). Exemplarily, the first direction can be represented as the X direction in the accompanying drawings; the second direction can be represented as the Y direction in the accompanying drawings; and the third direction can be represented as the Z direction in the accompanying drawings.

[0037] Combine the following Figure 2 and FIG. 3A to FIG. 3I The method for manufacturing the bonding structure provided in the embodiment of the present application is described in detail.

[0038] Step S101 is executed to provide a first wafer and a second wafer.

[0039] Here and below, the first wafer and the second wafer may be two opposite wafers to be bonded. In the following specific embodiments, the first wafer and the second wafer may also be understood to be interchangeable.

[0040] In some embodiments, the chips of the first wafer and the chips of the second wafer may include semiconductor chips of different types. For example, the chips of the first wafer may include logic chips, and the chips of the second wafer may include memory chips. Alternatively, the chips of the first wafer and the chips of the second wafer may include semiconductor chips of the same type. For example, both the chips of the first wafer and the chips of the second wafer may include logic chips.

[0041] The logic chip can be, for example, a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application specific integrated circuit (ASIC).

[0042] The memory chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or may be a non-volatile memory chip, such as a resistive random access memory (RRAM) chip.

[0043] refer to Figure 3A and Figure 3B In some embodiments, a first wafer is provided, including: providing a first substrate; the first substrate includes a first circuit; forming a first interconnection structure 106 connected to the first circuit on a first surface of the first substrate; forming a first carrier sheet 301 on the first interconnection structure 106; flipping the first carrier sheet 301, thinning the second surface of the first substrate, and obtaining a first wafer; the first carrier sheet carries the first wafer and exposes the first surface of the first wafer; the first surface of the first substrate and the second surface of the first substrate are two opposite surfaces.

[0044] By way of example, the chips of the first wafer 102 may include logic chips.

[0045] refer to Figure 3AIn some implementations, the first circuit and the first interconnect structure can be formed by a lithography-etching process (Lithography-Etch, LE) and a deposition process, wherein the deposition process includes but is not limited to a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) and other processes.

[0046] refer to Figure 3A The material of the first substrate 104 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Figure 3A The first substrate 104 is formed with a first substrate 106 (not shown), and the first circuit may include a variety of active devices and passive devices (such as capacitors, resistors, inductors and the like) that meet the desired structural and functional requirements of the design. The first circuit function circuit 121 may include an NMOS device or a PMOS device. The first interconnect structure 106 includes an interconnect layer located in the insulating layer, and the interconnect layer connects the first circuit. The material of the insulating layer (also referred to as the dielectric layer herein) includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The material of the interconnect layer includes but is not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof. The interconnect layer may be a conductive via and a conductive distribution layer connected to each other.

[0047] Continue to refer Figure 3A , a dielectric layer is deposited on the first interconnect structure 106, and a first carrier sheet 301 bonded to the dielectric layer is formed by a temporary bonding process. The first carrier sheet 301 can be used as a carrier sheet when the first substrate 104 is subsequently thinned (refer to Figure 3B ). The material of the dielectric layer may be silicon oxide.

[0048] refer to Figure 3B , the first carrier sheet 301 is turned over to thin the second surface of the first substrate 104, and the first wafer is obtained. The first surface of the first substrate and the second surface of the first substrate are two opposite surfaces, wherein the first surface can be understood as a surface for forming the first circuit, for example, the second surface of the first substrate can be understood as a surface for forming the first circuit thereon, and for another example, the second surface of the first wafer can be understood as a surface for forming the first interconnect structure 106 thereon. The first carrier sheet 301 carries the first wafer 102 and exposes the first surface S1 of the first wafer 102.

[0049] refer to Figure 3C and Figure 3D In some embodiments, a lead-out structure penetrating the first wafer is formed on the first side of the first wafer, including: forming a through silicon via 108 penetrating the first wafer on the first side of the first wafer; forming a lead-out pad 110 connected to the through silicon via 108 on the through silicon via 108; the material of the through silicon via 108 is different from the material of the lead-out pad 110; wherein the lead-out structure 112 includes the through silicon via 108 and the lead-out pad 110.

[0050] refer to Figure 3C , a dielectric layer is formed on the first surface of the first wafer by a deposition process, a through hole penetrating the dielectric layer and the first wafer is formed by a photolithography-etching process, and a conductive material is formed in the through hole by a deposition process to obtain a through silicon via 108, and the through silicon via 108 extends and is connected to the first interconnect structure 106. The through silicon via 108 can be made of the same material as the interconnect layer. For example, the material of the through silicon via 108 can be copper or a copper alloy.

[0051] refer to Figure 3D , a dielectric layer is formed on the through silicon via 108 by a deposition process, and a lead pad 110 is formed in the dielectric layer by a photolithography-etching process and a deposition process. A conductive material is formed in the through hole by a deposition process to obtain the through silicon via 108, and the through silicon via 108 extends and is connected to the first interconnect structure 106. The lead pad 110 may be made of a different material from the through silicon via 108. For example, the material of the lead pad 110 may be aluminum or an aluminum alloy.

[0052] refer to Figure 3D In some embodiments, forming a lead-out pad 110 connected to the through silicon via 108 on the through silicon via 108 includes: forming the lead-out pad 110 connected to the through silicon via 108 on the through silicon via 108; forming a passivation layer 114 on the lead-out pad 110; and the passivation layer 114 exposes at least a portion of the surface of the lead-out pad 110. The passivation layer 114 has an opening OP, and the opening OP exposes at least a portion of the surface of the lead-out pad 110.

[0053] refer to Figures 3E to 3G In some embodiments, a first bonding layer is formed on the second side of the first wafer, including: forming a second carrier sheet on the lead-out pad; flipping the second carrier sheet and removing the first carrier sheet; the second carrier sheet carries the first wafer and exposes the second side of the first wafer; forming a first bonding via contacting the first interconnect structure and a first bonding pad contacting the first bonding via on the second side of the first wafer; wherein the first bonding layer 120 includes a first bonding via 116 and a first bonding pad 118.

[0054] refer to Figure 3E, a dielectric layer is deposited on the lead pad 110, and a second carrier 302 bonded to the dielectric layer is formed by a temporary bonding process. The second carrier 302 can be used as a carrier when the first bonding pad is subsequently formed on the second surface of the first wafer (refer to Figure 3F ). The material of the dielectric layer may be silicon oxide.

[0055] refer to Figure 3F , flip the second carrier sheet 302, and remove the first carrier sheet 301 by a dissociation process (refer to Figure 3E ), the second carrier sheet 302 carries the first wafer 102 and exposes the dielectric layer of the second surface S2 of the first wafer 102 .

[0056] refer to Figure 3G , forming a first bonding dielectric layer 122 on the dielectric layer, and forming a first bonding via 116 and a first bonding pad 118 penetrating the first bonding dielectric layer and the dielectric layer. Exemplarily, the material of the first bonding dielectric layer 122 may include but is not limited to polyimide, silicon carbon nitride or silicon oxide; the material of the first bonding via 116 and the first bonding pad 118 includes copper or copper alloy.

[0057] refer to Figure 3H In some embodiments, providing a second wafer 202 includes: providing a second substrate 204; the second substrate 204 includes a second circuit ( Figure 3H (not shown); a second interconnect structure 206 connected to the second circuit is formed on the first surface of the second substrate 204. The second wafer 202, the second substrate 204, the second circuit and the second interconnect structure 206 can be understood by referring to the above descriptions of the first wafer 102 and the first wafer 102, the first substrate 104, the first circuit and the first interconnect structure 106, respectively, and will not be repeated here. For example, the chip of the second wafer 202 may include a memory chip.

[0058] Continue to refer Figure 3H In some embodiments, a second bonding layer 220 is formed on the surface of the second wafer 202, including: forming a second bonding via 216 in contact with the second interconnect structure and a second bonding pad 218 in contact with the second bonding via on the surface of the second wafer 202; wherein the second bonding layer 220 includes the second bonding via 216 and the second bonding pad 218. The second bonding layer 220, the second bonding via 216, and the second bonding pad 218 can be understood by referring to the above-mentioned descriptions of the first bonding layer 120, the first bonding via 116, and the first bonding pad 118, and will not be repeated here.

[0059] refer to FIG. 3H to FIG. 3IIn some embodiments, bonding the first wafer 102 and the second wafer 202 includes: removing the second carrier sheet 302 after forming the bonding structure BS. The second carrier sheet 302 is removed by a dissociation process. The second wafer 202 carries the first wafer 102 and exposes the dielectric layer on the lead-out pads 110 of the first wafer 102. In some embodiments, the dielectric layer formed in the opening OP is removed to expose the top surface of the lead-out pad 110 indicating a portion.

[0060] refer to FIG. 3H to FIG. 3I In some embodiments, bonding the first wafer to the second wafer includes: bonding the first wafer to the second wafer using a fusion bonding process or a hybrid bonding process.

[0061] refer to Fig. 3I In some embodiments, the bonding interface BS obtained by the hybrid bonding process may include a bonding interface between metal layers and a bonding interface between dielectric layers. In an optional embodiment, the bonding interface obtained by the fusion bonding process may include a bonding interface between metal layers and metal layers, a bonding interface between metal layers and dielectric layers, and a bonding interface between dielectric layers.

[0062] Although the semiconductor package structure including two wafers (a first wafer and a second wafer) is shown in the present exemplary embodiment, Fig. 3I As shown), alternatively, the first wafer is replaced by a plurality of first stacked wafers for understanding, for example, the plurality of first stacked wafers may be two, three or even more stacked logic chips; alternatively, the second wafer is replaced by a plurality of second stacked wafers for understanding, for example, the plurality of second stacked wafers may be two, three or even more stacked memory chips.

[0063] refer to Fig. 3I In some example embodiments, the chips of the stacked first wafer and the chips of the stacked second wafer may constitute a High Bandwidth Memory (HBM) DRAM.

[0064] refer to Fig. 3I In some example embodiments, the first wafer 102 includes a plurality of first chips, the second wafer 202 includes a plurality of second chips, and the first wafer 102 and the second wafer 202 are bonded together along a scribe line (SL) ( Fig. 3I The chip is cut (not shown) to obtain a plurality of stacked chips (dies).

[0065] Figure 4 A schematic flow chart of another method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application.

[0066] In a second aspect, the present application provides a method for manufacturing a semiconductor packaging structure, referring to Figure 4 , the manufacturing method comprises the following steps:

[0067] S201, providing a first chip and a wafer; the first chip includes a first circuit; the wafer includes a second circuit;

[0068] S202, forming a lead-out structure penetrating the first chip on a first surface of the first chip;

[0069] S203, forming a first bonding layer on the second surface of the first chip; the first surface of the first chip and the second surface of the first chip are two opposite surfaces;

[0070] S204, forming a second bonding layer on the surface of the wafer;

[0071] S205, bonding the first chip and the wafer, the first bonding layer and the second bonding layer are in contact to form a bonding structure; the bonding structure connects the first circuit and the second circuit; wherein the lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit via the bonding structure.

[0072] In the present application embodiment, FIG. 3A to FIG. 3I The first wafer 102 shown in the figure is replaced by the first chip. In the embodiment of the present application, the wafer can be understood as FIG. 3A to FIG. 3I A second wafer 202 is shown.

[0073] In some embodiments, the second wafer 202 includes a plurality of second chips, and the bonded first chips and the second wafer 202 are diced along the dicing grooves ( Fig. 3I The chip is cut (not shown) to obtain a plurality of stacked chips.

[0074] Exemplarily, the stacked chip includes a first chip and a second chip bonded together; the first chip includes a first circuit; the second chip includes a second circuit; the lead-out structure of the first chip is located on the first side of the first chip; the first bonding layer is located on the second side of the first chip; the first side of the first chip and the second side of the first chip are two opposite surfaces; the second bonding layer is located on the surface of the second chip; the first bonding layer and the second bonding layer are in contact to form a bonding structure; the bonding structure connects the first circuit and the second circuit; wherein the lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit via the bonding structure.

[0075] In each embodiment of the present application, the lead-out structure of two wafers (a first wafer and a second wafer) is first made, and then the two wafers are bonded, so as to avoid the influence of the process of forming the lead-out structure due to bubble defects at the bonding interface, which may occur when the bonding structure of the two wafers is made first. For example, after the two wafers are bonded and then the lead-out structure of the two wafers is formed, the presence of bubble defects at the bonding interface may easily cause fragment defects in the process of forming the lead-out structure, thereby affecting the search mark of the subsequent lithography process.

[0076] In a third aspect, an embodiment of the present application provides a semiconductor structure, which includes: a substrate; a semiconductor packaging structure obtained according to any one of the manufacturing methods provided in the first aspect, or a semiconductor packaging structure obtained according to the manufacturing method provided in the second aspect; the semiconductor packaging structure is located on the substrate and connected to the substrate through a lead-out structure of the semiconductor packaging structure.

[0077] substrate ( Fig. 3I A substrate (not shown) is used as a substrate for the semiconductor package structure, which may be a printed circuit board (PCB), a glass substrate, a ceramic substrate, or a board with wiring.

[0078] The semiconductor package structure in the embodiment of the present application may be chip-level, and the lead-out structure of the semiconductor package structure may be connected to the substrate via a micro-bump.

[0079] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0080] The above description is only a preferred implementation mode of the present application, and does not limit the protection scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Providing a first wafer and a second wafer; the first wafer includes a first circuit; the second wafer includes a second circuit; forming a lead-out structure penetrating the first wafer on the first surface of the first wafer; forming a first bonding layer on the second surface of the first wafer; the first surface of the first wafer and the second surface of the first wafer are two opposite surfaces; forming a second bonding layer on the surface of the second wafer; Bonding the first wafer and the second wafer, wherein the first bonding layer and the second bonding layer are in contact with each other to form a bonding structure; the bonding structure connects the first circuit and the second circuit; The lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit via the bonding structure.

2. The manufacturing method according to claim 1, characterized in that: A lead-out structure penetrating the first wafer is formed on the first surface of the first wafer, including: forming a through silicon via penetrating the first wafer on a first surface of the first wafer; A lead pad connected to the through silicon via is formed on the through silicon via; the material of the through silicon via is different from that of the lead pad; wherein the lead structure includes the through silicon via and the lead pad.

3. The manufacturing method according to claim 2, characterized in that: The providing of a first wafer comprises: Providing a first substrate; the first substrate includes the first circuit; forming a first interconnect structure connected to the first circuit on the first surface of the first substrate; forming a first carrier sheet on the first interconnect structure; The first carrier sheet is turned over and the second surface of the first substrate is thinned to obtain the first wafer; the first carrier sheet carries the first wafer and exposes the first surface of the first wafer; the first surface of the first substrate and the second surface of the first substrate are two opposite surfaces.

4. The manufacturing method according to claim 3, characterized in that: Forming a first bonding layer on the second surface of the first wafer, comprising: forming a second carrier sheet on the lead-out pad; Turning over the second carrier sheet and removing the first carrier sheet; the second carrier sheet carries the first wafer and exposes the second surface of the first wafer; A first bonding via contacting the first interconnect structure and a first bonding pad contacting the first bonding via are formed on the second surface of the first wafer; wherein the first bonding layer includes the first bonding via and the first bonding pad.

5. The manufacturing method according to claim 4, characterized in that: Bonding the first wafer and the second wafer, comprising: The second carrier sheet is removed after the bonding structure is formed.

6. The manufacturing method according to claim 2, characterized in that: Forming a lead-out pad connected to the through silicon via on the through silicon via, comprising: forming a lead-out pad connected to the through silicon via on the through silicon via; A passivation layer is formed on the lead-out pad; the passivation layer exposes at least a portion of the surface of the lead-out pad.

7. The manufacturing method according to claim 1, characterized in that: The providing of the second wafer comprises: Providing a second substrate; the second substrate includes the second circuit; A second interconnect structure connected to the second circuit is formed on the first surface of the second substrate.

8. The manufacturing method according to claim 7, characterized in that: Forming a second bonding layer on the surface of the second wafer, comprising: A second bonding via in contact with the second interconnect structure and a second bonding pad in contact with the second bonding via are formed on the surface of the second wafer; wherein the second bonding layer includes the second bonding via and the second bonding pad.

9. The manufacturing method according to claim 1, characterized in that: Bonding the first wafer and the second wafer, comprising: The first wafer and the second wafer are bonded by using a fusion bonding process or a hybrid bonding process.

10. A method for manufacturing a semiconductor packaging structure, characterized in that: include: A first chip and a wafer are provided; the first chip includes a first circuit; the wafer includes a second circuit; forming a lead-out structure penetrating the first chip on the first surface of the first chip; forming a first bonding layer on the second surface of the first chip; the first surface of the first chip and the second surface of the first chip are two opposite surfaces; forming a second bonding layer on the surface of the wafer; Bonding the first chip and the wafer, wherein the first bonding layer and the second bonding layer are in contact with each other to form a bonding structure; the bonding structure connects the first circuit and the second circuit; The lead-out structure is connected to the second circuit, and / or the lead-out structure is connected to the second circuit via the bonding structure.

11. A semiconductor structure, characterized in that: include: substrate; A semiconductor package structure obtained by the manufacturing method according to any one of claims 1 to 9, or a semiconductor package structure obtained by the manufacturing method according to claim 10; The semiconductor package structure is located on the substrate and is connected to the substrate through a lead-out structure of the semiconductor package structure.

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