Shallow trench isolation formation method, semiconductor devices and chips

Abstract

This invention provides a shallow trench isolation formation method, a semiconductor device, and a chip, relating to the field of semiconductor technology. The shallow trench isolation formation method includes: providing a substrate, and sequentially forming a buffer layer and a stop layer with an etching window on the upper surface of the substrate; performing a first etching process on the buffer layer through the etching window to form a buffer trench; wherein the trench wall of the buffer trench has a concave arc-shaped configuration; performing a second etching process on the bottom of the buffer trench to form an initial isolation trench on the substrate at the bottom of the buffer trench; the opening of the initial isolation trench connecting to the buffer trench has a smooth chamfer configuration; performing a third etching process on the bottom of the initial isolation trench to deepen the initial isolation trench, forming an isolation trench; and filling the isolation trench to form a shallow trench isolation. This invention enables the formation of a smooth chamfer at the opening of the shallow trench isolation, improving the performance stability of the semiconductor structure and enhancing the reliability of the semiconductor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a shallow trench isolation formation method, a semiconductor device, and a chip. Background Technology

[0002] Shallow trench isolation (STI) is a structure used in semiconductor manufacturing to isolate transistors and other semiconductor devices. Its main function is to create electrically isolated regions on a silicon wafer to prevent electrical interference between different devices while maintaining a compact layout between them.

[0003] In existing technologies, a buffer layer 101 and a stop layer are typically formed sequentially on a substrate. Then, a shallow trench isolation etching window is formed on the buffer layer. The substrate is etched through the shallow trench isolation etching window to form a rectangular trench. Subsequently, a dielectric is filled into the rectangular trench to form a shallow trench isolation. The shallow trench isolation formed in this way has an insufficiently smooth opening near the substrate, resulting in poor performance and low reliability of the semiconductor structure. Summary of the Invention

[0004] To address the technical problems of poor performance and low reliability of semiconductor structures in the prior art, this invention provides a shallow trench isolation formation method, a semiconductor device, and a chip. The shallow trench isolation formation method can form a smooth chamfer at the opening of the shallow trench isolation, effectively avoiding the loss of the gate oxide layer subsequently formed on the shallow trench isolation, improving the performance stability of the semiconductor structure, and enhancing the reliability of the semiconductor.

[0005] To achieve the above objectives, a first aspect of the present invention provides a method for forming shallow trench isolation, the method comprising: providing a substrate, and sequentially forming a buffer layer and a stop layer having an etching window on the upper surface of the substrate; wherein the etching window can expose the buffer layer; performing a first etching process on the buffer layer through the etching window to form a buffer trench on the buffer layer; wherein the trench wall of the buffer trench has a concave arc-shaped configuration; the buffer trench can expose the substrate; performing a second etching process on the bottom of the buffer trench to form an initial isolation trench on the substrate; wherein the opening of the initial isolation trench and the buffer trench is a rounded chamfer configuration; performing a third etching process on the bottom of the initial isolation trench to deepen the depth of the initial isolation trench, forming an isolation trench on the substrate; and filling the isolation trench to form a shallow trench isolation.

[0006] Furthermore, the etching gases used in the first etching process include isotropic etching gases and anisotropic etching gases.

[0007] Furthermore, the etching gases used in the second etching process include isotropic etching gases and anisotropic etching gases.

[0008] Furthermore, isotropic etching gases include, but are not limited to, one or more of SF6, CH2F2, and C4F8.

[0009] Furthermore, the etching gas used in the third etching process includes anisotropic etching gases.

[0010] Furthermore, the anisotropic etching gases include, but are not limited to, one or both of Cl2 and HBr.

[0011] Furthermore, the gases used in the first etching process include CH2F2, SF6, and HBr; the etching conditions for the first etching process include: the flow rate of CH2F2 is between 0 and 60 sccm; the flow rate of SF6 is between 0 and 60 sccm; the flow rate of HBr is between 0 and 40 sccm; the etching time is between 20 s and 40 s; the reaction pressure is between 5 mtorr and 20 mtorr; and the bias power of the reaction chamber is between 100 W and 400 W.

[0012] Furthermore, the gases used in the second etching process include: Cl2, CH2F2, O2, and HBr; the etching conditions for the second etching process include: a Cl2 flow rate of 50 sccm to 100 sccm; a CH2F2 flow rate of 0 sccm to 60 sccm; a O2 flow rate of 0 to 10 sccm; a HBr flow rate of 0 to 40 sccm; and an etching time of 10 s to 30 s; the electric field parameters for the second etching process include: a reaction pressure of 20 mtorr to 50 mtorr; and a bias power of 200 W to 400 W for the reaction chamber.

[0013] Furthermore, the gases used in the third etching process include Cl2, O2, and HBr; the etching conditions for the third etching process include: O2 flow rate between 0 and 10 sccm; Cl2 flow rate between 50 and 200 sccm; HBr flow rate between 20 and 100 sccm; etching time between 40 and 60 seconds; reaction pressure between 5 and 20 mtorr; and bias power of the reaction chamber between 100 W and 400 W.

[0014] Furthermore, the thickness of the buffer layer is between

[0015] A second aspect of the present invention provides a semiconductor device comprising a shallow trench isolation formed by the shallow trench isolation formation method described above.

[0016] A third aspect of the present invention provides a chip comprising the semiconductor device described above.

[0017] The present invention has at least the following technical effects through the technical solution provided by the present invention:

[0018] The shallow trench isolation formation method of the present invention sequentially forms a buffer layer and a stop layer on the upper surface of a substrate. An etching window is formed in the stop layer to expose the buffer layer. A first etching process is performed on the buffer layer through the etching window to form a buffer trench with concave arc-shaped walls. A second etching process is then performed on the bottom of the buffer trench to form an initial isolation trench on the substrate at the bottom of the buffer trench. Because the walls of the buffer trench are concave arc-shaped, the angle between the trench walls and the substrate is greater than 90 degrees. This facilitates the formation of a smooth chamfered trench opening at the junction with the buffer trench during the initial isolation trench formation, effectively avoiding losses in the gate oxide layer subsequently formed on the shallow trench isolation and improving the performance stability of the semiconductor structure. A third etching process is then performed on the bottom of the initial isolation trench to deepen the initial isolation trench, forming an isolation trench. A dielectric is then filled into the isolation trench to form a shallow trench isolation. This invention enables the formation of smooth chamfers in the openings of shallow trench isolation, effectively avoiding losses in the gate oxide layer subsequently formed on the shallow trench isolation, improving the performance stability of the semiconductor structure, and enhancing the reliability of the semiconductor structure.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0021] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0022] Figure 1 A flowchart of a shallow trench isolation formation method provided in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the shallow trench isolation structure formed in the existing shallow trench isolation forming method;

[0024] Figure 3 This is a schematic diagram of the structure of a substrate formed in one embodiment of the shallow trench isolation formation method provided in this invention.

[0025] Figure 4This is a schematic diagram of the structure of the buffer layer and the stop layer formed in one embodiment of the shallow trench isolation forming method provided by the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of an etched window formed in one embodiment of the shallow trench isolation formation method provided by the present invention;

[0027] Figure 6 This is a schematic diagram of the structure of a buffer trench formed in one embodiment of the shallow trench isolation forming method provided by the present invention;

[0028] Figure 7 This is a schematic diagram of the structure of an initial isolation trench formed in one embodiment of the shallow trench isolation forming method provided by the present invention;

[0029] Figure 8 This is a schematic diagram of the structure of an isolation trench formed in one embodiment of the shallow trench isolation forming method provided by the present invention;

[0030] Figure 9 This is a schematic diagram of the structure of a shallow trench isolation formed in one embodiment of the shallow trench isolation forming method provided in this invention.

[0031] Explanation of reference numerals in the attached figures

[0032] 100-Substrate; 101-Buffer layer; 102-Stop layer; 103-Initial opening; 104-Shallow trench isolation; 200-Substrate; 201-Buffer layer; 202-Stop layer; 203-Buffer trench; 204-Initial isolation trench; 205-Isolation trench; 206-Shallow trench isolation. Detailed Implementation

[0033] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0035] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0036] As described in the background section, existing semiconductor devices have poor performance. This will be explained in detail below with reference to the accompanying drawings.

[0037] Please refer to Figure 2In the prior art, a substrate 100 is first provided, and then a buffer layer 101 and a stop layer 102 are sequentially formed on the substrate 100. Next, an etching window is formed in the stop layer 102, and the buffer layer 101 is etched through the etching window to form an initial opening 103 in the buffer layer 101, exposing the underlying substrate 100. Then, the substrate 100 is etched downwards through the initial opening 103 to form an isolation trench. A dielectric is filled into the isolation trench to form a shallow trench isolation 104. The gas used in the etching process is chlorine, and the etching process is all vertically downwards, resulting in insufficiently smooth corners at the openings of the formed shallow trench isolation 104, which reduces the performance reliability of the semiconductor structure.

[0038] Based on this, the present invention provides a shallow trench isolation formation method. A buffer layer and a stop layer are sequentially formed on the upper surface of a substrate. An etching window is formed in the stop layer to expose the buffer layer. A first etching process is performed on the buffer layer through the etching window to form a buffer trench. The walls of the buffer trench have a concave arc-shaped configuration. Next, a second etching process is performed on the bottom of the buffer trench to form an initial isolation trench on the substrate at the bottom of the buffer trench. Because the walls of the buffer trench have a concave arc-shaped configuration, the angle between the trench walls and the substrate is greater than 90 degrees. This facilitates the formation of a smooth chamfered trench opening near the buffer trench when forming the initial isolation trench, effectively avoiding losses in the gate oxide layer subsequently formed on the shallow trench isolation, and improving the performance stability of the semiconductor structure. Then, a third etching process is performed on the bottom of the initial isolation trench to deepen the initial isolation trench, forming an isolation trench. A dielectric is filled in the isolation trench to form a shallow trench isolation. This invention enables the formation of smooth chamfers in the openings of shallow trench isolation, effectively avoiding losses in the gate oxide layer subsequently formed on the shallow trench isolation, improving the performance stability of the semiconductor structure, and enhancing the reliability of the semiconductor structure.

[0039] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Please refer to Figure 1The first aspect of this invention provides a shallow trench isolation formation method, the method comprising: S101: providing a substrate 200 and sequentially forming a buffer layer 201 and a stop layer 202 having an etching window on the upper surface of the substrate 200; wherein the etching window is capable of exposing the buffer layer 201; S102: performing a first etching process on the buffer layer 201 through the etching window to form a buffer trench 203 in the buffer layer 201; wherein the trench wall of the buffer trench 203 has an inwardly concave arc-shaped configuration; the buffer trench 203 is capable of... S103: Expose the substrate 200; S104: Perform a second etching process on the bottom of the buffer trench 203 to form an initial isolation trench 204 on the substrate 200; wherein the opening of the initial isolation trench 204 and the buffer trench 203 is a rounded chamfer configuration; S105: Perform a third etching process on the bottom of the initial isolation trench 204 to deepen the depth of the initial isolation trench 204 and form an isolation trench 205 on the substrate 200; S106: Fill the isolation trench 205 to form a shallow trench isolation 206.

[0041] Specifically, step S101 is first performed: a substrate 200 is provided and a buffer layer 201 and a stop layer 202 with an etching window are sequentially formed on the upper surface of the substrate 200; wherein the etching window can expose the buffer layer 201.

[0042] Specifically, in the embodiments of the present invention, firstly, a Figure 3 The substrate 200 shown is one of a silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. Then, a [structure / form] is formed on the substrate 200. Figure 4 The buffer layer 201 and stop layer 202 are shown. The buffer layer 201 is made of silicon oxide and is formed by deposition or secondary oxidation. The stop layer 202 is made of silicon nitride and is formed by deposition. During the subsequent formation of the isolation structure 206, the stop layer 202 can serve as a stop layer for planarizing the isolation structure 206. Because the stop layer 202 is made of silicon nitride, it has high stress, and direct deposition onto the silicon substrate 200 would cause dislocations on the silicon surface. Depositing a layer of silicon oxide as the buffer layer 201 can prevent the silicon nitride material of the stop layer 202 from depositing on the silicon surface and causing dislocations.

[0043] like Figure 5As shown, an anti-reflection layer (not shown) is then formed on the stop layer 202, followed by the formation of a mask layer (not shown) with an etching window. The etching window of the mask layer exposes a portion of the stop layer 202. The stop layer 202 is etched through the etching window, transferring the etching window to the stop layer 202 until the buffer layer 201 is exposed. The anti-reflection layer reduces or eliminates light reflection on the semiconductor surface, thereby improving the accuracy and efficiency of the photolithography process. The mask layer is made of organic materials and is used to define the positions of the subsequently formed buffer trench 203, initial isolation trench 204, and isolation trench 205.

[0044] Next, step S102 is performed: the buffer layer 201 is etched through an etching window to form a buffer trench 203 in the buffer layer 201; wherein the trench wall of the buffer trench 203 is a concave arc-shaped configuration; the buffer trench 203 can expose the substrate 200.

[0045] Furthermore, the etching gases used in the first etching process include isotropic etching gases and anisotropic etching gases.

[0046] Furthermore, isotropic etching gases include, but are not limited to, one or more of SF6, CH2F2, and C4F8.

[0047] Furthermore, the anisotropic etching gases include, but are not limited to, one or both of Cl2 and HBr.

[0048] Furthermore, the gases used in the first etching process include CH2F2, SF6, and HBr; the etching conditions for the first etching process include: the flow rate of CH2F2 is between 0 and 60 sccm; the flow rate of SF6 is between 0 and 60 sccm; the flow rate of HBr is between 0 and 40 sccm; the etching time is between 20 s and 40 s; the reaction pressure is between 5 mtorr and 20 mtorr; and the bias power of the reaction chamber is between 100 W and 400 W.

[0049] Furthermore, the thickness of the buffer layer 201 is between

[0050] Specifically, in this embodiment of the invention, the buffer layer 201 is subjected to a first etching process through an etching window to form a buffer layer 201. Figure 6The buffer trench 203 is shown. The etching gases used in the first etching process include isotropic etching gases and anisotropic etching gases. Introducing an isotropic etching gas into the etching gas of the first etching process allows the buffer layer 201 to be etched along the direction parallel to the substrate 200 while forming the buffer trench 203. This better exposes the chamfered area in subsequent process steps, providing a good process foundation for subsequent processes. Introducing anisotropic etching gases allows the buffer layer 201 to be etched along the direction perpendicular to the substrate 200 surface, effectively ensuring the morphology of the formed buffer trench 203 and guaranteeing process efficiency. The etching gases used in this embodiment include CH2F2, SF6, and HBr. By using isotropic and anisotropic etching gases, combined with the process parameters of the first etching, a buffer trench 203 with an inwardly concave arc-shaped configuration can be formed. This makes the angle between the bottom wall of the buffer trench 203 and the substrate 200 greater than 90°, thereby better exposing the chamfered position in subsequent process steps and facilitating the formation of a smooth chamfered opening.

[0051] The thickness of the buffer layer 201 is between The buffer layer 201 has a relatively large thickness, which makes it easier to form an arc-shaped configuration with concave trench walls when etching the buffer layer 201 later. The trench walls have an inclination angle greater than 90° with the substrate 200, which is also beneficial to control the inclination angle of the initial isolation trench 204 formed by subsequent etching and optimize the morphology of the initial isolation trench 204.

[0052] In this embodiment, the setting of etching gas and process parameters in the first etching process can make the etching rate of silicon material on substrate 200 less than the etching rate of silicon oxide material on buffer layer 201, which is more conducive to controlling the morphology of initial isolation trench 204.

[0053] Next, step S103 is performed: a second etching process is performed on the bottom of the buffer trench 203 to form an initial isolation trench 204 on the substrate 200; wherein the opening of the initial isolation trench 204 that connects with the buffer trench 203 is a smooth chamfered configuration.

[0054] Furthermore, the etching gases used in the second etching process include isotropic etching gases and anisotropic etching gases.

[0055] Furthermore, isotropic etching gases include, but are not limited to, one or more of SF6, CH2F2, and C4F8.

[0056] Furthermore, the anisotropic etching gases include, but are not limited to, one or both of Cl2 and HBr.

[0057] Furthermore, the gases used in the second etching process include: Cl2, CH2F2, O2, and HBr; the etching conditions for the second etching process include: a Cl2 flow rate of 50 sccm to 100 sccm; a CH2F2 flow rate of 0 sccm to 60 sccm; a O2 flow rate of 0 to 10 sccm; a HBr flow rate of 0 to 40 sccm; and an etching time of 10 s to 30 s; the electric field parameters for the second etching process include: a reaction pressure of 20 mtorr to 50 mtorr; and a bias power of 200 W to 400 W for the reaction chamber.

[0058] Specifically, in this embodiment of the invention, a second etching process is performed at the bottom of the buffer trench 203, and a substrate 200 is formed at the bottom of the buffer trench 203. Figure 7 The initial isolation trench 204 is shown. The etching gases used in the second etching process include isotropic and anisotropic etching gases. The introduction of an isotropic etching gas in the second etching process allows for the smoothing of exposed corners during the formation of the initial isolation trench 204, resulting in a smooth chamfer. This improves the integrity and thickness uniformity of the gate oxide layer formed on the initial isolation trench 204, enhancing the performance reliability of the semiconductor structure. The introduction of anisotropic etching gas in the second etching process enables the etching of the substrate 200 along a direction perpendicular to the surface of the substrate 200. By combining isotropic and anisotropic etching gases and adjusting the etching parameters, a smooth chamfer configuration can be formed near the opening of the buffer trench 203 in the initial isolation trench 204. The depth of the initial isolation trench 204 is positively correlated with the time of the second etching process. The second etching process also introduces a protective gas, including O2, N2 or He, to protect the substrate 200 of the initial isolation trench 204 sidewalls during the second etching process.

[0059] In this embodiment, the etching gas and process parameters of the second etching process are set such that the etching rate of silicon material on substrate 200 is greater than the etching rate of silicon oxide material on buffer layer 201, so as to avoid excessive wear of buffer layer 201 during the second etching process.

[0060] Next, step S104 is performed: a third etching process is performed on the bottom of the initial isolation trench 204 to deepen the depth of the initial isolation trench 204, and an isolation trench 205 is formed on the substrate 200.

[0061] Furthermore, the etching gas used in the third etching process includes anisotropic etching gases.

[0062] Furthermore, the anisotropic etching gases include, but are not limited to, one or both of Cl2 and HBr.

[0063] Furthermore, the gases used in the third etching process include Cl2, O2, and HBr; the etching conditions for the third etching process include: O2 flow rate between 0 and 10 sccm; Cl2 flow rate between 50 and 200 sccm; HBr flow rate between 20 and 100 sccm; etching time between 40 and 60 seconds; reaction pressure between 5 and 20 mtorr; and bias power of the reaction chamber between 100 W and 400 W.

[0064] Specifically, in this embodiment of the invention, after forming the initial isolation trench 204, a third etching process is performed on the bottom of the initial isolation trench 204 to deepen the initial isolation trench 204 and form... Figure 8 The isolation trench 205 shown.

[0065] The third etching process uses an anisotropic etching gas. This third etching process is used to form isolation trenches 205 with a high aspect ratio. The use of anisotropic etching is beneficial for forming isolation trenches 205 with a high aspect ratio. A protective gas, including O2, is also used in the third etching process. The protective gas is used to protect the substrate 200 exposed on the sidewalls of the isolation trenches 205 during the third etching process.

[0066] Finally, step S105 is executed: the isolation trench 205 is filled to form a shallow trench isolation 206.

[0067] Specifically, in this embodiment of the invention, after the isolation trench 205 is formed, a medium material can be directly filled into the isolation trench 205 to form... Figure 9 The shallow trench isolation 206 shown is an example. It eliminates the need to form a linear layer on the surface of the isolation trench 205 and then form the isolation structure 206 on the linear layer, simplifying the process flow.

[0068] A second aspect of the present invention provides a semiconductor device comprising a shallow trench isolation formed by the shallow trench isolation formation method described above.

[0069] A third aspect of the present invention provides a chip comprising the semiconductor device described above.

[0070] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0071] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0072] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A method for forming a shallow trench isolation, characterized in that, The shallow trench isolation formation method includes: A substrate is provided, and a buffer layer and a stop layer having an etching window are sequentially formed on the upper surface of the substrate; wherein the etching window can expose the buffer layer; The buffer layer is first etched through an etching window to form a buffer trench in the buffer layer; wherein the wall of the buffer trench is a concave arc-shaped configuration; the buffer trench can expose the substrate; the angle between the bottom wall of the buffer trench and the substrate is greater than 90°, thereby exposing the opening of the initial isolation trench to be formed. The bottom of the buffer trench is subjected to a second etching process to form an initial isolation trench on the substrate; wherein the opening of the initial isolation trench and the buffer trench is a smooth chamfered configuration. A third etching process is performed on the bottom of the initial isolation trench to deepen the initial isolation trench and form an isolation trench on the substrate; The isolation trench is filled to form a shallow trench isolation.

2. The shallow trench isolation forming method according to claim 1, characterized in that, The etching gases used in the first etching process include isotropic etching gases and anisotropic etching gases.

3. The shallow trench isolation forming method according to claim 1, characterized in that, The etching gases used in the second etching process include isotropic etching gases and anisotropic etching gases.

4. The shallow trench isolation forming method according to claim 2 or 3, characterized in that, Isotropic etching gases include, but are not limited to, one or more of SF6, CH2F2 and C4F8.

5. The shallow trench isolation forming method according to claim 1, characterized in that, The etching gas used in the third etching process includes anisotropic etching gas.

6. The shallow trench isolation forming method according to claim 2, 3 or 5, characterized in that, Anisotropic etching gases include, but are not limited to, one or both of Cl2 and HBr.

7. The shallow trench isolation forming method according to claim 1, characterized in that, The gases used in the first etching process include: CH2F2, SF6, and HBr; The etching conditions for the first etching process include: CH2F2 flow rate between 0 and 60 sccm; SF6 flow rate between 0 and 60 sccm; HBr flow rate between 0 and 40 sccm; etching time between 20 and 40 seconds; reaction pressure between 5 mtorr and 20 mtorr; and bias power of the reaction chamber between 100 W and 400 W.

8. The shallow trench isolation forming method according to claim 1, characterized in that, The gases used in the second etching process include: Cl2, CH2F2, O2, and HBr; The etching conditions for the second etching process include: a Cl2 flow rate of 50 sccm to 100 sccm; a CH2F2 flow rate of 0 sccm to 60 sccm; an O2 flow rate of 0 to 10 sccm; a HBr flow rate of 0 to 40 sccm; and an etching time of 10 s to 30 s. The electric field parameters for the second etching process include: a reaction pressure of 20 mtorr to 50 mtorr; and a bias power of 200 W to 400 W for the reaction chamber.

9. The shallow trench isolation forming method according to claim 1, characterized in that, The gases used in the third etching process include: Cl2, O2, and HBr; The etching conditions for the third etching process include: O2 flow rate between 0 and 10 sccm; Cl2 flow rate between 50 and 200 sccm; HBr flow rate between 20 and 100 sccm; etching time between 40 and 60 seconds; reaction pressure between 5 and 20 mtorr; and bias power of the reaction chamber between 100 W and 400 W.

10. The shallow trench isolation forming method according to claim 1, characterized in that, The thickness of the buffer layer is between 400 Å and 600 Å.

11. A semiconductor device, characterized in that, The semiconductor device includes a shallow trench isolation formed using the shallow trench isolation formation method according to any one of claims 1-10.

12. A chip, characterized in that, The chip includes the semiconductor device as described in claim 11.

Images