Semiconductor structure manufacturing method and semiconductor structure
In the manufacturing process of semiconductor structures, the contact hole is formed by using self-aligning columns as mask etching, which solves the problem of offsetting the pattern registration accuracy of the contact photomask hole mask pattern under small line width, and achieves high-precision contact hole formation and reduces production costs.
Patent Information
- Application Number
- CN202411850705.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-04-08
AI Technical Summary
With a small line width, the mesa between adjacent gate trench structures is narrow, resulting in a deviation in the registration accuracy of the contact mask hole mask pattern, resulting in discrete parameters such as product threshold voltage (VTH) and on-resistance (Ron).
Using a semiconductor structure manufacturing method, by etching the gate trench on the substrate, forming a gate structure and an interlayer dielectric layer, and forming a self-aligning column in the interlayer dielectric layer, the contact hole is etched using the self-aligning column as a mask.
The contact hole can be etched without the assistance of the mask mask version, avoiding the alignment accuracy problems caused by the body engraving error of the mask mask version and reducing production costs.
Smart Images
Figure CN119786434A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art
[0002] At present, the cell region structure of a general trench-type power MOS transistor includes a gate trench structure and a contact hole structure. After the gate trench structure is formed, a contact hole is formed by etching the area between two adjacent gate trenches, and then a conductive material is filled in the contact hole to form the contact hole structure.
[0003] As the requirements for product performance increase, product line widths are shrinking, and the demand for process accuracy is also increasing, especially under small line widths. Because the table between adjacent gate trench structures is compressed very narrow, the registration accuracy deviation of the contact mask hole mask pattern will cause discrete parameters such as product threshold voltage (VTH) and on-resistance (Ron). Summary of the invention
[0004] An object of the present invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure to solve one or more problems in the prior art.
[0005] In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, comprising:
[0006] Providing a substrate, the substrate comprising a substrate and an epitaxial layer formed on the substrate, etching the epitaxial layer to form at least two gate trenches arranged at intervals;
[0007] forming a gate structure, the gate structure comprising a gate oxide layer and a gate conductive material layer, the gate oxide layer covers the bottom wall and the side wall of the gate trench, the gate conductive material layer fills the gate trench, and the upper surface of the gate conductive material layer is lower than the upper surface of the epitaxial layer;
[0008] forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the gate conductive material layer and extends to cover the gate oxide layer and the upper surface of the epitaxial layer, and the area surrounded by the interlayer dielectric layer constitutes an alignment groove;
[0009] forming a self-alignment column, wherein the self-alignment column is filled in the alignment groove, and the upper surface of the self-alignment column is higher than the upper surface of the epitaxial layer; and,
[0010] Using the self-aligned pillar as a mask, the interlayer dielectric layer and the epitaxial layer between two adjacent gate trenches are etched in sequence to form a contact hole, and the self-aligned pillar is removed.
[0011] Optionally, in the method for manufacturing the semiconductor structure, an upper surface of the self-alignment pillar is flush with an upper surface of the interlayer dielectric layer.
[0012] Optionally, in the method for manufacturing the semiconductor structure, when forming the contact hole, the epitaxial layer is etched using a first etching process, and the self-alignment column is made of a material that can be etched and removed by the first etching process.
[0013] Optionally, in the method for manufacturing the semiconductor structure, the material of the epitaxial layer includes silicon, and the material of the self-aligned pillar includes polysilicon.
[0014] Optionally, in the method for manufacturing the semiconductor structure, the method further comprises:
[0015] Performing ion implantation on the epitaxial layer to form a body region and a source region in the epitaxial layer, wherein the body region and the source region are located between two adjacent gate trenches, and the source region is located above the body region;
[0016] The bottom of the contact hole extends into the body region.
[0017] Optionally, in the method for manufacturing the semiconductor structure, the step of performing ion implantation to form the body region and the source region is performed after forming the self-aligned pillar;
[0018] After forming the self-aligned pillars and before performing ion implantation, the manufacturing method includes:
[0019] Thinning the interlayer dielectric layer on the epitaxial layer to a target thickness;
[0020] After the ion implantation, the manufacturing method includes: increasing the thickness of the interlayer dielectric layer until the upper surface of the interlayer dielectric layer is flush with the upper surface of the self-aligned pillar.
[0021] Optionally, in the method for manufacturing the semiconductor structure, the step of thinning the thickness of the interlayer dielectric layer on the epitaxial layer includes:
[0022] removing the interlayer dielectric layer on the epitaxial layer, and,
[0023] A shielding oxide layer having the target thickness is formed on the epitaxial layer.
[0024] Optionally, in the method for manufacturing the semiconductor structure, the target thickness is
[0025] Optionally, in the method for manufacturing the semiconductor structure, a height difference between an upper surface of the gate conductive material layer and an upper surface of the epitaxial layer is 0.3 μm to 0.4 μm.
[0026] The present invention also provides a semiconductor structure, which is manufactured using the manufacturing method as described in any of the preceding items.
[0027] In summary, the manufacturing method of the semiconductor structure provided by the present invention includes: providing a substrate, the substrate including a substrate and an epitaxial layer formed on the substrate, etching the epitaxial layer to form at least two gate trenches arranged at intervals; forming a gate structure, the gate structure including a gate oxide layer and a gate conductive material layer, the gate oxide layer covers the bottom wall and side walls of the gate trench, the gate conductive material layer is filled in the gate trench, and the upper surface of the gate conductive material layer is lower than the upper surface of the epitaxial layer; forming an interlayer dielectric layer, the interlayer dielectric layer covers the gate conductive material layer and extends to cover the upper surfaces of the gate oxide layer and the epitaxial layer, and the area surrounded by the interlayer dielectric layer constitutes an alignment groove; forming a self-alignment column, the self-alignment column is filled in the alignment groove, and the upper surface of the self-alignment column is higher than the upper surface of the epitaxial layer; and, using the self-alignment column as a mask, sequentially etching the interlayer dielectric layer and the epitaxial layer between two adjacent gate trenches to form a contact hole, and removing the self-alignment column. Compared with the prior art, the manufacturing method provided by the present invention has the following advantages:
[0028] (1) By utilizing the manufacturing method provided by the present invention, contact holes can be formed by etching without the assistance of a photomask mask, thereby avoiding the problem of alignment accuracy caused by the overlay error of the photomask mask itself. In addition, by eliminating the use of a photomask mask, production costs can also be reduced.
[0029] (2) Compared with the prior art, the manufacturing method provided by the present invention only needs to increase the etching depth of the gate trench and add the step of forming a self-aligned column. The formed self-aligned column can be removed simultaneously in the step of etching the epitaxial layer to form a contact hole. The process flow is simple and will not affect the execution of other conventional steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;
[0031] Figure 2 to Figure 8 for Figure 1 Schematic diagram of device structure corresponding to each step in the figure;
[0032] The descriptions of the reference numerals are as follows:
[0033] 10-substrate; 20-epitaxial layer; 30-gate trench; 31-gate oxide layer; 32-gate conductive material layer; 40-interlayer dielectric layer; 41-first interlayer dielectric layer; 42-shielding oxide layer; 43-second interlayer dielectric layer; 50-self-aligning pillar; 51-aligning groove; 61-body region; 62-source region; 71-first through hole; 72-second through hole. DETAILED DESCRIPTION
[0034] The following is a further detailed description of the manufacturing method and semiconductor structure of the semiconductor structure proposed by the present invention in conjunction with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0035] See also Figure 1 This embodiment provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0036] S1, providing a substrate, wherein the substrate includes a substrate and an epitaxial layer formed on the substrate, and etching the epitaxial layer to form at least two gate trenches arranged at intervals;
[0037] S2, forming a gate structure, wherein the gate structure includes a gate oxide layer and a gate conductive material layer, wherein the gate oxide layer covers the bottom wall and the side wall of the gate trench, the gate conductive material layer fills the gate trench, and the upper surface of the gate conductive material layer is lower than the upper surface of the epitaxial layer;
[0038] S3, forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the gate conductive material layer and extends to cover the gate oxide layer and the upper surface of the epitaxial layer, and the area surrounded by the interlayer dielectric layer constitutes an alignment trench;
[0039] S4, forming a self-alignment column, wherein the self-alignment column is filled in the alignment groove, and the upper surface of the self-alignment column is higher than the upper surface of the epitaxial layer;
[0040] S5, using the self-aligned pillar as a mask, sequentially etching the interlayer dielectric layer and the epitaxial layer between two adjacent gate trenches to form a contact hole, and removing the self-aligned pillar.
[0041] The manufacturing method provided in this embodiment uses the self-aligned pillars aligned with the gate trenches as a mask for etching the area between two adjacent gate trenches to form a contact hole. In this way, the contact hole can be etched without the assistance of a photomask mask, thereby avoiding the problem of alignment accuracy caused by the overlay error of the photomask mask itself. In addition, the production cost can be reduced by eliminating the use of a photomask mask. In addition, compared with the prior art, the manufacturing method provided by the present invention only needs to increase the etching depth of the gate trench and increase the step of forming the self-aligned pillars. The formed self-aligned pillars can be removed simultaneously in the step of etching the epitaxial layer to form the contact hole. The process flow is simple and will not affect the execution of other conventional steps.
[0042] The following combination Figure 2 to Figure 8 The above steps are further described.
[0043] First, execute step S1, see Figure 2 , providing a substrate, the substrate comprising a substrate 10 and an epitaxial layer 20 formed on the substrate 10, and etching the epitaxial layer 20 to form at least two gate trenches 30 arranged at intervals.
[0044] It can be understood that, generally, when the number of the gate trenches 30 is at least two, at least two of the gate trenches 30 are arranged at intervals along a horizontal direction parallel to the epitaxial layer 20 .
[0045] The substrate 10 may be any suitable substrate known to those skilled in the art. In the present embodiment, as an example, the substrate 10 may be a silicon substrate. The material of the epitaxial layer 20 may be the same as or different from the material of the substrate 10. As an example, in the present embodiment, the epitaxial layer 20 may be a silicon epitaxial layer. In other embodiments, the epitaxial layer 20 may also be a silicon carbide epitaxial layer, etc.
[0046] Next, execute step S2. Please refer to Figure 2, forming a gate structure, the gate structure includes a gate oxide layer 31 and a gate conductive material layer 32, the gate oxide layer 31 covers the bottom wall and side walls of the gate trench 30, the gate conductive material layer 32 is filled in the gate trench 30, and the upper surface of the gate conductive material layer 32 is lower than the upper surface of the epitaxial layer 20, that is, the filling height of the gate conductive material layer 32 in the gate trench 30 is less than the depth of the gate trench 30.
[0047] The gate oxide layer 31 can be formed by a furnace tube wet oxidation process or a rapid thermal oxidation process, and the present application does not limit this. Optionally, the gate oxide layer 31 covers not only the bottom wall and the side wall of the gate trench 30, but also the surface of the substrate. Optionally, the gate conductive material layer 32 is made of polysilicon.
[0048] In the conventional process for forming a gate structure, the gate conductive material layer fills the gate trench, that is, after the gate conductive material layer is filled in the gate trench, the surface of the gate conductive material layer is flush with the top of the gate trench. In the method provided in this embodiment, the etching depth when etching to form the gate trench 30 is greater than the etching depth when the gate trench is conventionally formed. Therefore, after the gate conductive material layer 32 is filled in the gate trench 30, the filling height of the gate conductive material layer 32 in the gate trench 30 is less than the depth of the gate trench 30. Preferably, the etching depth of the gate trench 30 is 0.3μm to 0.4μm deeper than the depth of the conventional gate trench 30, so that the height difference H between the upper surface of the gate conductive material layer 32 and the upper surface of the epitaxial layer 20 is 0.3μm to 0.4μm, and the height difference H determines the height of the portion of the self-aligned column formed in the subsequent step that is exposed outside the substrate.
[0049] Next, execute step S3, see Figure 3 , forming an interlayer dielectric layer 40, wherein the interlayer dielectric layer 40 covers the gate conductive material layer 32 and extends to cover the surface of the epitaxial layer 20, and the area surrounded by the interlayer dielectric layer 40 constitutes an alignment groove 51; and performing step S4, see Figure 4 , forming a self-alignment column 50 , wherein the self-alignment column 50 fills the alignment groove 51 , and the upper surface of the self-alignment column 50 is higher than the upper surface of the epitaxial layer 20 .
[0050] When the contact hole is formed in the subsequent step, the epitaxial layer 20 is etched by the first etching process. Preferably, the self-aligning pillar 50 is made of a material that can be removed by the first etching process. In this way, in the subsequent step, when the epitaxial layer 20 is etched, the self-aligning pillar 50 will also be removed. For example, if the epitaxial layer 20 is made of silicon, the self-aligning pillar 50 can be made of polysilicon. The material of the self-aligning pillar 50 can be adaptively adjusted according to the change of the material of the epitaxial layer 20.
[0051] Preferably, the upper surface of the self-aligning pillar 50 is flush with the upper surface of the interlayer dielectric layer 40. The step of forming the self-aligning pillar 50 may include: filling the alignment groove 51 with polysilicon material until the polysilicon material covers the surface of the alignment groove 51, and then etching back the polysilicon material until its upper surface is flush with the upper surface of the interlayer dielectric layer 40. The upper surface of the self-aligning pillar 50 is flush with the upper surface of the interlayer dielectric layer 40, which is helpful for self-alignment when forming contact holes later.
[0052] In some other embodiments, the interlayer dielectric layer 40 may be thinned so that the upper surface of the self-alignment pillar 50 is flush with the upper surface of the interlayer dielectric layer 40 .
[0053] See also Figure 5 The manufacturing method provided in this embodiment also includes: performing ion implantation on the epitaxial layer 20 to form a body region 61 and a source region 62 in the epitaxial layer 20 , wherein the body region 61 and the source region 62 are located between two adjacent gate trenches 30 , and the source region 62 is located above the body region 61 .
[0054] As an example, the substrate 10 is an N+ type substrate, the epitaxial layer 20 is an N− type epitaxial layer, the body region 61 is a P well region, and the source region 62 is an N+ region.
[0055] Optionally, the step of performing ion implantation to form the body region 61 and the source region 62 is performed after forming the self-aligned pillar 50; the thickness of the interlayer dielectric layer 40 affects the depth of ion implantation, therefore, after forming the self-aligned pillar 50 and before performing ion implantation, the manufacturing method includes: thinning the thickness of the interlayer dielectric layer 40 on the epitaxial layer 20 to a target thickness. Optionally, the target thickness is
[0056] In this embodiment, preferably, the step of thinning the thickness of the interlayer dielectric layer 40 on the epitaxial layer 20 includes: removing the interlayer dielectric layer 40 on the epitaxial layer 20, and forming a shielding oxide layer 42 of the target thickness on the epitaxial layer 20, that is, the thickness of the shielding oxide layer 42 is It can be understood that the formed shielding oxide layer 42 is used for ion implantation and can also serve as an interlayer dielectric layer. In some other embodiments, the purpose of thinning can be achieved by directly removing a portion of the thickness of the interlayer dielectric layer 40, but the thickness of the interlayer dielectric layer 40 to be directly removed is limited to 100%. The thickness uniformity and quality of the oxide layer above the ion implantation area are poor, but by removing all of it and then growing it, the thickness uniformity and quality are better, making the ion implantation more stable.
[0057] In addition, after the ion implantation is completed, the manufacturing method provided in this embodiment further includes: increasing the thickness of the interlayer dielectric layer 40 to the upper surface of the interlayer dielectric layer 40 and the upper surface of the self-aligned pillar 50. In this way, in the subsequent steps, the self-aligned pillar 50 is used as a mask for etching to form a contact hole.
[0058] In combination with the above description, it can be seen that in this embodiment, the interlayer dielectric layer 40 is not formed by a single process step. In summary, see Figure 6 The formation process of the interlayer dielectric layer 10 includes: first forming a first interlayer dielectric layer 41, the first interlayer dielectric layer 41 covers the gate conductive material layer 32 and extends to cover the surface of the epitaxial layer 20, and then removing the first interlayer dielectric layer 40 on the surface of the epitaxial layer 20 and forming the shielding oxide layer 42 on the surface of the epitaxial layer 20. After the ion implantation is completed, a second interlayer dielectric layer 43 is formed on the surface of the shielding oxide layer 42. Thus, the first interlayer dielectric layer 41, the shielding oxide layer 42 and the second interlayer dielectric layer 43 together constitute the dielectric layer 20.
[0059] Among them, the first interlayer dielectric layer 41 can be formed by a plasma chemical vapor deposition process to form the interlayer dielectric layer 40. In some other embodiments, it can also be formed by other processes, such as chemical vapor deposition process, etc.; the second interlayer dielectric layer 41 can be formed by a chemical vapor deposition process. In some other embodiments, it can also be formed by physical vapor deposition and other processes; the shielding oxide layer 42 can be formed by a thermal oxidation process. In some other embodiments, it can also be formed by chemical vapor deposition process, physical vapor deposition and other processes.
[0060] In some other embodiments, the step of forming the body region 61 and the source region 62 by ion implantation can also be performed before etching the epitaxial layer 20 to form the gate trench 30. In this way, there is no need to thin the interlayer dielectric layer 40 and then increase its thickness, that is, the first interlayer dielectric layer 41 constitutes the interlayer dielectric layer 40.
[0061] Finally, step S5 is performed to sequentially etch the interlayer dielectric layer 40 and the epitaxial layer 20 between two adjacent gate trenches 30 using the self-aligned pillars 50 as masks to form contact holes, and remove the self-aligned pillars 50 .
[0062] The bottom of the contact hole is located in the body region 61 . Thus, after the contact hole is filled with a conductive material to form a conductive plug, the conductive plug penetrates the source region 62 and the bottom is electrically connected to the body region 61 .
[0063] See also Figure 7 and Figure 8 , the interlayer dielectric layer 40 may be first etched with an etchant having a relatively high etching rate for the interlayer dielectric layer 40 to form a first through hole 71, and then the epitaxial layer 20 may be etched with an etchant having a relatively high etching rate for the epitaxial layer 20 to form a second through hole 72, wherein the first through hole 71 and the second through hole 72 together constitute the contact hole. When the epitaxial layer 20 is etched to form the second through hole 72, the self-aligned pillar 50 is also etched away simultaneously.
[0064] Among them, when etching the interlayer dielectric layer 40 to form the first through hole 71, a gas containing C, H, and F elements can be used, and combined with O2, Ar, He, etc., so that the aperture of the first through hole 71 decreases from top to bottom and its cross-sectional shape is an inverted trapezoid. In this way, it can be avoided that when etching with the self-alignment column 50 as a mask to form the first through hole 71, the gate oxide layer 31 is etched or even pierced, which causes conduction abnormality between the conductive plug filled in the through hole and the gate conductive material layer 32.
[0065] In addition, this embodiment also provides a semiconductor structure, and the semiconductor structure is manufactured using the manufacturing method provided by this embodiment.
[0066] Optionally, the semiconductor structure described in this embodiment may be a MOS device such as a trench MOS field effect transistor (Trench MOS), a shielded gate field effect transistor (SGT MOS), etc., but the application is not limited to this. Any semiconductor device that requires a contact hole structure to be formed between two adjacent gate trenches is within the protection scope of this application.
[0067] In summary, the manufacturing method of the semiconductor structure provided by the embodiment of the present invention includes: providing a substrate, the substrate including a substrate and an epitaxial layer formed on the substrate, etching the epitaxial layer to form at least two gate trenches arranged at intervals; forming a gate structure, the gate structure including a gate oxide layer and a gate conductive material layer, the gate oxide layer covers the bottom wall and the side wall of the gate trench, the gate conductive material layer is filled in the gate trench, and the upper surface of the gate conductive material layer is lower than the upper surface of the epitaxial layer; forming an interlayer dielectric layer, the interlayer dielectric layer covers the gate conductive material layer and extends to cover the upper surface of the gate oxide layer and the epitaxial layer, and the area surrounded by the interlayer dielectric layer constitutes an alignment groove; forming a self-alignment column, the self-alignment column is filled in the alignment groove, and the upper surface of the self-alignment column is higher than the upper surface of the epitaxial layer; and, using the self-alignment column as a mask, sequentially etching the interlayer dielectric layer and the epitaxial layer between two adjacent gate trenches to form a contact hole, and removing the self-alignment column. By using the manufacturing method provided by the present invention, contact holes can be etched without the assistance of a photomask mask, thereby avoiding the problem of alignment accuracy caused by the overlay error of the photomask mask itself. In addition, the production cost can be reduced by eliminating the use of a photomask mask. In addition, compared with the prior art, the manufacturing method provided by the embodiment of the present invention only needs to increase the etching depth of the gate trench and add the step of forming a self-aligning column. The formed self-aligning column can be removed simultaneously in the step of etching the epitaxial layer to form the contact hole. The process flow is simple and will not affect the execution of other conventional steps.
[0068] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and an epitaxial layer formed on the substrate, etching the epitaxial layer to form at least two gate trenches arranged at intervals; forming a gate structure, the gate structure comprising a gate oxide layer and a gate conductive material layer, the gate oxide layer covers the bottom wall and the side wall of the gate trench, the gate conductive material layer fills the gate trench, and the upper surface of the gate conductive material layer is lower than the upper surface of the epitaxial layer; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the gate conductive material layer and extends to cover the gate oxide layer and the upper surface of the epitaxial layer, and the area surrounded by the interlayer dielectric layer constitutes an alignment groove; forming a self-alignment column, wherein the self-alignment column is filled in the alignment groove, and the upper surface of the self-alignment column is higher than the upper surface of the epitaxial layer; as well as, Using the self-aligned pillar as a mask, the interlayer dielectric layer and the epitaxial layer between two adjacent gate trenches are etched in sequence to form a contact hole, and the self-aligned pillar is removed.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The upper surface of the self-aligned pillar is flush with the upper surface of the interlayer dielectric layer.
3. The method for manufacturing a semiconductor structure according to claim 1, wherein: When forming the contact hole, the epitaxial layer is etched by a first etching process, and the self-alignment pillar is made of a material that can be removed by the first etching process.
4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The material of the epitaxial layer includes silicon, and the material of the self-aligned pillar includes polysilicon.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The manufacturing method further comprises: Performing ion implantation on the epitaxial layer to form a body region and a source region in the epitaxial layer, wherein the body region and the source region are located between two adjacent gate trenches, and the source region is located above the body region; The bottom of the contact hole extends into the body region.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The step of performing ion implantation to form the body region and the source region is performed after forming the self-aligned pillar; After forming the self-aligned pillars and before performing ion implantation, the manufacturing method includes: Thinning the interlayer dielectric layer on the epitaxial layer to a target thickness; After the ion implantation, the manufacturing method includes: increasing the thickness of the interlayer dielectric layer until the upper surface of the interlayer dielectric layer is flush with the upper surface of the self-aligned pillar.
7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The step of reducing the thickness of the interlayer dielectric layer on the epitaxial layer comprises: removing the interlayer dielectric layer on the epitaxial layer, and, A shielding oxide layer having the target thickness is formed on the epitaxial layer.
8. The method for manufacturing a semiconductor structure according to claim 6 or 7, characterized in that: The target thickness is 9. The method for manufacturing a semiconductor structure according to claim 1, wherein: A height difference between an upper surface of the gate conductive material layer and an upper surface of the epitaxial layer is 0.3 μm to 0.4 μm.
10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured using the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.