Flat packaging device with flat pins and manufacturing method thereof
By using a fully covered sealing layer and pre-cutting method to form gaps in the packaging device, the problems of high equipment costs and accumulated pin stress in the prior art are solved, and the effect of reducing production costs and improving product reliability is achieved.
Patent Information
- Application Number
- CN202311290772.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-08
- Publication Date
- 2025-04-08
AI Technical Summary
During the production process of existing packaging devices, different equipment and molds are needed to make packaging devices of different specifications, resulting in high equipment costs and easy accumulation of stress on the pins, affecting reliability.
A flat-type packaging device with flat pins is adopted, and its sealing layer is fully covered on the wire frame and voids are formed by pre-cutting to reduce machining steps.
It reduces equipment costs, reduces residual glue and overflow problems, reduces stress accumulation on the joints, and improves product reliability.
Smart Images
Figure CN119786478A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a flat package device, and more particularly to a flat package device with flat pins extending outward. Background Art
[0002] Existing packaged devices mainly go through die attaching, wire bonding, molding, trimming and forming steps to obtain independent packaged devices. Figure 8 As shown, steps such as die bonding, wire bonding, and sealing have been completed on a lead frame 81 , and a plurality of packaged devices 82 have been manufactured on the lead frame 81 .
[0003] Please refer to Fig. 9 As shown, after the sealing is completed, the lead frame 81 is punched to obtain a plurality of independent packaged devices 82, each of which has a pin 83 extending outward on the side. Fig.10 As shown, each pin 83 is bent and formed so that each pin 83 has a specific bending shape, such as L-shape, J-shape, etc. However, the above-mentioned existing packaging method has the following disadvantages:
[0004] Different specifications of packaged devices require different equipment or molds to complete the production. For example, when performing the encapsulation process on each chip on the lead frame, it is necessary to use a specific mold equipment to cover the position of each chip with encapsulation material; for packaged devices of different specifications, the number, size or position of the chips may change, and the corresponding encapsulation mold equipment may need to be replaced; after demolding, each packaged device may have problems with overflow and residual glue, and an additional step is required for appearance trimming.
[0005] When punching the lead frame and bending the pins, different machines are required to complete each process step; the equipment cost is relatively expensive.
[0006] The pins of each packaged device need to go through multiple machining steps such as punching, bending and forming, which easily accumulates a lot of stress on the pins, causing the pins to malfunction. Summary of the invention
[0007] In view of the above problems in the prior art, the main purpose of the present invention is to provide a "flat package device with flat pins and a manufacturing method thereof" to reduce production costs and improve product reliability.
[0008] To achieve the above-mentioned object, the flat package device with flat pins proposed in the present invention comprises:
[0009] One crystal pad;
[0010] A chip is disposed on the surface of the wafer pad;
[0011] A plurality of pins are distributed around the die pad and are electrically connected to the chip respectively; and
[0012] A sealing layer covers the crystal pad, a part of the plurality of pins and the chip, the sealing layer has a top surface, a bottom surface and four side surfaces, wherein each of the side surfaces is a plane and is perpendicular to the top surface, and each of the plurality of pins extends horizontally and straightly outward from the side surface of the sealing layer without bending.
[0013] The method for manufacturing a flat package device with flat pins proposed by the present invention comprises:
[0014] Prepare a semi-finished substrate, the semi-finished substrate includes a lead frame, the lead frame has a plurality of crystal pads and pins, wherein at least one chip is disposed on the surface of each crystal pad, and the chip is electrically connected to the corresponding pin;
[0015] The surface of the lead frame is completely covered with a sealing layer, the sealing layer covers the lead frame, the plurality of chips and the connector, and the surface of the sealing layer is a plane;
[0016] Performing a pre-cutting operation on the sealing layer to form a plurality of pre-cutting lanes on the surface of the sealing layer, wherein the extension direction of the plurality of pre-cutting lanes is perpendicular to the extension direction of the plurality of pins, and each of the pre-cutting lanes extends from the surface of the sealing layer to the surface of each pin;
[0017] In each pre-cutting lane, the sealing glue layer filled between adjacent pins is removed to form a gap between adjacent pins; and
[0018] The semi-finished substrate is completely cut to obtain a plurality of independently separated packaged devices.
[0019] The present invention does not require specific sealing, lead frame punching, and pin bending, which can reduce equipment costs, and the sealing layer fully covers the lead frame, which can relatively reduce the problems of residual glue and overflowing glue; in the processing of each pin, the problem of excessive stress accumulation on the pin caused by existing mechanical stamping and pin bending operations is reduced, which can improve the reliability of the structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1A : A schematic cross-sectional view of a semi-finished substrate of the present invention.
[0021] Figure 1B : Schematic diagram of the appearance of the semi-finished substrate of the present invention.
[0022] Figure 2A: A cross-sectional schematic diagram of the present invention performing pre-cutting on the semi-finished substrate.
[0023] Figure 2B : Schematic diagram of the appearance of pre-cutting the semi-finished substrate of the present invention.
[0024] Figure 2C : Figure 2B A partial enlarged schematic diagram of .
[0025] Figure 3A : A schematic diagram of the appearance of the present invention performing pre-cutting on the semi-finished substrate along the staggered direction.
[0026] Figure 3B : Figure 3A A partial enlarged schematic diagram of .
[0027] Figure 4 : Schematic diagram of the appearance of removing the sealant from the pre-cutting path of the present invention.
[0028] Figure 5 : A schematic diagram of the present invention covering a mask layer on the surface of the sealing layer and removing the sealing layer by plasma etching.
[0029] Figure 6 : Schematic diagram of the operation of completely cutting a semi-finished substrate according to the present invention.
[0030] Fig. 7A : A three-dimensional appearance diagram of an embodiment of a packaging device of the present invention.
[0031] Figure 7B : A bottom-up stereoscopic view of an embodiment of a packaging device of the present invention.
[0032] Figure 7C : A cross-sectional view of an embodiment of a packaging device of the present invention.
[0033] Figure 8 : A three-dimensional schematic diagram of a lead frame after the sealing step is completed according to the existing packaging method.
[0034] Fig. 9 :right Figure 8 The lead frame is cut to obtain multiple packaged devices.
[0035] Fig.10 :right Fig. 9 The appearance of the packaged device after the pins are bent and formed. DETAILED DESCRIPTION
[0036] Please refer to Figure 1A and Figure 1BAs shown, the present invention first prepares a semi-finished substrate 100, which is mainly made through the steps of die attaching, wire bonding, molding, etc. to form a plurality of semi-finished packaged devices. The structure of the semi-finished substrate 100 includes a lead frame 10, which has a plurality of integrally formed die pads 11 and pins 12, wherein the plurality of die pads 11 are arranged in regular rows and columns, and a plurality of pins 12 are arranged around each die pad 11. Each packaged device has one or more die pads 11 inside, and at least one chip 20 is respectively arranged on the surface of each die pad 11, and each chip 20 is electrically connected to the corresponding pin 12 through a connector 30, and the structural type of the plurality of connectors 30 is not limited, for example, the connector 30 can be a metal wire, a conductive sheet, or other electrically conductive components.
[0037] The surface of the lead frame 10 is covered with a sealing layer 40, and the thickness of the sealing layer 40 is sufficient to cover the lead frame 10, the chip 20 and the connector 30; different from the existing sealing method, the present invention does not seal the pads and chips of individual packaged devices, but comprehensively covers the lead frame 10 with the sealing layer 40, and the surface of each pin 12 is covered with the sealing layer 40. After the covering is completed, the surface of the sealing layer 40 is a plane.
[0038] Please refer to Figure 2A to Figure 2C As shown, the present invention performs a pre-cutting operation on the sealing layer 40 of the semi-finished substrate 100, and forms a plurality of pre-cutting paths 41 on the surface of the sealing layer 40, wherein the extension direction of the plurality of pre-cutting paths 41 is perpendicular to the extension direction of the lead 12. Figure 2B In the embodiment, the pins 12 of each packaged device extend in the direction of ±Y axis along the opposite sides of the packaged device, and the pre-cutting road 41 is formed on the sealing layer 40 along the direction of X axis; each pre-cutting road 41 extends downward from the surface of the sealing layer 40 to the surface of the pins 12, and the surface of each pin 12 can be exposed in each pre-cutting road 41, but each pin 12 is not cut off. When performing the pre-cutting operation, a blade can be used for mechanical cutting; or a laser beam can be used to cut the surface of the sealing layer 40.
[0039] Please refer to Figure 3A to Figure 3B As shown, in another embodiment, the pins 12 of each packaged device extend outward along the four sides of the packaged device. When the sealing layer 40 is pre-cut, a plurality of pre-cutting lanes 41A and 41B are formed along the Y-axis and X-axis directions respectively, and the plurality of pre-cutting lanes 41A and 41B are arranged in an alternating manner.
[0040] Please refer to Figure 4As shown, after the pre-cutting operation is performed, the sealing layer 40 filled between adjacent pins 12 is removed. In this step, the sealing layer 40 can be burned by using a laser beam L, that is, the laser beam L is controlled to irradiate in the pre-cutting 41. The energy of the beam can burn the sealing layer 40 composed of dielectric material without burning the pins 12 made of metal. When the sealing layer 40 between adjacent pins 12 is removed, a gap can be formed between the adjacent pins 12.
[0041] In another embodiment, the sealing layer 40 may also be removed by plasma etching. Figure 5 As shown, if this method is adopted, a mask layer 50 (mask) must be pre-covered on the surface of the sealing layer 40, exposing only the sealing layer 40 in the pre-cutting road 41. The mask layer 50 can prevent the etching reaction gas from directly contacting the surface of the sealing layer 40. Because the sealing layer 40 between adjacent pins 12 is exposed to the reaction space of plasma etching, the sealing layer 40 between the pins 12 can be removed, and the mask layer 50 can be removed after plasma etching.
[0042] In another embodiment of plasma etching, the mask layer 50 can be a metal layer. After the plasma etching is completed, the metal layer does not need to be removed, so that it remains on the package device and serves as a metal heat dissipation layer to improve the surface heat dissipation efficiency of the package device.
[0043] After removing the sealing layer 40 between adjacent pins 12 , the present invention can further perform electroplating on the surface of the exposed pins 12 so that a tin layer 60 is attached to the exposed surface of each pin 12 to reduce the area of surface oxidation.
[0044] Please refer to Figure 6 As shown, after removing the sealing layer 40 between adjacent pins 12 or further completing the electroplating operation of the pins 12, a full cut is performed along the cutting path T shown by the dotted line around each packaged device to obtain multiple independently separated packaged devices. For example, when performing a full cut, at least the pre-cutting path 41 in the aforementioned process will be cut to separate the pins 12 between adjacent packaged devices.
[0045] Please refer to Figure 7A to Figure 7C, which is a schematic structural diagram of a finished packaged device of the present invention, the packaged device comprises a crystal pad 11, a plurality of pins 12, and a chip 20 disposed on the surface of the crystal pad 11, wherein the chip 20 is electrically connected to each pin 12 through a connector 30. A sealing layer 40 covers the crystal pad 11, a portion of the plurality of pins 12, the chip 20 and the connector 30, and the sealing layer 40 is a flat rectangular cube as a whole, having a top surface, a bottom surface and four side surfaces, wherein each of the side surfaces is a plane and is perpendicular to the top surface, and does not have a demolding angle of an existing sealing body.
[0046] Each pin 12 extends horizontally and straightly outward from the side of the sealing layer 40, and each pin 12 is not bent into a specific shape. The bottom surface of each pin 12, the bottom surface of the crystal pad 11 and the bottom surface of the sealing layer 40 are coplanar, so the bottom surface of the pin 12 and the bottom surface of the crystal pad 11 are exposed to the sealing layer 40 and are not covered by the sealing layer 40. The peripheral surface of each pin 12 is covered with a tin layer 60, and the end surface of each pin 12 is a cutting plane and is not covered with the tin layer 60.
[0047] When the packaged device of the present invention is actually used, the bottom surface of each pin 12 can be welded on the surface of a circuit board, and each pin 12 extending to the outside of the sealing layer 40 can also be provided for solder to adhere. According to the distribution of solder on each pin 12, the welding status of each pin 12 can be conveniently inspected from the outside of the packaged device to judge whether the packaged device is well welded to the circuit board.
[0048] In summary, the present invention has the following advantages:
[0049] 1. Compared with the existing packaging method, it is not necessary to use a specific mold equipment to seal the lead frame, nor is it necessary to use a specific specification machine for cutting and bending the pins, so the required equipment cost can be reduced.
[0050] 2. The present invention covers the lead frame with a sealing layer in its entirety, rather than individually covering a single die pad, thereby improving the efficiency of the sealing process and reducing problems of residual glue and overflowing glue.
[0051] 3. According to one embodiment of the present invention, the packaged device may have an appearance similar to a quad flat no-lead package (QFN), with pins on the bottom surface of the packaged device for soldering; in addition, each pin extends horizontally outward to increase the surface area in contact with the solder, thereby improving the reliability of soldering and being able to check from the appearance whether the packaged device is well connected to the circuit board.
[0052] 4. The present invention only cuts the lead frame, thereby reducing the problem of excessive stress accumulation on the pins caused by existing mechanical stamping and pin bending operations.
Claims
1. A flat package device with flat pins, characterized in that: Include: One crystal pad; A chip is disposed on the surface of the wafer pad; A plurality of pins are distributed around the die pad and are electrically connected to the chip respectively; and A sealing layer covers the crystal pad, a part of the plurality of pins and the chip, the sealing layer has a top surface, a bottom surface and four side surfaces, wherein each of the side surfaces is a plane and is perpendicular to the top surface, and each of the plurality of pins extends horizontally and straightly outward from the side surface of the sealing layer without bending.
2. The flat package device with flat pins as claimed in claim 1, characterized in that: The sealing layer is a flat rectangular cube; and A bottom surface of each of the pins, a bottom surface of the crystal pad and a bottom surface of the sealing glue layer are coplanar.
3. The flat package device with flat pins as claimed in claim 2, characterized in that: The plurality of pins are electrically connected to the chip through wires.
4. The flat package device with flat pins as claimed in claim 2, characterized in that: The plurality of pins are electrically connected to the chip through a conductive sheet.
5. The flat package device with flat pins according to any one of claims 1 to 4, characterized in that: The periphery of each pin is covered with a tin layer, and the end surface of each pin is a cutting plane and is not covered with the tin layer.
6. The flat package device with flat pins as claimed in claim 5, characterized in that: The plurality of pins extend horizontally and straightly outward from at least two opposite side surfaces of the sealing layer.
7. The flat package device with flat pins as claimed in claim 5, characterized in that: The surface of the sealing glue layer is provided with a metal heat dissipation layer.
8. A method for manufacturing a flat package device with flat pins, characterized in that: Include: Prepare a semi-finished substrate, the semi-finished substrate includes a lead frame, the lead frame has a plurality of crystal pads and pins, wherein at least one chip is disposed on the surface of each crystal pad, and the chip is electrically connected to the corresponding pin; The surface of the lead frame is completely covered with a sealing layer, the sealing layer covers the lead frame, the plurality of chips and the connector, and the surface of the sealing layer is a plane; Performing a pre-cutting operation on the sealing layer to form a plurality of pre-cutting lanes on the surface of the sealing layer, wherein the extension direction of the plurality of pre-cutting lanes is perpendicular to the extension direction of the plurality of pins, and each of the pre-cutting lanes extends from the surface of the sealing layer to the surface of each pin; In each pre-cutting lane, the sealing glue layer filled between adjacent pins is removed to form a gap between adjacent pins; and The semi-finished substrate is completely cut to obtain a plurality of independently separated packaged devices.
9. The method for manufacturing a flat package device with flat pins as claimed in claim 8, characterized in that: In the pre-cutting step, a plurality of vertically staggered pre-cutting paths are formed on the surface of the sealing layer.
10. The method for manufacturing a flat package device with flat pins as claimed in claim 8 or 9, characterized in that: In the pre-cutting step, the sealing layer is cut with a blade.
11. The method for manufacturing a flat package device with flat pins as claimed in claim 8 or 9, characterized in that: In the pre-cutting step, the sealing layer is cut by a laser beam.
12. The method for manufacturing a flat package device with flat pins as claimed in claim 8 or 9, characterized in that: In the step of removing the sealing layer between adjacent pins, the sealing layer between adjacent pins is burned away by a laser beam.
13. The method for manufacturing a flat package device with flat pins as claimed in claim 8 or 9, characterized in that: The step of removing the sealing glue layer between adjacent pins further includes: A mask layer is covered on the surface of the sealing layer, wherein the mask layer does not cover the plurality of pre-cutting paths; The sealing glue layer between adjacent pins is removed by plasma etching.
14. The method for manufacturing a flat package device with flat pins as claimed in claim 13, characterized in that: The mask layer is a metal layer.
15. The method for manufacturing a flat package device with flat pins as claimed in claim 8 or 9, characterized in that: After the sealing glue layer between adjacent pins is removed, the surface of each exposed pin is further electroplated to form a tin layer.
16. The method for manufacturing a flat package device with flat pins as claimed in claim 8 or 9, characterized in that: In the step of completely cutting the semi-finished substrate, cutting is performed at least along the plurality of pre-cut streets to separate the leads of adjacent packaged devices.