Embedded chip packaging structure and preparation method thereof

Abstract

The invention discloses an embedded chip packaging structure and a preparation method thereof in the field of semiconductor power product packaging testing, the packaging structure comprises a metal layer, an insulating dielectric layer, a metal base and a power chip, the power chip is placed on the metal base and embedded in a groove between the insulating dielectric layer and the metal layer, and the insulating dielectric layer is arranged on the metal base. The front surface of the power chip and the metal base are connected with the metal layers through metal via holes which are formed in advance to form a three-dimensional current loop; wherein the drain electrode of the power chip is connected with the power input end, the source electrode of the power chip is respectively connected with the Kelvin source electrode interface and the power output end, the grid electrode of the power chip is connected with the input end of the driving signal, and the packaging structure further comprises an insulation and voltage resistance test interface. And the insulation and voltage resistance test interface is connected with the lowermost metal layer through the isolated metal layers and the metal via holes. The electric energy transmission efficiency and the power density can be improved, the signal control accuracy is enhanced, and the stability and the reliability of the whole structure are improved.

Description

Technical Field

[0001] The invention relates to an embedded chip packaging structure and a preparation method thereof, belonging to the technical field of semiconductor power product packaging and testing. Background Art

[0002] With the rapid development of science and technology, the application of high-voltage power chips in high-demand fields such as automotive electronics has become more and more common. These applications have put forward strict automotive-grade standards for power modules to ensure the reliability, safety and performance of the products and meet the needs of long-term stable operation. 2 As a new packaging solution, Silicon Carbide Pack technology achieves increased power density and reduced parasitic inductance by embedding power chips into printed circuit boards (PCBs), thereby enhancing system efficiency and reliability. For chips embedded in PCBs, especially high-voltage silicon carbide chips, strict certification testing is crucial, which not only ensures product quality and reliability, but also meets the high standards of the automotive industry, enhances product competitiveness, and promotes quality control. However, existing technologies are insufficient in the testing and certification of high-voltage silicon carbide embedded chips and power modules, and cannot effectively respond to these special needs. Therefore, innovative packaging design solutions are urgently needed to overcome these limitations and promote the widespread application and stable development of high-voltage power products in fields such as new energy vehicles. Summary of the invention

[0003] The purpose of the present invention is to provide an embedded chip packaging structure and a preparation method thereof, which can solve the problem that traditional packaging cannot carry out certification testing for S-cells, and fully combine the PCB's own process to innovatively prepare a packaging structure specifically adapted for S-cells, meet the S-cell certification test and related application requirements, and provide a reliable packaging solution for the effective application of S-cells.

[0004] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions.

[0005] In a first aspect, the present invention provides an embedded chip packaging structure, comprising a metal layer, an insulating dielectric layer, a metal base and a power chip, wherein the power chip is placed on the metal base, and the power chip and the metal base assembly is embedded in a groove between the insulating dielectric layer and the metal layer, and the front surface of the power chip and the metal base are connected to the metal layers of each layer through pre-opened metal vias to form a three-dimensional current loop; The drain of the power chip is connected to the power input terminal through a metal layer and a metal via, the source of the power chip is connected to the Kelvin source interface and the power output terminal through a metal layer and a metal via, respectively, and the gate of the power chip is connected to the input terminal of the driving signal through a metal layer and a metal via; The packaging structure also includes an insulation withstand voltage test interface, which is connected to the bottom metal layer through isolated metal layers and metal vias.

[0006] In combination with the first aspect, further, the uppermost layer of the metal layer is coated with ink for protecting the circuit and providing insulation, and the lowermost layer of the metal layer serves as a heat dissipation layer in direct contact with the outside.

[0007] In combination with the first aspect, further, the metal via includes a first via, a second via and a third via, and the first via, the second via and the third via penetrate the insulating dielectric layer and connect different metal layers.

[0008] In combination with the first aspect, further, a copper layer with uniform thickness is plated on the hole walls of the first conductive hole and the third conductive hole.

[0009] In combination with the first aspect, further, the middle hollow areas of the first conductive hole and the third conductive hole are filled with insulating material to perform a plugging treatment.

[0010] In combination with the first aspect, further, it also includes a gate resistor for adjusting the gate current change rate, and the gate resistor is arranged between the power chip and the input end of the driving signal.

[0011] In combination with the first aspect, further, the gate resistor is surface mounted on a surface mount pad of the driving resistor.

[0012] In combination with the first aspect, further, the packaging structure is provided with a U-shaped groove for extending the creepage distance.

[0013] In a second aspect, a method for preparing an embedded chip packaging structure comprises: The metal base and the power chip are tightly combined by welding to form a combination; The assembly is embedded in the groove between the insulating dielectric layer and the two metal layers; Adding a plurality of metal layers and insulating dielectric layers above and below the assembly, respectively, and pressing the assembly and the original metal layers and insulating dielectric layers together with the newly added plurality of metal layers and insulating dielectric layers to form a multi-layer packaging structure; A first conductive hole and a third conductive hole are formed on the multi-layer packaging structure by a drilling process, and a second conductive hole is formed on the multi-layer packaging structure by a laser process; After the via holes are made, a predetermined circuit pattern is made on each metal layer connected to the first via hole, the second via hole and the third via hole by etching technology; After etching is completed, ink is coated on the uppermost layer of the metal layer to form an ink layer.

[0014] In combination with the second aspect, further, the packaging structure can support multiple contact modes during testing to meet the testing requirements of AEC-Q101 and AQG-324 standards.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The packaging structure of the present invention first places the power chip on the metal base and embeds the assembly into the groove between the insulating dielectric layer and the metal layer to form a stable mechanical support, and at the same time connects the metal layers through the pre-opened metal vias to build a three-dimensional current loop. This structure not only ensures the effective transmission of electrical energy, but also improves the reliability and efficiency of electrical connections.

[0016] In addition, the drain, source, and gate of the power chip are connected to the corresponding power input terminal, Kelvin source interface, power output terminal, and drive signal input terminal through metal layers and metal vias. This layout makes power transmission and signal control more accurate and efficient. In particular, the design of the Kelvin source interface helps to reduce the parasitic inductance of the source pin, optimize the layout of the driver board, increase the switching speed, and reduce the switching loss, thereby improving the overall performance.

[0017] In order to further improve the safety and reliability of the package structure, the package structure also includes an insulation withstand voltage test interface, which is connected to the bottom metal layer through isolated metal layers and metal vias, allowing high voltage to be applied during testing and monitoring leakage current to determine the integrity of the insulation. This design helps ensure the safety and stability of the package structure under high voltage conditions, prevent electrical breakdown and short circuits, and ensure the long-term stable operation of the package structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 1 is a schematic diagram of an embedded chip packaging structure provided by an embodiment of the present invention; Figure 2 The figure is a front schematic diagram of the L1 layer of the packaging structure provided by an embodiment of the present invention; Figure 3 The figure shows a schematic diagram of the surface of the packaging structure L1 layer after being coated with ink provided by an embodiment of the present invention; Figure 4 FIG. 1 is a schematic diagram of the back side L6 layer of the packaging structure provided by an embodiment of the present invention; In the figure: 1. Metal layer; 2. Insulating medium layer; 3. Metal base; 4. Power chip; 5. First through hole; 6. Second through hole; 7. Third through hole; 8. Ink; 9. Drive resistor surface mount pad; 10. U-shaped groove; 11. External access power input terminal; 12. Welding power input terminal; 13. Back power input terminal; 14. External access power output terminal; 15. Welding power output terminal; 16. Back power output terminal; 17. Ink layer; 18. Heat dissipation layer; 21. First source interface; 22. Second source interface; 31. Front drive signal input terminal; 32. Back drive signal input terminal; 41. Front insulation withstand voltage test interface; 42. Back insulation withstand voltage test interface. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. The embodiments of the present invention and the technical features in the embodiments may be combined with each other unless there is a conflict.

[0020] The term "and / or" is only a description of the association relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the related objects are in an "or" relationship. Example 1

[0021] See also Figure 1 The present invention introduces an embedded chip packaging structure, which is specially designed for the testing and certification of power products, and aims to meet the strict requirements of high quality and reliability in the field of automotive electronics. The core components of the packaging structure include a power chip 4, and the range of the power chip 4 includes but is not limited to high-voltage power products such as silicon carbide (SiC), gallium nitride (GaN), and insulated gate bipolar transistors (IGBT). The power chip 4 is placed on a metal base 3, and the combination of the two is embedded in the groove between the insulating dielectric layer 2 and the metal layer 1. This arrangement not only ensures the physical support of the power chip 4, but also connects with the metal layer 1 through the metal via to form a three-dimensional current loop, providing a stable current and signal transmission path for the power chip 4.

[0022] In this package structure, see Figure 3 and Figure 4The drain of the power chip 4 is connected to the power input terminal through the metal layer 1 and the metal via, ensuring the effective transmission of electric energy. The power input terminal is the primary port of the transmission link, and the power input terminal includes a front power input terminal, that is, an external access power input terminal 11, a welding power input terminal 12, and a back power input terminal 13. The back power input terminal 13 is located on the back of the packaging structure and cooperates with the front input terminal of the packaging structure.

[0023] The source of the power chip 4 is connected to the Kelvin source interface and the power input terminal through the metal layer 1 and the metal via respectively. The Kelvin source serves as an auxiliary source, which helps to reduce the parasitic inductance of the source pin, optimize the drive board layout, increase the switching speed, and reduce the switching loss. Among them, the Kelvin source interface includes a first source interface 21 and a second source interface 22; the power output terminal includes a front output terminal, namely an externally connected power output terminal 14, a welded power output terminal 15 and a back power output terminal 16.

[0024] The gate of the power chip 4 is connected to the drive signal input terminal through the metal layer 1 and the metal via, and different gate resistors are surface-mounted to achieve precise regulation of gate current changes, avoiding voltage overshoot and suppressing oscillation, thereby protecting the gate of the power device; wherein, the input terminal of the drive signal includes a front drive signal input terminal 31 and a back drive signal input terminal 32.

[0025] In order to ensure the safety and reliability of the packaging structure, the packaging structure also includes an insulation withstand voltage test interface, which is connected to the bottom metal layer (L6 metal layer) through the isolated metal layer 1 and the metal via. This connection method allows high voltage to be applied during the test and the leakage current to be monitored to determine the integrity of the insulation. The insulation withstand voltage test interface includes a front insulation withstand voltage test interface 41 and a back insulation withstand voltage test interface 42.

[0026] In addition, in order to achieve more accurate drive current regulation and adapt to a variety of power devices and protect power devices, the package structure also includes a drive resistor surface mount pad 9, which can be surface mounted with different gate resistors. The L1 layer is connected to the gate of the chip through the circuit design and metal vias, etc., so that the drive current can be adjusted more accurately.

[0027] In summary, the packaging structure design of the present invention not only meets the application requirements of high-voltage power products in the fields of automotive electronics, but also provides a practical and innovative solution through its unique design, such as diversified contact methods, optimized drive layout and enhanced safety measures, providing a solid quality foundation for the testing and certification of high-voltage power modules. Example 2

[0028] See also Figure 3 The top layer of the metal layer 1 is coated with ink 8, which not only protects the circuit from physical damage and environmental influences, but also provides insulation function to prevent short circuits between circuits, ensuring the stability and safety of the packaging system. In contrast, the bottom layer of the metal layer 1 is not coated with ink 8, but is directly in contact with the outside world as a heat dissipation layer 18, thereby quickly conducting the heat generated inside the package to the external environment, keeping the temperature inside the package within a safe range, and improving the thermal management efficiency of the package.

[0029] Furthermore, the metal vias include a first via 5, a second via 6 and a third via 7, and the three vias penetrate the insulating dielectric layer 2 and connect different metal layers 1 to achieve electrical connection between the layers.

[0030] In particular, the hole walls of the first via 5 and the third via 7 are plated with a copper layer of uniform thickness, which enhances the conductivity of the hole walls and ensures that the vias can serve as effective electrical connection channels. In order to ensure the reliability of the packaged product in subsequent tests and other processes, the hollow areas in the middle of these vias are filled with insulating materials for plugging to prevent short circuits between the copper layer and the surrounding metal layer.

[0031] In addition, in order to accurately control the gate current change rate, the packaging structure also includes a gate resistor arranged between the power chip 4 and the drive signal input terminal. The setting of the gate resistor avoids voltage overshoot and suppresses oscillation, protecting the gate of the power device from damage.

[0032] In terms of contact methods, the packaging structure provides a variety of options, including probe contact, pluggable contact and welding, to adapt to different test scenarios and equipment connection requirements.

[0033] It should be noted that in order to adapt to higher pollution levels and ensure safety in high-voltage environments, see Figure 2 The packaging structure is designed with a U-shaped groove 10 to extend the creepage distance, and the path that the current may "crawl" is further extended by increasing the straight-line distance and the groove shape, thereby increasing the creepage distance.

[0034] In summary, the embedded chip packaging structure of the present invention provides a practical and innovative solution through its unique design, such as the ink layer 17 for protecting the circuit, the multi-layer metal vias, the plugging treatment, the setting of the gate resistor, the diversified contact methods and the U-shaped groove 10 for extending the creepage distance, to meet the application requirements of high-voltage power products in the fields of automotive electronics, etc., and ensure the safety, reliability and high efficiency of the packaging structure. Example 3

[0035] In combination with Example 1 and Example 2, the present invention introduces a method for preparing an embedded chip packaging structure, which aims to achieve a multi-layer packaging structure with a stable structure and excellent electrical performance. The preparation process includes: Step S1, tightly combining the metal base 3 and the power chip 4 by welding to form a stable assembly; Here, the metal base 3 is connected to the power chip 4 directly or by means of solder. This step ensures the electrical and mechanical connection between the power chip 4 and the metal base 3, providing a solid foundation for the subsequent packaging structure.

[0036] Step S2, embedding the welded assembly into the groove between the insulating dielectric layer 2 and the two metal layers 1; Here, this step is to fix the power chip 4 and ensure its electrical isolation from the surrounding structures.

[0037] Step S3, adding a plurality of metal layers 1 and insulating dielectric layers 2 above and below the assembly and stacking them alternately, and pressing the newly added stacked body together with the original assembly and the metal layers 1 and insulating dielectric layers 2 to form a multi-layer packaging structure; Here, the packaging structure of the embodiment of the present invention is finally pressed into a six-layer composite plate structure. The pressing process can ensure that the layers are tightly combined to build a stable overall structure, while providing more circuit layers and better electrical isolation.

[0038] Step S4, using a drilling process to form a first conductive hole 5 and a third conductive hole 7 on the stacked body, and using a laser process to form a second conductive hole 6; Here, three vias penetrate the insulating dielectric layer 2 and connect different metal layers 1 to achieve electrical connection between layers. The production of vias is a key step in connecting the chip to the external circuit, as they ensure that current and signals can flow smoothly inside the package structure.

[0039] Step S5, after the via holes are made, a predetermined circuit pattern is made on each metal layer 1 connected to the first via hole 5, the second via hole 6 and the third via hole 7 by etching technology; Here, the circuit pattern defines the conductive path on the metal layer, including leading out different electrode connection points (electrodes of the power chip 4 and electrodes of the metal base 3) and constructing the path for current flow, ensuring that the current can flow along the predetermined path and achieve correct connection between the power chip 4 and the external circuit.

[0040] Step S6 : After etching is completed, ink 8 is coated on the uppermost layer of the metal layer 1 to form an ink layer 17 .

[0041] Here, the ink layer protects the circuit from physical damage and environmental influences, while providing insulation function to prevent short circuits between circuits and ensure the stability and safety of the packaging system, while the bottom metal layer 1 is not coated with ink, so that its metal surface acts as a heat dissipation layer in contact with the outside world.

[0042] In summary, the preparation method of the present invention realizes a high-performance embedded chip packaging structure through precise welding, pressing, via hole production and circuit pattern etching. This method not only improves the electrical performance and thermal management efficiency of the packaging structure, but also enhances its mechanical stability and environmental adaptability, meeting the requirements of high-voltage power products in the fields of automotive electronics, namely AEC-Q 101 and AQG-324.

[0043] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. An embedded chip packaging structure, characterized in that: Comprising a metal layer (1), an insulating dielectric layer (2), a metal base (3) and a power chip (4), wherein the power chip (4) is placed on the metal base (3), the power chip (4) and the metal base (3) assembly is embedded in a groove between the insulating dielectric layer (2) and the metal layer (1), and the front surface of the power chip (4) and the metal base (3) are connected to the metal layers (1) of each layer via pre-opened metal conducting holes, thereby forming a three-dimensional current loop; The drain of the power chip (4) is connected to the power input terminal through the metal layer (1) and the metal via hole, the source of the power chip (4) is connected to the Kelvin source interface and the power output terminal through the metal layer (1) and the metal via hole, respectively, and the gate of the power chip (4) is connected to the input terminal of the drive signal through the metal layer (1) and the metal via hole; The packaging structure further comprises an insulation withstand voltage test interface, wherein the insulation withstand voltage test interface is connected to the bottommost metal layer (1) through the isolated metal layer (1) and the metal via hole.

2. The embedded chip packaging structure according to claim 1, characterized in that: The uppermost layer of the metal layer (1) is coated with ink (8) for protecting the circuit and providing insulation, and the lowermost layer of the metal layer (1) serves as a heat dissipation layer in direct contact with the outside world.

3. The embedded chip packaging structure according to claim 1, characterized in that: The metal vias comprise a first via (5), a second via (6) and a third via (7); the first via (5), the second via (6) and the third via (7) penetrate the insulating dielectric layer (2) and connect different metal layers (1).

4. The embedded chip packaging structure according to claim 3, characterized in that: The hole walls of the first conductive hole (5) and the third conductive hole (7) are plated with a copper layer of uniform thickness.

5. The embedded chip packaging structure according to claim 4, characterized in that: The hollow areas between the first conductive hole (5) and the third conductive hole (7) are filled with insulating material to perform a plugging process.

6. The embedded chip packaging structure according to claim 1, characterized in that: It also includes a gate resistor for regulating the gate current change rate, wherein the gate resistor is arranged between the power chip (4) and the input end of the drive signal.

7. The embedded chip packaging structure according to claim 6, characterized in that: The gate resistor is surface mounted on the driving resistor surface mounting pad (9).

8. The embedded chip packaging structure according to claim 1, characterized in that: The packaging structure is also provided with a U-shaped groove (10) for extending the creepage distance.

9. A method for preparing the embedded chip packaging structure according to claims 1-8, characterized in that: include: The metal base (3) and the power chip (4) are tightly combined by welding to form a combined body; The assembly is embedded in the groove between the insulating dielectric layer (2) and the two metal layers (1); Adding a plurality of metal layers (1) and insulating dielectric layers (2) above and below the assembly, respectively, and pressing the assembly and the original metal layers (1) and insulating dielectric layers (2) together with the newly added plurality of metal layers (1) and insulating dielectric layers (2) to form a multi-layer packaging structure; A first conductive hole (5) and a third conductive hole (7) are made on the multi-layer packaging structure by using a drilling process, and a second conductive hole (6) is made on the multi-layer packaging structure by using a laser process; After the via holes are made, a predetermined circuit pattern is made on each metal layer (1) connected to the first via hole (5), the second via hole (6) and the third via hole (7) by etching technology; After etching is completed, ink (8) is coated on the uppermost layer of the metal layer (1) to form an ink layer (17).

10. The embedded chip packaging structure according to claim 9, characterized in that: The packaging structure can support multiple contact modes during testing to meet the testing requirements of AEC-Q101 and AQG-324 standards.

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