Semiconductor element with thickening layer and manufacturing method thereof

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor element includes a substrate; the word line structure comprises a word line dielectric layer which is arranged in the substrate and has a U-shaped section profile; the lower conductive part is located on the word line dielectric layer and located in the substrate, and the upper conductive part is located on the lower conductive part and located in the substrate; and a word line cover layer on the word line conductive layer, the lower thickening layer is provided with a U-shaped section profile and is arranged between the lower conductive part and the upper conductive part, between the upper conductive part and the word line dielectric layer and between the word line cover layer and the word line dielectric layer; a lower cap layer on the substrate and adjacent to the word line dielectric layer; and an upper cap layer covering the lower cap layer and the word line structure. The upper surface of the lower thickening layer and the upper surface of the word line dielectric layer are roughly coplanar, and the vertical bit plane of the upper surface of the lower thickening layer and the vertical bit plane of the upper surface of the word line dielectric layer are higher than the upper surface of the substrate. The lower thickening layer includes a high-k material, an oxide, a nitride, a nitrogen oxide, or a combination thereof.

Description

[0001] This application is a divisional of Chinese invention patent application No. 202311715290.3, entitled “Semiconductor element with thickened layer and method for manufacturing the same,” filed on December 13, 2023. Application No. 202311715290.3 claims priority and benefits of U.S. formal application No. 18 / 377,413 filed on October 6, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method for preparing the semiconductor element, and more particularly to a semiconductor element having a thickened layer and a method for preparing the semiconductor element having the thickened layer. Background Art

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor components is gradually getting smaller to meet the increasing demand for computing power. However, during the process of size reduction, different problems increase. Therefore, there are still challenges in achieving improved quality, yield, performance and reliability, as well as reducing complexity.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0005] An embodiment of the present disclosure provides a semiconductor element, including a substrate; a word line structure, including: a word line dielectric layer, located in the substrate and including a U-shaped cross-sectional profile; a word line conductive layer, a lower conductive portion and an upper conductive portion, the lower conductive portion including a portion located on the word line dielectric layer and located in the substrate, and the upper conductive portion located on the lower conductive portion and located in the substrate; and a word line cap layer, located on the word line conductive layer; a lower thickening layer, including a U-shaped cross-sectional profile, located between the lower conductive portion and the upper conductive portion, between the upper conductive portion and the word line dielectric layer, and between the word line cap layer and the word line dielectric layer; a lower cap layer, located on the substrate and adjacent to the word line dielectric layer; and an upper cap layer, covering the lower cap layer and the word line structure. An upper surface of the lower thickening layer and an upper surface of the word line dielectric layer are substantially coplanar, and a vertical plane of the upper surface of the lower thickening layer and the upper surface of the word line dielectric layer is higher than an upper surface of the substrate. The lower thickening layer comprises a high-k material, an oxide, a nitride, a nitride oxide or a combination thereof.

[0006] Another embodiment of the present disclosure provides a method for preparing a semiconductor device, comprising providing a substrate, forming a lower cover layer on the substrate, and forming a word line groove passing through the substrate and extending to the substrate; conformally forming a word line dielectric layer on the word line groove; forming a lower conductive portion on the word line dielectric layer and in the word line groove; conformally forming a first thickened material layer on the lower conductive portion, the word line dielectric layer and the lower cover layer; forming an upper conductive portion on the first thickened material layer and in the word line groove; The invention relates to a method for forming a word line trench in a conductive layer; conformally forming a second thickening material layer on the upper conductive portion and the first thickening material layer; forming an upper insulating material layer on the second thickening material layer to completely fill the word line trench; removing portions of the second thickening material, the first thickening material and the upper insulating material to respectively form an upper thickening layer, a lower thickening layer and a word line cover layer, while recessing the word line dielectric layer; and forming an upper cover layer to cover the lower cover layer, the word line dielectric layer, the word line cover layer, the lower thickening layer and the upper thickening layer.

[0007] Due to the design of the semiconductor device disclosed in the present invention, the thickness of the word line dielectric layer is increased by adding the lower thickening layer and / or the upper thickening layer, which can effectively alleviate the drain leakage problem caused by the gate, thereby improving the performance of the semiconductor device. In addition, the upper cover layer shields the word line dielectric layer, the lower thickening layer and the upper thickening layer during the etching and / or cleaning process. This protection can prevent these layers from being recessed and exposing the drain region and the source region, thereby avoiding short circuits that may occur due to such exposure.

[0008] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1 1 is a flow chart illustrating a method for preparing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 2 to 19It is a cross-sectional schematic diagram illustrating a process of preparing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 20 to Figure 22 It is a schematic cross-sectional view illustrating the process of preparing a semiconductor element in some embodiments of the present disclosure.

[0013] Description of reference numerals:

[0014] 1A: Semiconductor components

[0015] 1B: Semiconductor components

[0016] 1C: Semiconductor components

[0017] 1D: Semiconductor components

[0018] 10: Preparation method

[0019] 101: Base

[0020] 101TS: Top surface

[0021] 103: Isolation layer

[0022] 105: Impurity region

[0023] 105D: Drain region

[0024] 105S: Source region

[0025] 111: Lower cover layer

[0026] 111TS: Top surface

[0027] 113: Upper cover layer

[0028] 200: Character line structure

[0029] 210: word line dielectric layer

[0030] 210TS: Top surface

[0031] 220: word line conductive layer

[0032] 221: Lower conductive part

[0033] 221TS: Upper surface

[0034] 223: Upper conductive part

[0035] 230: Character line cover layer

[0036] 230P: Protrusion

[0037] 230TS: Upper surface

[0038] 301: Lower barrier layer

[0039] 301TS: Upper surface

[0040] 303: Intermediate barrier layer

[0041] 303TS: Upper surface

[0042] 401: Lower thickening layer

[0043] 401TS: Upper surface

[0044] 403: Upper thickening layer

[0045] 403TS: Top surface

[0046] 511: First insulating material layer

[0047] 513: Upper insulating material layer

[0048] 521: First barrier material layer

[0049] 531: first conductive material layer

[0050] 533: Second conductive material layer

[0051] 541: First thickening material layer

[0052] 543: Second thickening material layer

[0053] 601: Bit line contact

[0054] 601O: Bit line contact opening

[0055] 603: Unit contact point

[0056] 701: First mask layer

[0057] AA: Active Area

[0058] S11: Steps

[0059] S13: Steps

[0060] S15: Steps

[0061] S17: Steps

[0062] S19: Steps

[0063] S21: Steps

[0064] T1: Thickness

[0065] T2: Thickness

[0066] T3: Thickness

[0067] T4: Thickness

[0068] T5: Thickness

[0069] T6: Thickness

[0070] TR: Character line groove

[0071] VL1: Vertical plane

[0072] VL2: Vertical plane

[0073] VL3: Vertical plane

[0074] Z: Direction DETAILED DESCRIPTION

[0075] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0076] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0077] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0078] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0079] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variances that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, is exactly the same, equal, or planar, or it may be the same, equal, or planar within an acceptable variance, and for example, the acceptable variance may occur due to the manufacturing process.

[0080] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0081] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the relative direction of the Z-direction arrow.

[0082] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 19 1 is a cross-sectional schematic diagram illustrating a process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0083] refer to Figures 1 to 3 In step S11 , a substrate 101 may be provided, a lower cap layer 111 may be formed on the substrate 101 , and a plurality of word line trenches TR may be formed passing through the lower cap layer 111 and extending to the substrate 101 .

[0084] Please refer to Figure 2 The substrate 101 may include a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or a combination thereof.

[0085] Please refer to Figure 2 , an isolation layer 103 may be formed in the substrate 101. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A photolithography process and a subsequent etching process, such as an anisotropic dry etching process, may be performed to form a plurality of trenches penetrating the pad oxide layer, the pad nitride layer and extending to the substrate 101. An insulating material may be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, may be subsequently performed until the upper surface 101TS of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent processing steps, and simultaneously form the isolation layer 103. For example, the insulating material may be silicon oxide or other applicable insulating materials. In some embodiments, the isolation layer 103 may define an active area AA in the substrate 101.

[0086] Please refer to Figure 2, an impurity region 105 may be formed in the active region AA. In some embodiments, the fabrication technique of the impurity region 105 may include an implantation process using a p-type dopant or an n-type dopant. The term "p-type dopant" refers to an impurity that produces a valence electron defect when added to an intrinsic semiconductor material. In a silicon-containing semiconductor material, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, or indium. The term "n-type dopant" refers to an impurity that contributes free electrons to the intrinsic semiconductor material when added to an intrinsic semiconductor material. For example, in a silicon-containing material, examples of n-type dopants include, but are not limited to, antimony, arsenic, or phosphorus.

[0087] Please refer to Figure 2 , a lower cap layer 111 may be formed on the substrate 101 to completely cover the impurity region 105 and the isolation layer 103. In some embodiments, the lower cap layer 111 may include a material having an etching selectivity to the substrate 101 and the isolation layer 103. In some embodiments, for example, the lower cap layer 111 may include silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, silicon boron carbon nitride, or a combination thereof. In some embodiments, for example, the lower cap layer 111 may include silicon nitride. In some embodiments, for example, the manufacturing technology of the lower cap layer 111 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes.

[0088] Please refer to Figure 2 A first mask layer 701 may be formed on the lower cap layer 111. In some embodiments, the first mask layer 701 may be a photoresist layer and may include a pattern of a plurality of word line trenches TR.

[0089] Please refer to Figure 3 , a trench etching process can be performed using the first mask layer 701 as a mask to remove some portions of the lower cover layer 111, some portions of the isolation layer 103 and the substrate 101, and simultaneously form a plurality of word line trenches TR. After forming the plurality of word line trenches TR, the first mask layer 701 can be removed. The impurity region 105 can be divided into a plurality of segments. The plurality of segments disposed between the isolation layer 103 and the word line trenches TR can be referred to as drain regions 105D. The plurality of segments disposed between two adjacent word line trenches TR can be referred to as source regions 105S. In a cross-sectional view, the lower cover layer 111 can be divided into a plurality of segments.

[0090] Please refer to Figure 1 and Figures 4 to 6 In step S13 , a plurality of word line dielectric layers 210 may be conformally formed on the plurality of word line trenches TR, and a plurality of lower conductive portions 221 may be formed on the plurality of word line dielectric layers 210 .

[0091] Please refer to Figure 4 , a first insulating material layer 511 may be conformally formed on the lower cover layer 111 and on the plurality of word line trenches TR. The first insulating material layer 511 may have a U-shaped cross-sectional profile in the plurality of word line trenches TR. That is, the first insulating material layer 511 may be conformally formed along the surface of the plurality of word line trenches TR. In some embodiments, the first insulating material layer 511 may have a thickness in a range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0092] In some embodiments, the manufacturing technology of the first insulating material layer 511 may include a thermal oxidation process. For example, the manufacturing technology of the first insulating material layer 511 may include oxidizing the surface of the plurality of word line trenches TR. In some embodiments, the manufacturing technology of the first insulating material layer 511 may include a deposition process, such as chemical vapor deposition or atomic layer deposition. In some embodiments, after depositing a pad polysilicon layer (not shown in the figure for clarity), the manufacturing technology of the first insulating material layer 511 may include free radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown in the figure for clarity), the manufacturing technology of the first insulating material layer 511 may include free radical oxidation of the pad silicon nitride layer. In some embodiments, the first insulating material 511 may include a material having an etching selectivity to the lower cover layer 111 and the substrate 101. In some embodiments, the first insulating material 511 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof.

[0093] In some embodiments, the high-k dielectric material may include a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0094] Please refer to Figure 5 , a first barrier material layer 521 can be conformally formed on the first insulating material layer 511. In some embodiments, for example, the first barrier material layer 521 can be titanium nitride, titanium, or a combination thereof. In some embodiments, for example, the first barrier material layer 521 can be titanium nitride. In some embodiments, for example, the fabrication technique of the first barrier material layer 521 can include atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other applicable deposition processes.

[0095] Please refer to Figure 5, a first conductive material layer 531 may be formed on the first barrier material layer 521 and completely fill the plurality of word line trenches TR. In some embodiments, for example, the first conductive material 531 may be tungsten, cobalt, zirconium, tantalum, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), transition metal aluminide, or a combination thereof. In some embodiments, for example, the first conductive material 531 may be tungsten. In some embodiments, for example, the fabrication technique of the first conductive material layer 531 may include physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, or other applicable deposition processes.

[0096] Please refer to Figure 6 A planarization process, such as chemical mechanical polishing, may be performed until the upper surface 111TS of the lower cap layer 111 is exposed to remove excess material, provide a substantially flat surface for subsequent processing steps, and transform the first insulating material layer 511 into a plurality of word line dielectric layers 210. The plurality of word line dielectric layers 210 may be formed on the plurality of word line trenches TR, respectively.

[0097] Please refer to Figure 6 , an etch-back process may be performed to remove some portions of the first barrier material layer 521 and the first conductive material layer 531. After the etch-back process, the first barrier material layer 521 is transformed into a plurality of lower barrier layers 301 on the plurality of word line dielectric layers 210. The first conductive material layer 531 is transformed into a plurality of lower conductive portions 221 on the plurality of lower barrier layers 301.

[0098] For the sake of brevity, clarity and convenience of description, only one word line dielectric layer 210 , one lower barrier layer 301 and one lower conductive portion 221 are described.

[0099] Please refer to Figure 6 In some embodiments, the upper surface 210TS of the word line dielectric layer 210 and the upper surface 111TS of the lower cap layer 111 may be substantially coplanar. In some embodiments, the upper surface 221TS of the lower conductive portion 221 and the upper surface 301TS of the lower barrier layer 301 may be substantially coplanar. In some embodiments, the upper surface 221TS of the lower conductive portion 221 and the upper surface 301TS of the lower barrier layer 301 may be in different vertical planes (not shown).

[0100] In some embodiments, the thickness of the upper section of the wordline dielectric layer 210 may be reduced due to consumption during the etch-back and / or post-etch cleaning process. Therefore, the upper section of the wordline dielectric layer 210 becomes thinner than the lower section of the wordline dielectric layer 210. For illustration, the thickness T1 at the upper section of the wordline dielectric layer 210 may be less than the thickness T2 at the lower section of the wordline dielectric layer 210. In some embodiments, the thickness T1 at the upper section of the wordline dielectric layer 210 may gradually increase from the upper surface 210TS of the wordline dielectric layer 210 downward toward the substrate 101.

[0101] Please refer to Figure 1 , Figure 7 and Figure 8 In step S15 , a plurality of intermediate barrier layers 303 may be formed on the plurality of lower conductive portions 221 , and a first thickening material layer 541 may be conformally formed on the lower cap layer 111 , the plurality of word line dielectric layers 210 , and the plurality of intermediate barrier layers 303 .

[0102] Please refer to Figure 7 , multiple intermediate barrier layers 303 may be formed on multiple lower conductive portions 221 respectively. For the sake of brevity, clarity and convenience of description, only one intermediate barrier layer 303 is described. The intermediate barrier layer 303 may be formed in the word line trench TR and may also cover the lower barrier layer 301. That is, in the cross-sectional view, the lower conductive portion 221 may be surrounded by the lower barrier layer 301 and the intermediate barrier layer 303. In some embodiments, for example, the intermediate barrier layer 303 may include titanium nitride, titanium or a combination thereof. In some embodiments, for example, the intermediate barrier layer 303 may include titanium nitride. In some embodiments, the intermediate barrier layer 303 may include the same material as the lower barrier layer 301. In some embodiments, for example, the manufacturing technology of the intermediate barrier layer 303 may include radio frequency physical vapor deposition or other applicable deposition. In some embodiments, the thickness T3 of the lower barrier layer 301 and the thickness T4 of the intermediate barrier layer 303 may be substantially the same. In some embodiments, the thickness T3 of the lower barrier layer 301 and the thickness T4 of the middle barrier layer 303 may be different.

[0103] It should be understood that the intermediate barrier layer 303 may be selectively formed on the lower conductive portion 221 and the lower barrier layer 301. No visible intermediate barrier layer 303 is found on the inner surface of the word line dielectric layer 210.

[0104] Please refer to Figure 8, the first thickening material layer 541 may be conformally formed on the lower cover layer 111, the plurality of word line dielectric layers 210, and the plurality of intermediate barrier layers 303. In some embodiments, the first thickening material layer 541 formed in the word line trench TR may present a U-shaped cross-sectional profile due to conformality with the inner surface of the word line dielectric layer 210 and the upper surface 303TS of the intermediate barrier layer 303. In some embodiments, the first thickening material layer 541 formed on the inner surface of the word line dielectric layer 210 may be tapered due to conformality with the inner surface of the word line dielectric layer 210. In some embodiments, for example, the first thickening material 541 may be a material having etching selectivity to the lower cover layer 111. In some embodiments, for example, the first thickening material layer 541 may be silicon oxide. In some embodiments, the manufacturing technology of the first thickening material layer 541 may include atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0105] Please refer to Figure 1 and Figures 9 to 12 In step S17 , a plurality of upper conductive portions 223 may be formed on the first thickened material layer 541 , and a second thickened material layer 543 may be conformally formed on the plurality of upper conductive portions 223 and the first thickened material layer 541 .

[0106] Please refer to Fig. 9 , a second conductive material layer 533 may be formed on the first thickened material layer 541 and completely fill the word line trench TR. In some embodiments, for example, the second conductive material 533 may be polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the second conductive material layer 533 may be doped with a p-type dopant or an n-type dopant. In some embodiments, for example, the manufacturing technology of the second conductive material layer 533 may include chemical vapor deposition or other applicable deposition processes. In some embodiments, doping may be achieved by an implantation process after the deposition process. In some embodiments, doping may be performed by doping dopants during the deposition process.

[0107] Please refer to Fig.10 , an etch-back process may be subsequently performed to remove some portions of the second conductive material layer 533 to form a plurality of upper conductive portions 223. For the sake of brevity, clarity and convenience of description, only one upper conductive portion 223 is described. The upper conductive portion 223 may be formed on the first thickened material layer 541 and within the word line trench TR. The lower conductive portion 221 and the upper conductive portion 223 together constitute a word line conductive layer 220.

[0108] In some embodiments, the upper segment of the first thickened material layer 541 formed on the word line dielectric layer 210 may be consumed during the etch-back process or the post-cleaning process after the etch-back process. That is, the thickness of the upper segment may be reduced or the upper segment may be completely consumed, so that the upper segment of the word line dielectric layer 210 may be partially exposed (not shown).

[0109] Please refer to Fig.11 , the second thickening material layer 543 can be conformally formed on the first thickening material layer 541 and the plurality of upper conductive portions 223. In some embodiments, the second thickening material layer 543 formed in the word line trench TR can present a U-shaped cross-sectional profile due to being conformal with the first thickening material layer 541. In some embodiments, the second thickening material layer 543 formed in the word line trench TR can be tapered. In some embodiments, for example, the second thickening material layer 543 can be a material having etching selectivity to the lower cover layer 111. In some embodiments, the second thickening material layer 543 can be the same material as the first thickening material layer 541. In some embodiments, for example, the second thickening material layer 543 can be silicon oxide. In some embodiments, the manufacturing technology of the second thickening material layer 543 can include atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0110] Please refer to Fig.12 , an upper insulating material layer 513 can be formed on the second thickening material layer 543 and completely fill the plurality of word line trenches TR. In some embodiments, for example, the upper insulating material layer 513 can be a material having etching selectivity to the word line dielectric layer 210, the first thickening material layer 541 and the second thickening material layer 543. In some embodiments, for example, the upper insulating material layer 513 can be silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, silicon boron carbon nitride or a combination thereof. In some embodiments, for example, the upper insulating material 513 can be silicon nitride. In some embodiments, for example, the manufacturing technology of the upper insulating material layer 513 can include chemical vapor deposition, plasma enhanced chemical vapor deposition or other applicable deposition processes.

[0111] Please refer to Figure 1 and Figures 13 to 15 In step S19 , a recess process may be performed to remove portions of the upper insulating material layer 513 , the second thickening material layer 543 , and the first thickening material layer 541 to form a plurality of word line capping layers 230 , a plurality of upper thickening layers 403 , and a plurality of lower thickening layers 401 .

[0112] In some embodiments, the recess process can be a multi-stage etching process. For example, the recess process can be a three-stage etching process. The etching chemistry in each stage can be different to provide different etching selectivities. In some embodiments, the recess process can alternately use phosphoric acid and dilute hydrofluoric acid to selectively remove nitrides and oxides, respectively. In some embodiments, the recess process can include vapor hydrofluoric acid and ammonia. By adjusting the ratio between the vapor hydrofluoric acid and ammonia used in the recess process, nitrides or oxides can be selectively etched.

[0113] Please refer to Fig.13 During the first stage of the recess process, the upper insulating material layer 513 may be selectively removed. The endpoint may be identified by detecting the second thickened material layer 543 and / or the first thickened material layer 541. In some embodiments, the first stage of the recess process may include phosphoric acid to selectively remove the upper insulating material layer 513 including silicon nitride. After the first stage of the recess process, the remaining upper insulating material layer 513 may be referred to as a plurality of word line capping layers 230. The word line dielectric layer 210, the word line conductive layer 220, and the word line capping layer 230 together constitute the word line structure 200.

[0114] Please refer to Fig.14 , during the second stage of the recess process, the first thickened material layer 541 and the second thickened material layer 543 formed on the lower cover layer 111 may be selectively removed. The endpoint may be identified by identifying the lower cover layer 111. In some embodiments, the second stage of the recess process may include dilute hydrofluoric acid to selectively remove the first thickened material layer 541 and the second thickened material layer 543 including silicon oxide. After the second stage of the recess process, the remaining second thickened material layer 543 may be transformed into the upper thickened layer 403. The remaining first thickened material layer 541 may be transformed into the lower thickened layer 401. In some embodiments, the thickness T5 of the lower thickened layer 401 and the thickness T6 of the upper thickened layer 403 may be substantially the same. In some embodiments, the thickness T5 of the lower thickened layer 401 and the thickness T6 of the upper thickened layer 403 may be different.

[0115] At this stage, the upper surface 230TS of the word line capping layer 230 may be located at a vertical plane higher than the upper surface 401TS of the lower thickening layer 401 or the upper surface 403TS of the upper thickening layer 403. The section of the word line capping layer 230 located above the lower thickening layer 401 or the upper thickening layer 403 may be referred to as a protruding portion 230P of the word line capping layer 230.

[0116] Please refer to Fig.15, during the third stage of the recess process, the protrusion 230P of the word line cap layer 230 may be selectively removed. This stage may be performed at a predetermined time interval. In some embodiments, the third stage of the recess process may include phosphoric acid to selectively remove the protrusion 230P of the word line cap layer 230. In some embodiments, during the third stage of the recess process, the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be slightly consumed, so that each upper surface 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may also be recessed. In some embodiments, the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be slightly consumed during a cleaning process after the third stage of the recess process.

[0117] In some embodiments, the upper surfaces 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be substantially coplanar. In some embodiments, the upper surface 111TS of the lower cap layer 111 and the upper surface 230TS of the word line cap layer 230 may be substantially coplanar. In some embodiments, the upper surfaces 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be at a vertical plane VL1 lower than the vertical plane VL2 of the upper surface 230TS of the word line cap layer 230. In some embodiments, the upper surfaces 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be at a vertical plane VL1 higher than the vertical plane VL3 of the upper surface 101TS of the substrate 101.

[0118] In some embodiments, the upper surface 111TS of the lower cap layer 111 and the upper surface 230TS of the word line cap layer 230 may be at different vertical planes (not shown). However, the upper surface 111TS of the lower cap layer 111 and the upper surface 230TS of the word line cap layer 230 may be at a higher vertical plane than the upper surfaces 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403.

[0119] In some embodiments, the upper surfaces 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be at different vertical planes (not shown). However, the upper surfaces 210TS, 401TS, 403TS of the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 may be at a vertical plane higher than the upper surface 101TS of the substrate 101.

[0120] In some embodiments, the upper surface 230TS of the word line capping layer 230 may be curved. In other words, the word line capping layer 230 may have a rounded upper surface 230TS. Specifically, the upper surface 230TS of the word line capping layer 230 may include a flat section parallel to the upper surface 101TS of the substrate 101, and both ends of the flat section smoothly transition to curves.

[0121] In some embodiments, the upper surface 111TS of the lower cover layer 111 may be curved. In other words, the lower cover layer 111 may have a rounded upper surface 111TS. Specifically, the upper surface 111TS of the lower cover layer 111 may include a flat section parallel to the upper surface 101TS of the substrate 101, and each end thereof smoothly transitions into a curved form.

[0122] Conventionally, the upper section of the word line dielectric layer 210 may reduce in thickness during processes such as etching back or cleaning, thereby potentially causing gate-induced drain leakage. In contrast, the implementation of the lower thickening layer 401 and the upper thickening layer 403 can enhance the insulation capability of the word line dielectric layer 210 by increasing the thickness of the word line dielectric layer 210. This approach effectively mitigates the problem of gate-induced drain leakage, thereby improving the performance of the semiconductor device 1A.

[0123] Please refer to Figure 1 and Figures 16 to 19 In step S21 , an upper cap layer 113 may be formed on the substrate 101 , and a bit line contact 601 and a plurality of cell contacts 603 may be formed on the substrate 101 .

[0124] Please refer to Fig.16 , the upper cap layer 113 may be formed over the substrate 101 to cover the lower cap layer 111, the word line dielectric layer 210, the lower thickening layer 401, the upper thickening layer 403, and the word line cap layer 230. In some embodiments, for example, the upper cap layer 113 may include a material having an etching selectivity to the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403. In some embodiments, for example, the upper cap layer 113 may include silicon nitride, boron nitride, silicon boron nitride, boron nitride phosphide, silicon boron carbon nitride, or a combination thereof. In some embodiments, the upper cap layer 113 may include silicon nitride. In some embodiments, the upper cap layer 113 may include a material that is the same as the lower cap layer 111. In some embodiments, for example, the fabrication technique of the upper cap layer 113 may include chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0125] Please refer to Fig.17, a bit line contact opening 601O may be formed through the upper cap layer 113 and the lower cap layer 111 and extend to the source region 105S. A cleaning process may be performed after forming the bit line contact opening 601O to remove residues remaining in the bit line contact opening 601O. In the absence of the upper cap layer 113, the cleaning process may corrode the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403. This corrosion has the risk of exposing the source region 105S and / or the drain region 105D. Therefore, when the conductive material is filled to form the bit line contact, a short circuit may occur. In contrast, the presence of the upper cap layer 113 protects the word line dielectric layer 210, the lower thickening layer 401, and the upper thickening layer 403 during the cleaning process, thereby preventing a short circuit.

[0126] Please refer to Fig.18 The bit line contact 601 may be formed in the bit line contact opening 6010 and electrically connected to the source region 105S. In some embodiments, for example, the bit line contact 601 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0127] Please refer to Fig.19 , multiple cell contacts 603 can be formed through the upper cap layer 113 and the lower cap layer 111. Multiple cell contacts 603 can be formed on multiple drain regions 105D respectively. In some embodiments, for example, multiple cell contacts 603 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminum, or a combination thereof. Multiple cell contacts 603 can be electrically connected to multiple drain regions 105D respectively and correspondingly.

[0128] Figure 20 to Figure 22 It is a schematic cross-sectional view illustrating the process of preparing semiconductor elements 1B, 1C, and 1D according to some embodiments of the present disclosure.

[0129] Please refer to Fig. 20 , the semiconductor element 1B may have a similar Fig.19 A structure shown. Fig. 20 Zhongyu Fig.19 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0130] Please refer to Fig. 20, only the upper thickening layer 403 exists. The upper conductive portion 223 may be disposed on the intermediate barrier layer 303. The word line capping layer 230 may be disposed on the upper conductive portion 223. The upper thickening layer 403 may be disposed between the upper conductive portion 223 and the word line capping layer 230 and between the word line dielectric layer 210 and the word line capping layer 230.

[0131] Please refer to Fig.21 , the semiconductor element 1C may have a similar Fig.19 A structure shown. Fig.21 Zhongyu Fig.19 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0132] Please refer to Fig.21 , only the lower thickening layer 401 exists. The word line capping layer 230 may be disposed on the upper conductive portion 223. The lower thickening layer 401 may be disposed between the intermediate barrier layer 303 and the upper conductive portion 223, between the upper conductive portion 223 and the word line dielectric layer 210, and between the word line capping layer 230 and the word line dielectric layer 210.

[0133] Please refer to Fig. 22 , the semiconductor element 1D may have a similar Fig.19 A structure shown. Fig. 22 Zhongyu Fig.19 The same or similar elements have been marked with like element numbers, and repeated descriptions have been omitted.

[0134] In the semiconductor element 1D, before forming the lower thickening layer 401 and the upper thickening layer 403 (for example, before Figure 6 During the etch-back process (as shown), the upper section of the word line dielectric layer 210 may be completely consumed, so that the source region 105S and the drain region 105D may be exposed during the formation of the lower thickening layer 401. Therefore, the lower thickening layer 401 may be disposed between the intermediate barrier layer 303 and the upper conductive portion 223, between (the lower section of) the word line dielectric layer 210, and between the upper thickening layer 403 and the source region 105S (and the drain region 105D).

[0135] An embodiment of the present disclosure provides a semiconductor device, including a substrate; a word line structure, including: a word line dielectric layer, located in the substrate and including a U-shaped cross-sectional profile; a word line conductive layer, located on the word line dielectric layer and located in the substrate; and a word line cap layer, located on the word line conductive layer; an upper thickening layer, including a U-shaped cross-sectional profile, located between the word line conductive layer and the word line cap layer and between the word line dielectric layer and the word line cap layer; a lower cap layer, located on the substrate and adjacent to the word line dielectric layer; and an upper cap layer, covering the lower cap layer and the word line structure. An upper surface of the upper thickening layer and an upper surface of the word line dielectric layer are substantially coplanar, and a vertical plane of the upper surface of the upper thickening layer and the upper surface of the word line dielectric layer is higher than an upper surface of the substrate.

[0136] Another embodiment of the present disclosure provides a semiconductor element, including a substrate; a word line structure, including: a word line dielectric layer, located in the substrate and including a U-shaped cross-sectional profile; a word line conductive layer, a lower conductive portion and an upper conductive portion, the lower conductive portion including a portion located on the word line dielectric layer and located in the substrate, and the upper conductive portion located on the lower conductive portion and located in the substrate; and a word line cap layer, located on the word line conductive layer; a lower thickening layer, including a U-shaped cross-sectional profile, located between the lower conductive portion and the upper conductive portion, between the upper conductive portion and the word line dielectric layer, and between the word line cap layer and the word line dielectric layer; a lower cap layer, located on the substrate and adjacent to the word line dielectric layer; and an upper cap layer, covering the lower cap layer and the word line structure. An upper surface of the lower thickening layer and an upper surface of the word line dielectric layer are substantially coplanar, and a vertical plane of the upper surface of the lower thickening layer and the upper surface of the word line dielectric layer is higher than an upper surface of the substrate. The lower thickening layer comprises a high-k material, an oxide, a nitride, a nitride oxide or a combination thereof.

[0137] Another embodiment of the present disclosure provides a method for preparing a semiconductor device, comprising providing a substrate, forming a lower cover layer on the substrate, and forming a word line groove passing through the substrate and extending to the substrate; conformally forming a word line dielectric layer on the word line groove; forming a lower conductive portion on the word line dielectric layer and in the word line groove; conformally forming a first thickened material layer on the lower conductive portion, the word line dielectric layer and the lower cover layer; forming an upper conductive portion on the first thickened material layer and in the word line groove; The invention relates to a method for forming a word line trench in a conductive layer; conformally forming a second thickening material layer on the upper conductive portion and the first thickening material layer; forming an upper insulating material layer on the second thickening material layer to completely fill the word line trench; removing portions of the second thickening material, the first thickening material and the upper insulating material to respectively form an upper thickening layer, a lower thickening layer and a word line cover layer, while recessing the word line dielectric layer; and forming an upper cover layer to cover the lower cover layer, the word line dielectric layer, the word line cover layer, the lower thickening layer and the upper thickening layer.

[0138] Due to the design of the semiconductor device of the present invention, the thickness of the word line dielectric layer 210 is increased by adding the lower thickening layer 401 and / or the upper thickening layer 403, which can effectively alleviate the drain leakage problem caused by the gate, thereby improving the performance of the semiconductor device 1A. In addition, the upper cap layer 113 shields the word line dielectric layer 210, the lower thickening layer 401 and the upper thickening layer 403 during the etching and / or cleaning process. This protection can prevent these layers from being recessed and potentially exposing the drain region 105D and the source region 105S, thereby avoiding short circuits that may occur due to such exposure.

[0139] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0140] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a base; A character line structure, including: a word line dielectric layer disposed in the substrate and comprising a U-shaped cross-sectional profile; a word line conductive layer, a lower conductive portion and an upper conductive portion, the lower conductive portion including a portion located on the word line dielectric layer and in the substrate, the upper conductive portion located on the lower conductive portion and in the substrate; and a word line cover layer, located on the word line conductive layer; a lower thickening layer including a U-shaped cross-sectional profile, located between the lower conductive portion and the upper conductive portion, between the upper conductive portion and the word line dielectric layer, and between the word line cap layer and the word line dielectric layer; a lower cap layer disposed on the substrate and adjacent to the word line dielectric layer; and an upper cover layer, covering the lower cover layer and the word line structure, wherein an upper surface of the lower thickening layer and an upper surface of the word line dielectric layer are substantially coplanar, and a vertical plane of the upper surface of the lower thickening layer and the upper surface of the word line dielectric layer is higher than an upper surface of the substrate, The lower thickening layer includes a high-k material, an oxide, a nitride, a nitride oxide or a combination thereof.

2. The semiconductor device as claimed in claim 1, further comprising an upper thickening layer, wherein the upper thickening layer comprises a U-shaped cross-sectional profile and is located between the upper conductive portion and the word line capping layer and between the word line capping layer and the lower thickening layer. 3 . The semiconductor device as claimed in claim 2 , wherein an upper surface of the upper thickening layer and an upper surface of the lower thickening layer are substantially coplanar. 4 . The semiconductor device as claimed in claim 2 , wherein a vertical plane of an upper surface of the word line cap layer is higher than the vertical plane of the upper surface of the lower thickening layer. 5 . The semiconductor device as claimed in claim 4 , wherein the upper surface of the word line cap layer is curved. 6 . The semiconductor device as claimed in claim 2 , wherein a vertical plane of an upper surface of the lower cap layer is higher than the vertical plane of the upper surface of the lower thickening layer. 7 . The semiconductor device as claimed in claim 2 , wherein the upper surface of the lower cap layer is curved. 8 . The semiconductor device as claimed in claim 2 , further comprising a lower barrier layer located between the lower conductive portion and the word line dielectric layer. 9 . The semiconductor device as claimed in claim 8 , further comprising an intermediate barrier layer located between the lower conductive portion and the lower thickened layer. 10 . The semiconductor device as claimed in claim 9 , wherein the intermediate barrier layer comprises titanium nitride, titanium, or a combination thereof.

11. A method for preparing a semiconductor element, comprising: Providing a substrate, forming a lower cover layer on the substrate, and forming a word line trench passing through the substrate and extending to the substrate; conformally forming a word line dielectric layer on the word line trench; forming a lower conductive portion on the word line dielectric layer and in the word line trench; Conformally forming a first thickened material layer on the lower conductive portion, the word line dielectric layer and the lower cap layer; forming an upper conductive portion on the first thickened material layer and in the word line trench; conformally forming a second thickened material layer on the upper conductive portion and the first thickened material layer; forming an upper insulating material layer on the second thickened material layer to completely fill the word line trench; removing portions of the second thickening material layer, the first thickening material layer and the upper insulating material layer to form an upper thickening layer, a lower thickening layer and a word line capping layer respectively, while recessing the word line dielectric layer; as well as An upper cap layer is formed to cover the lower cap layer, the word line dielectric layer, the word line cap layer, the lower thickening layer and the upper thickening layer. 12 . The preparation method according to claim 11 , wherein after the word line dielectric layer is recessed, an upper surface of the lower thickening layer, an upper surface of the upper thickening layer, and an upper surface of the word line dielectric layer are substantially coplanar. 13 . The manufacturing method according to claim 12 , wherein after the word line dielectric layer is recessed, a vertical plane of an upper surface of the lower cap layer is higher than a vertical plane of the upper surface of the word line dielectric layer. 14 . The manufacturing method according to claim 12 , wherein after the word line dielectric layer is recessed, a vertical plane of an upper surface of the word line cap layer is higher than a vertical plane of the upper surface of the word line dielectric layer. The manufacturing method as claimed in claim 12 , wherein the lower cover layer and the upper cover layer comprise the same material. The preparation method as claimed in claim 12 , wherein the upper thickening layer and the lower thickening layer comprise the same material.

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