Fault protection method, circuit, device and storage medium

Abstract

The present invention discloses a fault protection method, circuit, device and storage medium, the method comprising: verifying the acquired fault signal to generate a verification signal; performing a logical operation on the verification signal to generate a protection request; and executing a corresponding fault protection action in response to the protection request to verify the fault signal and improve the accuracy of fault protection. The circuit comprises a main control module to verify the acquired fault signal to generate a verification signal; a logic gate module to receive the verification signal and perform a logical operation on the verification signal to generate a protection request; and a fault protection module to execute a corresponding fault protection action in response to the protection request to improve the efficiency of fault protection.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a fault protection method, circuit, device and storage medium. Background Art

[0002] At present, with the rapid development of technology, higher requirements are put forward for the safety of electronic power systems. At the same time, improving the efficiency and accuracy of fault detection is becoming increasingly prominent in improving the safety of the electronic power systems.

[0003] In the process of fault detection, the existing electronic power system usually receives fault signals from multiple fault detection sources through the main control chip of the system, and performs algorithm judgment on the fault signals to achieve fault detection. After detecting the fault signal, the corresponding action signal is sent to the corresponding actuator to control the actuator to perform actions such as resetting, shutting down, switching working modes, etc. to complete fault protection.

[0004] However, the above fault detection and protection method is limited by the main frequency of the main control chip and the code complexity of the logic algorithm, resulting in a long response time for a single fault. Furthermore, the main control chip does not detect the fault signal. If the fault signal has noise or the main control module is interfered, the main control chip may output an erroneous action signal, causing the actuator to perform an erroneous protection action. Summary of the invention

[0005] The purpose of the present invention is to provide a fault protection method, circuit, device and storage medium to solve the technical problem that the prior art relies on a main control module for fault protection, resulting in low fault protection efficiency or inaccurate fault protection.

[0006] In order to achieve the above object, in a first aspect, the present invention discloses a fault protection method, comprising:

[0007] Verifying the acquired fault signal and generating a verification signal;

[0008] Performing a logic operation on the verification signal to generate a protection request;

[0009] In response to the protection request, a corresponding fault protection action is executed.

[0010] A fault protection method disclosed in the present invention first verifies the acquired fault signal and then generates a verification signal to avoid erroneous protection action caused by an erroneous fault signal. Next, the verification signal is used to perform logical operations to generate a protection request corresponding to the fault signal, and then the protection request is responded to and the corresponding protection action is executed to improve the accuracy of the fault protection action.

[0011] As a preferred example, the step of verifying the acquired fault signal and generating a verification signal includes:

[0012] Determining whether the fault signal is a valid signal;

[0013] When it is determined that the fault signal is a valid signal, a verification signal corresponding to the fault signal is generated.

[0014] The present invention performs validity check on the fault signal to avoid erroneous protection action caused by erroneous fault signal, thereby improving the accuracy of fault protection.

[0015] As a preferred example, performing a logical operation on the verification signal to generate a protection request includes:

[0016] Performing a logical operation on the verification signal to obtain a fault type corresponding to the fault signal;

[0017] The protection request is generated according to the fault type.

[0018] The present invention performs a logical operation on the fault signal to execute a corresponding fault protection action according to the precise fault type, thereby improving the accuracy of the fault protection.

[0019] In a second aspect, the present invention discloses a fault protection circuit, comprising a main control module, a logic gate module and a fault protection module; wherein the output end of the main control module is electrically connected to the input end of the logic gate module; the output end of the logic gate module is electrically connected to the input end of the fault protection module;

[0020] The main control module is used to verify the acquired fault signal, generate a verification signal, and send the verification signal to the logic gate module;

[0021] The logic gate module receives the verification signal, and performs a logic operation on the verification signal to generate a protection request and sends the protection request to the fault protection module;

[0022] The fault protection module executes a corresponding fault protection action in response to the protection request.

[0023] The present invention discloses a fault protection circuit, in which a main control module is set to check only the fault signal, so as to avoid erroneous protection actions caused by fault signal errors, thereby improving the accuracy of fault protection. Furthermore, a logic gate module is set to perform logical operations on the check signal to generate a protection request corresponding to the fault type, which not only solves the technical problem of low operation efficiency caused by the main control chip performing logical operations, but also solves the technical problem of the main control chip being susceptible to interference and causing protection request errors. Thus, the fault protection module executes the corresponding fault protection action using the protection request output by the logic gate module, which not only improves the efficiency of fault protection, but also improves the accuracy of fault protection.

[0024] As a preferred example, the logic gate module includes a plurality of OR gates; wherein each of the OR gates includes a first input terminal, a second input terminal and a first output terminal;

[0025] The first input end of each of the OR gates is connected to the output end of the main control module, and is used to perform a logic operation on the check signal to obtain the fault type corresponding to the fault signal, and generate the protection request according to the fault type; wherein different OR gates output protection requests corresponding to different fault types;

[0026] The first output terminal of each of the OR gates is connected to the input terminal of the fault protection module, and is used to send the protection request to the fault protection module.

[0027] The present invention sets different OR gates for detecting different fault types, and then outputs corresponding protection requests to improve the accuracy of the protection requests.

[0028] As a preferred example, the logic gate module includes a plurality of AND gates, and the AND gates correspond to the OR gates one by one; wherein each of the AND gates includes a third input terminal, a fourth input terminal and a second output terminal;

[0029] The third input terminal of each AND gate is connected to the first output terminal of the corresponding OR gate, so as to respond to the protection request;

[0030] According to the protection request, the fourth input terminal of each AND gate is used to receive the fault signal.

[0031] The present invention sets an AND gate corresponding to the OR gate in a one-to-one manner in the logic gate module, wherein the input end of the AND gate is connected to the output end of the OR gate, so that when the OR gate outputs a protection request, the AND gate receives the fault signal to pull up the signal of the channel between the AND gate and the OR gate to maintain the signal.

[0032] As a preferred example, the second output terminal of each of the AND gates is connected to the corresponding second input terminal of the OR gate to maintain the fault signal.

[0033] The present invention connects the output end of the AND gate with the input end of the OR gate, so that after the OR gate triggers the fault protection module, the signal position is carried out through the AND gate until the fault is cleared, thereby improving the effect of fault protection.

[0034] As a preferred example, the verification signal is a pulse signal.

[0035] The present invention sets the check signal as a pulse signal, which can instantaneously pull up the OR gate of the logic gate module to trigger the fault protection module to perform a protection action and the AND gate to perform signal maintenance, thereby improving the efficiency of fault protection.

[0036] In a third aspect, the present invention discloses a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the fault protection method described in the first aspect when executing the computer program.

[0037] In a fourth aspect, the present invention discloses a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the fault protection method described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 : A flowchart of a fault protection method provided by an embodiment of the present invention;

[0039] Figure 2 : A structural diagram of a fault protection circuit provided by an embodiment of the present invention;

[0040] Figure 3 : A structural schematic diagram of a fault protection circuit provided by another embodiment of the present invention;

[0041] Figure 4 : A schematic diagram of the circuit structure of a logic gate group provided for another embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] Below, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0046] Embodiment 1

[0047] like Figure 1 As shown, Figure 1 1 is a flow chart of a fault protection method provided in an embodiment of the present application. The fault protection method includes steps 101 to 103, and the steps are mainly:

[0048] Step 101: verify the acquired fault signal to generate a verification signal.

[0049] In this embodiment, this step mainly includes: determining whether the fault signal is a valid signal; and when the fault signal is determined to be a valid signal, generating a verification signal corresponding to the fault signal.

[0050] Specifically, the fault signal does not limit the fault type, source and quantity. In practical applications, the fault signal may be single-channel or multi-channel. The fault signal may be a signal when the current is too large, a signal when the voltage is too large, a signal when the load is too large, a signal when the temperature is too high, and other types of fault signals. Furthermore, the fault signal can be obtained through various devices for fault signal collection, such as voltage or current detection circuits, temperature sensors, and load monitors.

[0051] This step verifies the validity of the fault signal to avoid erroneous protection actions caused by erroneous fault signals, thereby improving the accuracy of fault protection.

[0052] Step 102: Perform a logical operation on the verification signal to generate a protection request.

[0053] In this embodiment, this step mainly includes: performing a logical operation on the check signal to obtain a fault type corresponding to the fault signal; and generating the protection request according to the fault type.

[0054] Specifically, based on the different types of the fault signal, the corresponding fault protection actions are also different. The fault protection actions include resetting, shutting down, switching working modes, etc. to perform fault protection.

[0055] This step performs a logical operation on the fault signal to execute a corresponding fault protection action according to the precise fault type, thereby improving the accuracy of the fault protection.

[0056] Step 103: In response to the protection request, execute a corresponding fault protection action.

[0057] On the other hand, refer to Figure 2 This embodiment also discloses a fault protection circuit, which includes a main control module 201, a logic gate module 202 and a fault protection module 203. The output end of the main control module 201 is electrically connected to the input end of the logic gate module 202; the output end of the logic gate module 202 is electrically connected to the input end of the fault protection module 203.

[0058] The main control module 201 is used to verify the acquired fault signal, generate a verification signal, and send the verification signal to the logic gate module 202 .

[0059] The logic gate module 202 receives the verification signal, and performs a logic operation on the verification signal to generate a protection request and sends the protection request to the fault protection module 203 .

[0060] The fault protection module 203 executes a corresponding fault protection action in response to the protection request.

[0061] In this embodiment, in order to obtain the fault type corresponding to the fault signal according to the verification signal, preferably, a plurality of OR gates can be set in the logic gate module 202; wherein each of the OR gates includes a first input terminal, a second input terminal and a first output terminal; the first input terminal of each of the OR gates is connected to the output terminal of the main control module 201, and is used to perform a logical operation on the verification signal, obtain the fault type corresponding to the fault signal, and generate the protection request according to the fault type; wherein different OR gates output protection requests corresponding to different fault types; the first output terminal of each of the OR gates is connected to the input terminal of the fault protection module 203, and is used to send the protection request to the fault protection module 203, so that different fault types can be detected by different OR gates, and then the corresponding protection requests are output, so as to improve the accuracy of the protection request.

[0062] Furthermore, when the OR gate outputs a protection request, in order to maintain the fault signal to complete the fault protection, preferably, a plurality of AND gates are set in the logic gate module 202, and the AND gates correspond to the OR gates one by one; wherein each of the AND gates includes a third input terminal, a fourth input terminal and a second output terminal; the third input terminal of each of the AND gates is connected to the first output terminal of the corresponding OR gate for responding to the protection request; according to the protection request, the fourth input terminal of each of the AND gates is used to receive the fault signal to maintain the fault signal.

[0063] In this embodiment, an AND gate corresponding to the OR gate is set in the logic gate module, so that when the OR gate outputs a protection request, the AND gate receives the fault signal to pull up the signal of the channel between the AND gate and the OR gate to maintain the signal.

[0064] Furthermore, in order to maintain the fault signal, the second output terminal of each of the AND gates is connected to the second input terminal of the corresponding OR gate.

[0065] In this embodiment, in order to improve the efficiency of fault protection, it is preferred to set the check signal as a pulse signal, so that the pulse signal can instantaneously pull up the OR gate of the logic gate module to trigger the fault protection module to perform a protection action and the AND gate to maintain the signal, thereby improving the efficiency of fault protection.

[0066] Accordingly, this embodiment provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the fault protection method when executing the computer program. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The processor is the control center of the terminal, and various interfaces and lines are used to connect various parts of the entire terminal. The memory may be used to store the computer program, and the processor implements various functions of the terminal by running or executing the computer program stored in the memory and calling the data stored in the memory. The memory may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Med ia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0067] Correspondingly, this embodiment further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the fault protection method.

[0068] Wherein, if the module integrated with the fault protection circuit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, all or part of the processes in the above-mentioned embodiment method can also be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiments can be implemented. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0069] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0070] The present embodiment provides a fault protection method and circuit, in which a main control module is set to check only the fault signal, so as to avoid erroneous protection actions caused by fault signal errors, thereby improving the accuracy of fault protection. Furthermore, a logic gate module is set to perform logical operations on the check signal to generate a protection request corresponding to the fault type, which not only solves the technical problem of low computing efficiency caused by the limitation of the main control module to perform logical operations, but also solves the technical problem of the main control module being susceptible to interference and causing protection request errors. Thus, the fault protection module executes the corresponding fault protection action using the protection request output by the logic gate module, which not only improves the efficiency of fault protection, but also improves the accuracy of fault protection.

[0071] Embodiment 2

[0072] Reference Figure 3 , is a schematic diagram of a structure of a fault protection circuit provided in this embodiment. Specifically, the fault protection circuit includes a main control chip 301, a logic gate group 302 and an actuator 303.

[0073] Reference Figure 3 The output end of the main control chip is connected to the input end of the logic gate group 302 for receiving a fault signal and performing validity verification on the fault signal to generate a main control chip verification signal, and send the main control chip verification signal to the logic gate group 302.

[0074] The output end of the logic gate group 302 is electrically connected to the input end of the actuator 303, and is used to perform logic operations on the main control chip verification signal, identify the fault type contained in the main control chip verification signal, and output a corresponding protection request to the actuator 303 according to the fault type.

[0075] The executor 303 executes a fault protection action corresponding to the fault type according to the protection request.

[0076] Reference Figure 3 In the fault protection circuit shown, the source, type and quantity of the fault signal received by the main control chip 301 are not limited, that is, the main control chip 301 can receive multiple fault signals of different types at the same time.

[0077] In some implementations of this embodiment, it is assumed that four independent groups of fault signals are sent to the main control chip 301 at the same time. The four independent fault signals do not limit the fault type and source. In practical applications, the fault type is usually too large current, too large voltage, too large load, too large temperature, etc.; the source is usually voltage or current detection circuit, temperature sensor, load monitor, etc.

[0078] At this time, the fault signal does not need to perform logical operation after entering the main control chip 301. The main control chip 301 only needs to check whether each fault signal is valid, and after judging whether the fault signal is valid, generate the main control chip verification signal corresponding to the four groups of fault signals, and send it to the logic gate group 302.

[0079] Furthermore, after the logic gate group 302 receives the verification signal of the main control chip, it performs a logic operation to trigger the actuator 203 to perform a corresponding fault protection action. Specifically, the logic gate group 302 needs to determine the fault type corresponding to each fault signal according to the verification signal of the main control chip to trigger the actuator 203 to perform a precise fault protection action according to the fault type, and when the actuator 203 performs the protection action, maintain the stability of the fault signal to ensure that it is not interrupted before the actuator 203 completes the fault protection. In this regard, in some implementations of this embodiment, the logic gate group 302 is formed by a plurality of AND gates and a plurality of OR gates connected in series. Among them, different OR gates are used to detect different types of fault signals.

[0080] Specifically, refer to Figure 4, when the fault signals processed by the main control chip are four groups of fault signals, and the types corresponding to the fault signals are all different. The logic gate group is set to include four independent AND gates and four independent OR gates, and each OR gate corresponds to a fault type. Among them, the number of the AND gates and the OR gates is not limited, depending on the number of the fault signals. For example, when the main control chip processes three groups of fault signals or five groups of fault signals, the logic gate group includes three or five independent AND gates and three or five independent OR gates. However, the AND gates and the OR gates need to correspond one to one to ensure the stability of the path.

[0081] Reference Figure 4 Taking fault signal 1, fault signal 2, fault signal 3, and fault signal 4 as four independent fault signals as an example, four independent AND gates and four independent OR gates need to be set in the logic gate group 302; wherein each OR gate is used to diagnose one of the four independent fault signals.

[0082] Specifically, refer to Figure 4 , set OR gate 1 to diagnose fault No. 1 corresponding to fault signal 1, OR gate 2 to diagnose fault No. 2 corresponding to fault signal 2, OR gate 3 to diagnose fault No. 3 corresponding to fault signal 3, and OR gate 4 to diagnose fault No. 4 corresponding to fault signal 4. In order to save space occupied by logic circuits, the OR gates 1 and 2 can be combined to form U2; the OR gates 3 and 4 can be combined to form U3.

[0083] In certain embodiments of this example, Figure 3 In order to detect the fault type and trigger the corresponding protection action, the first input ends of the OR gates 1, 2, 3 and 4 in the logic gate group shown, i.e., 1B and 2B in U2 and 1B and 2B in U3, are connected to the input end of the main control chip 301, for receiving the main control chip verification signal output by the main control chip 301 for logic operation.

[0084] Specifically, when the OR gate 1, OR gate 2, OR gate 3, or gate 4 identifies the fault type of the main control chip check signal, when the corresponding No. 1 fault, No. 2 fault, No. 3 fault, or No. 4 fault in the OR gate 1, OR gate 2, OR gate 3, or gate 4 is activated, the output end of the OR gate 1, OR gate 2, OR gate 3, or gate 4, that is, 1Y and 2Y in the U2 and U3, is connected to the input end of the actuator 303, which is used to send the activated signal to the actuator 303, so that the actuator 303 performs a fault protection action corresponding to the type of the fault signal. Preferably, the actuator 303 performs different fault protection actions such as resetting, shutting down, switching working modes, etc. according to the type of the fault signal.

[0085] Furthermore, when the actuator 303 is triggered, in order to ensure that the actuator 303 continues to execute the fault protection action until the fault signal received by the main control chip 301 is cleared, the logic gate group needs to be set to maintain the fault signal until the fault signal stored in the OR gate is no longer triggered.

[0086] In certain implementations of this embodiment, reference Figure 4 , set AND gates corresponding to the OR gates one by one, and connect each AND gate to the corresponding OR gate to form a circuit for maintaining the fault signal. Specifically, taking fault signal 1, fault signal 2, fault signal 3, and fault signal 4 as four independent fault signals, it can be seen that four independent OR gates are set. Based on the setting of the OR gate, four independent AND gates are selected. Among them, the AND gate includes U1 composed of AND gate 1, AND gate 2, AND gate 3, and AND gate 4. In order to ensure the path connection between the AND gate and the OR gate, refer to Figure 4 The output terminal 1Y of the AND gate 1 is connected to the input terminal 1A of the OR gate 1, the output terminal 2Y of the AND gate 2 is connected to the input terminal 2A of the OR gate 2, the output terminal 3Y of the AND gate 3 is connected to the input terminal 1A of the OR gate 3, and the output terminal 4Y of the AND gate 4 is connected to the input terminal 2A of the OR gate 4.

[0087] The connection between the output terminal of the AND gate and the input terminal of the OR gate is used to maintain the signal. In order for the AND gate to respond to the protection request output by the OR gate in time, the signal can be maintained in time. Figure 4 The output terminal 1Y of the OR gate 1 is connected to the input terminal 1A of the AND gate 1, the output terminal 2Y of the OR gate 2 is connected to the input terminal 2A of the AND gate 2, the output terminal 1Y of the OR gate 3 is connected to the input terminal 3A of the AND gate 3, and the output terminal 2Y of the OR gate 4 is connected to the input terminal 4A of the AND gate 4.

[0088] Reference Figure 4 From the connection between the AND gate and the OR gate, it can be seen that when the fault signal in the OR gate is activated, the AND gate can respond to the protection request in time, and then receive the feedback fault signal through 1B, 2B, 3B, and 4B of U1, and then pull up the signal of the corresponding channel of U1 to maintain the signal.

[0089] In certain implementations of this embodiment, the logic gate group 302 performs verification based on the signal sent by the main control chip 301. In order to improve the response efficiency of the logic gate group 302 to the signal, the main control chip calibration signal sent by the main control chip 301 is preferably set to a pulse signal. The pulse signal can instantly pull up U2 and U3 and then trigger the actuator and U1 and then maintain a low potential.

[0090] Specifically, taking the example that four independent AND gates and four independent OR gates constitute the logic gate group 302 and the signal sent by the main control chip 301 is a pulse signal, the truth table of the logic operation performed by the OR gate in the logic gate group 302 can refer to Table 1. Table 1 is as follows:

[0091]

[0092]

[0093] As described in Table 1, after receiving the fault signal sent by the multiple fault signal transmission sources, the main control chip 301 performs validity check and generates corresponding pulse signals according to the true value corresponding to the fault signal. Referring to Table 1, when the true values ​​of the fault signal 1, fault signal 2, fault signal 3, and fault signal 4 are 1, 0, 0, and 0 respectively, it means that at this time, the fault signal 1 is true and there is a fault No. 1, then the main control chip 301 generates the corresponding true value 1. Then, different OR gates are used to identify the fault type of the signal sent by the main control chip 301, triggering the fault No. 1 set in the OR gate 1, and realizing the identification of the fault No. 1.

[0094] In this embodiment, refer to Figure 3 to Figure 4 The fault protection circuit, after a fault occurs, first checks the fault signal through the main control chip 301, then triggers the actuator through the OR gate of the logic gate, and then maintains the signal through the AND gate. When the fault is cleared, the fault signal is cleared, the OR gate signal is cleared, and fault protection is achieved.

[0095] Compared with the prior art, this embodiment has the following beneficial effects:

[0096] The fault protection circuit provided in this embodiment is composed of a plurality of AND gates and OR gates to form a logic gate circuit with signal transmission and reset, and then performs logic operations through the logic gate circuit, so that the response delay of the fault protection circuit is only related to the delay of the logic gate chip (usually ranging from 10ns to 500ns), and due to the main frequency of the main control chip and the complexity of the code, the delay caused by the logic judgment of the main control chip is at least more than 1ms. Therefore, the response speed of the fault protection circuit is greatly improved compared with the traditional method of performing logic judgment through the main control chip.

[0097] Furthermore, the fault protection circuit provided in this embodiment adopts a method of mutual verification between the main control chip and the logic gate circuit to perform circuit protection. The traditional method of performing logical judgment only through the main control chip may cause erroneous actions due to erroneous fault signals or interference with the main control chip. The mutual verification method can effectively avoid this situation and improve the accuracy of fault protection.

[0098] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fault protection method, characterized in that: include: Verifying the acquired fault signal and generating a verification signal; Performing a logic operation on the verification signal to generate a protection request; In response to the protection request, a corresponding fault protection action is executed.

2. A fault protection method according to claim 1, characterized in that: The step of verifying the acquired fault signal and generating a verification signal includes: Determining whether the fault signal is a valid signal; When it is determined that the fault signal is a valid signal, a verification signal corresponding to the fault signal is generated.

3. A fault protection method according to claim 2, characterized in that: The performing a logical operation on the verification signal to generate a protection request includes: Performing a logical operation on the verification signal to obtain a fault type corresponding to the fault signal; The protection request is generated according to the fault type.

4. A fault protection circuit, characterized in that: It includes a main control module, a logic gate module and a fault protection module; wherein the output end of the main control module is electrically connected to the input end of the logic gate module; the output end of the logic gate module is electrically connected to the input end of the fault protection module; The main control module is used to verify the acquired fault signal, generate a verification signal, and send the verification signal to the logic gate module; The logic gate module receives the verification signal, and performs a logic operation on the verification signal to generate a protection request and sends the protection request to the fault protection module; The fault protection module executes a corresponding fault protection action in response to the protection request.

5. A fault protection circuit according to claim 4, characterized in that: The logic gate module includes a plurality of OR gates; wherein each of the OR gates includes a first input terminal, a second input terminal and a first output terminal; The first input end of each of the OR gates is connected to the output end of the main control module, and is used to perform a logic operation on the check signal to obtain the fault type corresponding to the fault signal, and generate the protection request according to the fault type; wherein different OR gates output protection requests corresponding to different fault types; The first output terminal of each of the OR gates is connected to the input terminal of the fault protection module, and is used to send the protection request to the fault protection module.

6. A fault protection circuit according to claim 5, characterized in that: The logic gate module includes a plurality of AND gates, and the AND gates correspond to the OR gates one by one; wherein each of the AND gates includes a third input terminal, a fourth input terminal and a second output terminal; The third input terminal of each AND gate is connected to the first output terminal of the corresponding OR gate, so as to respond to the protection request; According to the protection request, the fourth input terminal of each of the AND gates is used to receive the fault signal to maintain the fault signal.

7. A fault protection circuit according to any one of claims 5-6, characterized in that: The second output terminal of each AND gate is connected to the second input terminal of the corresponding OR gate.

8. A fault protection circuit according to claim 4, characterized in that: The verification signal is a pulse signal.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the fault protection method according to any one of claims 1 to 3 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the fault protection method according to any one of claims 1 to 3 is implemented.

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