Electrostatic and surge integrated protection circuit suitable for high-frequency and high-speed interface chip

Abstract

The invention discloses an electrostatic surge integrated protection circuit suitable for a high-frequency and high-speed interface chip, and relates to the technical field of integrated circuit design. A plurality of trigger and bleeder circuits are formed by a resistor R1, a resistor R2, a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor M1 and a transistor M2; a low-capacitance and high-integration electrostatic surge integrated bleeder circuit can be formed; according to the invention, the parasitic capacitance can be reduced by adjusting key characteristic parameters and chip areas in different trigger and bleeder circuits, so that the trigger starting and current bleeding functions of interface chips with different working frequencies and data bandwidths are realized, the influence of electrostatic surge pulses on the performance of the protected interface chip is avoided, and the reliability of the interface chip is improved. The problems of circuit damage and the like caused by instant pulses of multi-type high-frequency and high-speed interface chips with different processes, different power domains and different application scenes can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips. Background Art

[0002] Electrostatic discharge (ESD) is the charge transfer phenomenon caused by the potential difference between two objects in contact or close to each other, which will generate a huge instantaneous current and voltage in a very short time. Surge, also known as electrical over stress (EOS), is an instantaneous overvoltage that exceeds the normal working voltage caused by lightning strikes and the start and stop of electronic equipment. When the surge voltage or current exceeds the maximum withstand voltage of the chip port, EOS will occur in the chip. The failure caused by EOS is very similar to that caused by ESD, which will manifest as internal short circuit, open circuit, deterioration of performance parameters or even non-function of the chip. The risk of ESD / EOS events runs through the entire life cycle of the chip. With the continuous improvement of integrated circuit technology, the minimum line width of the chip is constantly reduced, and the ESD / EOS protection performance of the chip is deteriorating more and more seriously. The process of high-frequency and high-speed interface chips is constantly shrinking, and the operating frequency is constantly increasing, and the signal transmission speed is constantly increasing. High-speed interface chips are becoming more and more sensitive to the parasitic capacitance introduced by traditional ESD or EOS protection circuit units, and the ESD / EOS protection of high-frequency and high-speed interface chips is becoming more and more difficult.

[0003] The triode and MOS tube structures used in traditional ESD / EOS protection units have the disadvantages of high trigger voltage, large parasitic capacitance, large chip area, and weak ESD robustness of the circuit per unit area. The thyristor (Silicon Controlled Rectifier, SCR) structure has attracted extensive attention in the industry due to its strong ESD robustness per unit area. However, since the trigger voltage of the SCR structure is too high and it is easy to produce latch-up effect, it is difficult to control the voltage hysteresis amplitude generated during the ESD / EOS protection process. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips, including a dual NPN transistor trigger leakage circuit, a dual PNP transistor trigger leakage circuit, a resistor string PMOS trigger leakage circuit, a resistor string NMOS trigger leakage circuit and a dual bias SCR trigger leakage circuit; The electrostatic surge integrated protection circuit is composed of a P-type substrate, a high-voltage N-well, an N-well, a P-well, a first N+ injection region, a first P+ injection region, a second P+ injection region, a third P+ injection region, a fourth P+ injection region, a second N+ injection region, a third N+ injection region, a fifth P+ injection region, a fourth N+ injection region, a fifth N+ injection region, a sixth N+ injection region, a first P-type polysilicon gate, and a second N-type polysilicon gate; The dual NPN transistor trigger leakage circuit is composed of transistor T5 and transistor T6; the dual PNP transistor trigger leakage circuit is composed of transistor T3 and transistor T4; the resistor string PMOS trigger leakage circuit is composed of resistor Rp and transistor M1; the resistor string NMOS trigger leakage circuit is composed of resistor Rn and transistor M2; the dual bias SCR trigger leakage circuit is composed of resistor Rp, resistor Rn, transistor T1 and transistor T2; The resistor Rn is a parasitic resistor formed by the first N+ injection region and the N-well; the resistor Rp is a parasitic resistor formed by the fifth P+ injection region and the P-well; the transistor M1 is formed by the third P+ injection region, the first P-type polysilicon gate, the N-well and the fourth P+ injection region; the transistor M2 is formed by the second N+ injection region, the second N-type polysilicon gate, the P-well and the third N+ injection region; the transistor T1 is formed by the second P+ injection region, the N-well and the P-well; the transistor T2 is formed by the N-well, the P-well and the second N+ injection region; the transistor T3 is formed by the first P+ injection region, the N-well and the second P+ injection region; the transistor T4 is formed by the third P+ injection region, the N-well and the second P+ injection region; the transistor T5 is formed by the fifth N+ injection region, the P-well and the sixth N+ injection region; the transistor T6 is formed by the fifth N+ injection region, the P-well and the fourth N+ injection region; The collector of transistor T6, the collector of transistor T5, the source of transistor M1, the emitter of transistor T1, the emitter of transistor T3, the emitter of transistor T4 and one end of resistor Rn are all connected to the anode of the electrostatic surge integrated protection circuit; the substrate electrode of transistor M1, the base of transistor T1, the base of transistor T3, the base of transistor T4, the drain of transistor M2 and the collector of transistor T2 are all connected to the other end of resistor Rn; One end of the resistor Rp, the emitter of the transistor T6, the emitter of the transistor T5, the emitter of the transistor T2, the drain of the transistor M2, the gate of the transistor M2, the collector of the transistor T3 and the collector of the transistor T4 are all connected to the cathode of the electrostatic surge integrated protection circuit; the base of the transistor T6, the base of the transistor T5, the drain of the transistor M1, the collector of the transistor T1, the base of the transistor T2 and the substrate electrode of the transistor M2 are all connected to the other end of the resistor Rp.

[0005] The technical solution further defined in the present invention is: Furthermore, when electrostatic surge stress acts between the anode and cathode of the electrostatic surge integrated protection circuit, the resistor Rp and the transistor M1 form a first auxiliary trigger path, and the resistor Rn and the transistor M2 form a second auxiliary trigger path. The leakage current formed by the first auxiliary trigger path and the second auxiliary trigger path increases the voltage drop across the resistor Rp and the resistor Rn, thereby realizing the orderly triggering of the first auxiliary trigger path and the second auxiliary trigger path to turn on the electrostatic surge integrated protection circuit.

[0006] As described above, in an integrated electrostatic surge protection circuit suitable for a high-frequency and high-speed interface chip, when the voltage drop across the resistor Rp and the resistor Rn is greater than or equal to 0.7V, the emitter junctions of the transistors T6, T5, T2, T1, T3 and T4 are forward-conducted, and the dual NPN transistor-triggered leakage circuit and the dual PNP transistor-triggered leakage circuit amplify the current, thereby enhancing the leakage capacity of the integrated electrostatic surge protection circuit.

[0007] As described above, an electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips, as the electrostatic surge stress continues to increase, the dual NPN transistor trigger leakage circuit and the dual PNP transistor trigger leakage circuit promote the increase of the base current and collector current of transistor T1 and transistor T2 through positive feedback, thereby further promoting the electrostatic surge integrated protection circuit to achieve a large surge current discharge function under the promotion of the dual bias SCR trigger leakage circuit.

[0008] As described above, an integrated electrostatic surge protection circuit suitable for a high-frequency and high-speed interface chip, a resistor string PMOS trigger leakage circuit and a resistor string NMOS trigger leakage circuit, and a highly integrated surface shallow junction auxiliary trigger circuit composed of a dual NPN transistor trigger leakage circuit and a dual PNP transistor trigger leakage circuit reduce the parasitic capacitance of the integrated electrostatic surge protection circuit and avoid the integrated electrostatic surge protection circuit from causing signal interference or performance degradation to the protection chip.

[0009] As described above, in an integrated electrostatic surge protection circuit suitable for a high-frequency and high-speed interface chip, the high-voltage N-well is replaced by an N-type buried layer.

[0010] The beneficial effects of the present invention are: (1) In the present invention, when electrostatic surge stress acts between the anode and cathode of the electrostatic surge integrated protection circuit, the resistor Rp and the transistor M1 form a first auxiliary trigger path, and the resistor Rn and the transistor M2 form a second auxiliary trigger path. The leakage current formed by the first auxiliary trigger path and the second auxiliary trigger path increases with the increase of electrical stress, thereby increasing the voltage drop across the resistors Rp and Rn. When the voltage drop across the resistors Rp and Rn is greater than or equal to 0.7V, the first auxiliary trigger path and the second auxiliary trigger path will quickly trigger and turn on the electrostatic surge integrated protection circuit, thereby increasing the electrostatic surge electrical stress response speed and reducing the trigger voltage. The resistors Rp and Rn can also protect the gate oxides of the transistors M1 and M2, thereby reducing the risk of breakdown damage to the gate oxide layer of the transistors. (2) In the present invention, as the electrostatic surge stress continues to increase, under the current amplification effect of the dual NPN transistor trigger leakage circuit and the dual PNP transistor trigger leakage circuit, the base current and collector current of transistor T1 and transistor T2 are further increased, and the current amplification capability of the electrostatic surge integrated protection circuit is driven by the dual bias SCR trigger leakage circuit to achieve a large surge current discharge function, thereby obtaining a gradually turned on and orderly triggered electrostatic and surge integrated protection performance; (3) In the present invention, under the action of instantaneous high-frequency strong pulse electrostatic surge stress, the resistor string MOS trigger leakage circuit and the highly integrated surface shallow junction auxiliary trigger circuit composed of a dual NPN transistor trigger leakage circuit and a dual PNP transistor trigger leakage circuit can reduce the parasitic capacitance of the electrostatic surge integrated protection circuit, avoid the electrostatic surge integrated protection circuit from generating parasitic capacitance on the protection chip, causing signal attenuation of the high-frequency high-speed interface chip, reduce the bit error rate, and solve the problems of insufficient electrostatic and surge protection capabilities of high-frequency high-speed interface chips, and signal attenuation and performance degradation caused by traditional electrostatic and surge protection circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the overall structure of the present invention; Figure 2 : is an equivalent circuit diagram of an electrostatic surge integrated protection circuit in an embodiment of the present invention; Figure 3 Schematic diagram of a resistor string MOS triggering leakage circuit in an embodiment of the present invention; Figure 4 Schematic diagram of a dual-transistor triggered bleeder circuit in an embodiment of the present invention.

[0012] Wherein: 100, P-type substrate; 101, high-voltage N-well; 102, N-well; 103, P-well; 104, first N+ injection region; 105, first P+ injection region; 106, second P+ injection region; 107, third P+ injection region; 108, fourth P+ injection region; 109, second N+ injection region; 110, third N+ injection region; 111, fifth P+ injection region; 112, fourth N+ injection region; 113, fifth N+ injection region; 114, sixth N+ injection region; 115, first P-type polysilicon gate; 116, second N-type polysilicon gate. DETAILED DESCRIPTION

[0013] This embodiment provides an integrated electrostatic surge protection circuit suitable for high-frequency and high-speed interface chips, such as Figure 1 As shown, it includes a P-type substrate 100, an N-type buried layer or a high-voltage N-well 101, an N-well 102, a P-well 103, a first N+ injection region 104, a first P+ injection region 105, a second P+ injection region 106, a third P+ injection region 107, a fourth P+ injection region 108, a second N+ injection region 109, a third N+ injection region 110, a fifth P+ injection region 111, a fourth N+ injection region 112, a fifth N+ injection region 113, a sixth N+ injection region 114, a first P-type polysilicon gate 115 and a second N-type polysilicon gate 116.

[0014] The integrated electrostatic surge protection circuit includes a resistor string MOS trigger leakage circuit, a dual transistor trigger leakage circuit and a dual bias SCR trigger leakage circuit, wherein the resistor string MOS trigger leakage circuit includes a resistor string PMOS trigger leakage circuit and a resistor string NMOS trigger leakage circuit, and the dual transistor trigger leakage circuit includes a dual NPN transistor trigger leakage circuit and a dual PNP transistor trigger leakage circuit.

[0015] The dual NPN transistor trigger leakage circuit is composed of transistor T5 and transistor T6; the dual PNP transistor trigger leakage circuit is composed of transistor T3 and transistor T4; the resistor string PMOS trigger leakage circuit is composed of resistor Rp and transistor M1; the resistor string NMOS trigger leakage circuit is composed of resistor Rn and transistor M2; the dual bias SCR trigger leakage circuit is composed of resistor Rp, resistor Rn, transistor T1 and transistor T2.

[0016] The resistor Rn is a parasitic resistor formed by the first N+ implantation region 104 and the N-well 102; the resistor Rp is a parasitic resistor formed by the fifth P+ implantation region 111 and the P-well 103; the transistor M1 is formed by the third P+ implantation region 107, the first P-type polysilicon gate 115, the N-well 102 and the fourth P+ implantation region 108; the transistor M2 is formed by the second N+ implantation region 109, the second N-type polysilicon gate 116, the P-well 103 and the third N+ implantation region 110; the transistor T1 is formed by the second P+ implantation region 106, the N-well 102 and the P-well 1 03; transistor T2 is composed of N well 102, P well 103 and second N+ injection area 109; transistor T3 is composed of first P+ injection area 105, N well 102) and second P+ injection area 106; transistor T4 is composed of third P+ injection area 107, N well 102 and second P+ injection area 106; transistor T5 is composed of fifth N+ injection area 113, P well 103 and sixth N+ injection area 114; transistor T6 is composed of fifth N+ injection area 113, P well 103 and fourth N+ injection area 112.

[0017] like Figure 2 As shown, the collector of transistor T6, the collector of transistor T5, the source of transistor M1, the emitter of transistor T1, the emitter of transistor T3, the emitter of transistor T4 and one end of resistor Rn are all connected to the anode of the electrostatic surge integrated protection circuit; the substrate electrode of transistor M1, the base of transistor T1, the base of transistor T3, the base of transistor T4, the drain of transistor M2 and the collector of transistor T2 are all connected to the other end of resistor Rn.

[0018] One end of the resistor Rp, the emitter of the transistor T6, the emitter of the transistor T5, the emitter of the transistor T2, the drain of the transistor M2, the gate of the transistor M2, the collector of the transistor T3 and the collector of the transistor T4 are all connected to the cathode of the electrostatic surge integrated protection circuit; the base of the transistor T6, the base of the transistor T5, the drain of the transistor M1, the collector of the transistor T1, the base of the transistor T2 and the substrate electrode of the transistor M2 are all connected to the other end of the resistor Rp.

[0019] like Figure 3As shown, when the electrostatic surge stress acts between the anode and the cathode of the electrostatic surge integrated protection circuit, the resistor Rp and the transistor M1 form a first auxiliary trigger path, and the resistor Rn and the transistor M2 form a second auxiliary trigger path. The leakage current formed by the first auxiliary trigger path and the second auxiliary trigger path increases with the increase of the electrical stress, thereby increasing the voltage drop across the resistor Rp and the resistor Rn. When the voltage drop across the resistor Rp and the resistor Rn is greater than or equal to 0.7V, the first auxiliary trigger path and the second auxiliary trigger path will quickly trigger and turn on the electrostatic surge integrated protection circuit, thereby increasing the electrostatic surge electrical stress response speed and reducing the trigger voltage. The resistor Rp and the resistor Rn can also protect the gate oxides of the transistors M1 and M2, reducing the risk of breakdown damage to the gate oxide layer of the transistors.

[0020] like Figure 4 As shown, as the electrostatic surge stress further increases, when the voltage drop across the resistor Rp and the resistor Rn is greater than or equal to 0.7V, the emitter junctions of the transistors T6, T5, T2, T1, T3 and T4 will be forward-conducted, and the dual NPN transistor-triggered leakage circuit and the dual PNP transistor-triggered leakage circuit will amplify the current, thereby discharging the ESD current.

[0021] As the electrostatic surge stress continues to increase, under the current amplification effect of the dual NPN transistor trigger leakage circuit and the dual PNP transistor trigger leakage circuit, the base current and collector current of transistor T1 and transistor T2 further increase, and the current amplification capability of the electrostatic surge integrated protection circuit, driven by the dual bias SCR trigger leakage circuit, realizes the large surge current discharge function, thereby obtaining the electrostatic and surge integrated protection performance of gradual opening and orderly triggering.

[0022] Under the action of instantaneous high-frequency strong pulse electrostatic surge stress, the resistor string MOS trigger leakage circuit and the highly integrated surface shallow junction auxiliary trigger circuit composed of a dual NPN transistor trigger leakage circuit and a dual PNP transistor trigger leakage circuit can reduce the parasitic capacitance of the electrostatic surge integrated protection circuit, avoid the electrostatic surge integrated protection circuit from generating parasitic capacitance on the protection chip, cause signal attenuation of the high-frequency and high-speed interface chip, reduce the bit error rate, and solve the problems of insufficient electrostatic and surge protection capabilities of high-frequency and high-speed interface chips, and signal attenuation and performance degradation caused by traditional electrostatic and surge protection circuits.

[0023] This embodiment utilizes a resistor string MOS trigger leakage circuit and a dual transistor trigger leakage circuit to regulate the dual bias SCR trigger leakage mechanism to reduce the trigger voltage of the ESD / EOS integrated protection circuit, increase the opening speed, and achieve orderly discharge performance that can meet the different intensities of static electricity and surge electrical stress pulses, achieve small-area, high-voltage-resistant, and strong leakage current integrated protection against static electricity and surges, reduce parasitic capacitance, and thus enhance the electrostatic surge protection performance, system stability, and reliability of high-frequency and high-speed interface chips.

[0024] In addition to the above embodiments, the present invention may also have other implementation modes. Any technical solution formed by equivalent replacement or equivalent transformation falls within the protection scope required by the present invention.

Claims

1. An integrated electrostatic surge protection circuit suitable for high-frequency and high-speed interface chips, characterized in that: It includes a dual NPN transistor trigger leakage circuit, a dual PNP transistor trigger leakage circuit, a resistor string PMOS trigger leakage circuit, a resistor string NMOS trigger leakage circuit and a dual bias SCR trigger leakage circuit; The electrostatic surge integrated protection circuit is composed of a P-type substrate (100), a high-voltage N-well (101), an N-well (102), a P-well (103), a first N+ injection region (104), a first P+ injection region (105), a second P+ injection region (106), a third P+ injection region (107), a fourth P+ injection region (108), a second N+ injection region (109), a third N+ injection region (110), a fifth P+ injection region (111), a fourth N+ injection region (112), a fifth N+ injection region (113), a sixth N+ injection region (114), a first P-type polysilicon gate (115), and a second N-type polysilicon gate (116); The dual NPN transistor trigger leakage circuit is composed of transistor T5 and transistor T6; the dual PNP transistor trigger leakage circuit is composed of transistor T3 and transistor T4; the resistor string PMOS trigger leakage circuit is composed of resistor Rp and transistor M1; the resistor string NMOS trigger leakage circuit is composed of resistor Rn and transistor M2; the dual bias SCR trigger leakage circuit is composed of resistor Rp, resistor Rn, transistor T1 and transistor T2; The resistor Rn is a parasitic resistor formed by the first N+ injection region (104) and the N well (102); the resistor Rp is a parasitic resistor formed by the fifth P+ injection region (111) and the P well (103); The transistor M1 is composed of a third P+ injection region (107), a first P-type polysilicon gate (115), an N-well (102), and a fourth P+ injection region (108); the transistor M2 is composed of a second N+ injection region (109), a second N-type polysilicon gate (116), a P-well (103), and a third N+ injection region (110); the transistor T1 is composed of a second P+ injection region (106), an N-well (102), and a P-well (103); and the transistor T2 is composed of an N-well (102), a P-well (103), and a second N+ injection region (109); The transistor T3 is composed of a first P+ injection region (105), an N well (102) and a second P+ injection region (106); The transistor T4 is composed of a third P+ injection region (107), an N well (102) and a second P+ injection region (106); the transistor T5 is composed of a fifth N+ injection region (113), a P well (103) and a sixth N+ injection region (114); the transistor T6 is composed of a fifth N+ injection region (113), a P well (103) and a fourth N+ injection region (112); The collector of transistor T6, the collector of transistor T5, the source of transistor M1, the emitter of transistor T1, the emitter of transistor T3, the emitter of transistor T4 and one end of resistor Rn are all connected to the anode of the electrostatic surge integrated protection circuit; the substrate electrode of transistor M1, the base of transistor T1, the base of transistor T3, the base of transistor T4, the drain of transistor M2 and the collector of transistor T2 are all connected to the other end of resistor Rn; One end of the resistor Rp, the emitter of the transistor T6, the emitter of the transistor T5, the emitter of the transistor T2, the drain of the transistor M2, the gate of the transistor M2, the collector of the transistor T3 and the collector of the transistor T4 are all connected to the cathode of the electrostatic surge integrated protection circuit; the base of the transistor T6, the base of the transistor T5, the drain of the transistor M1, the collector of the transistor T1, the base of the transistor T2 and the substrate electrode of the transistor M2 are all connected to the other end of the resistor Rp.

2. The electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips according to claim 1, characterized in that: When electrostatic surge stress acts between the anode and cathode of the electrostatic surge integrated protection circuit, the resistor Rp and the transistor M1 form a first auxiliary trigger path, and the resistor Rn and the transistor M2 form a second auxiliary trigger path. The leakage current formed by the first auxiliary trigger path and the second auxiliary trigger path increases the voltage drop across the resistor Rp and the resistor Rn, thereby realizing the orderly triggering of the first auxiliary trigger path and the second auxiliary trigger path to turn on the electrostatic surge integrated protection circuit.

3. The electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips according to claim 2, characterized in that: When the voltage drop across the resistor Rp and the resistor Rn is greater than or equal to 0.7V, the emitter junctions of transistors T6, T5, T2, T1, T3 and T4 are forward-conducted, and the dual NPN transistor-triggered leakage circuit and the dual PNP transistor-triggered leakage circuit amplify the current, thereby enhancing the leakage capacity of the electrostatic surge integrated protection circuit.

4. The electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips according to claim 1, characterized in that: As the electrostatic surge stress continues to increase, the dual NPN transistor trigger leakage circuit and the dual PNP transistor trigger leakage circuit promote the increase of the base current and collector current of transistor T1 and transistor T2 through positive feedback, thereby further promoting the electrostatic surge integrated protection circuit to achieve a large surge current discharge function under the promotion of the dual bias SCR trigger leakage circuit.

5. The electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips according to claim 1, characterized in that: The resistor string PMOS trigger leakage circuit and the resistor string NMOS trigger leakage circuit, as well as the highly integrated surface shallow junction auxiliary trigger circuit composed of the dual NPN transistor trigger leakage circuit and the dual PNP transistor trigger leakage circuit, reduce the parasitic capacitance of the electrostatic surge integrated protection circuit, and avoid the electrostatic surge integrated protection circuit from causing signal interference or performance degradation to the protection chip.

6. The electrostatic surge integrated protection circuit suitable for high-frequency and high-speed interface chips according to claim 1, characterized in that: The high-voltage N-well (101) is replaced with an N-type buried layer.

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