Parallel control method, uninterruptible power supply system and computer readable storage medium

Abstract

The present invention provides a parallel control method, an uninterruptible power supply system and a computer-readable storage medium, wherein the uninterruptible power supply parallel system comprises a host and a plurality of slaves respectively composed of uninterruptible power supply units, each of which comprises a rectifier control chip and an inverter control chip respectively connected to the communication unit of the host, and the method comprises the following steps executed by the host: the inverter control chip sends a synchronous pulse signal, current sharing information and a discrete control signal to a communication bus through the communication unit of the host, and the synchronous pulse signal is used to make the slave perform phase tracking; when the rectifier control chip detects that the inverter control chip is abnormal, the rectifier control chip continues to send a synchronous pulse signal, current sharing information and a discrete control signal to the communication bus through the communication unit. The present invention can improve the stability of the operation of the uninterruptible power supply parallel system.

Description

Technical Field

[0001] The present invention relates to the field of uninterruptible power supply, and more specifically, to a parallel control method, an uninterruptible power supply system and a computer-readable storage medium. Background Art

[0002] There are generally two solutions for parallel connection of uninterruptible power supplies (UPS): analog parallel connection and digital parallel connection. Analog parallel connection is to realize parallel connection through analog quantity, which is costly and has poor reliability. Digital parallel connection is to realize transmission of control parameters such as current sharing through synchronous pulse + CAN bus, in which synchronous pulse is used for phase locking and CAN bus is used for transmitting current sharing information and discrete control signals. This solution is low in cost, has good reliability and is easy to expand parallel connection, and is the mainstream parallel connection solution at present.

[0003] To parallel the devices through the CAN bus, the uninterruptible power supply units in the parallel system need to compete to become a master, and the other uninterruptible power supply units in the parallel system are slaves. The master sends a synchronization pulse signal to the CAN bus according to the bypass, LBS and other tracking sources. After all slaves capture the synchronization pulse, they calculate the phase and track the phase of the synchronization pulse. The current sharing information and discrete control signals are transmitted on the CAN bus through the CAN bus, and both the master and the slave send them to the CAN bus.

[0004] However, in the above-mentioned uninterruptible power supply parallel system using digital parallel scheme, once the identity of the host is lost (such as the control chip of the host is abnormal, or the host suddenly loses power), the synchronization pulse signal and bus signal may be temporarily lost, and can only be restored after the new host identity is competed out. During the period of signal loss, the individual units in the parallel system are prone to mutual irrigation and other faults. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a parallel control method, an uninterruptible power supply system and a computer-readable storage medium to address the problem that the host identity is lost in the above-mentioned uninterruptible power supply system using digital parallel connection, which leads to mutual irrigation and other faults between single machines.

[0006] The technical solution of the present invention to solve the above technical problems is to provide a parallel control method, which is applied to an uninterruptible power supply parallel system, wherein the uninterruptible power supply parallel system includes a host and multiple slaves, wherein the host and the slaves are respectively composed of uninterruptible power supply units, each of which includes a communication unit, and the multiple uninterruptible power supply units are respectively connected to a communication bus through the communication units, and each of which includes a rectifier control chip and an inverter control chip respectively connected to the communication unit of the unit, and the method includes the following steps performed by the host:

[0007] The inverter control chip sends a synchronization pulse signal, current sharing information and a discrete control signal to the communication bus through the communication unit of the local machine, and the synchronization pulse signal is used to enable the slave machine to perform phase tracking;

[0008] When the rectifier control chip detects that the inverter control chip is abnormal, the rectifier control chip continues to send the synchronization pulse signal, the current sharing information and the discrete control signal to the communication bus through the communication unit.

[0009] As a further improvement of the present invention, the method comprises the following steps performed by the host:

[0010] The inverter control chip sends a heartbeat signal to the rectifier control chip in real time;

[0011] When the rectifier control chip does not receive a heartbeat signal sent by the inverter control chip within a preset time, it is determined that the inverter control chip is abnormal.

[0012] As a further improvement of the present invention, the method further comprises:

[0013] When the rectifier control chip of the host detects that the inverter control chip is abnormal, the rectifier control chip sends an inverter control chip abnormality signal to the communication bus through the communication unit, and the rectifier control chip stops sending a synchronization pulse signal to the communication bus after a first preset time;

[0014] After receiving the abnormal signal of the inverter control chip of the host on the communication bus, the multiple slaves compete for a new host, and the new host sends a synchronization pulse signal to the communication bus after a second preset time. The rectifier control chip of the original host exits the working state when it receives the synchronization pulse signal sent by the new host on the communication bus.

[0015] As a further improvement of the present invention, the method comprises the following steps:

[0016] The inverter control chip and the rectifier control chip of the host and each slave respectively generate priority data according to the inverter unit state, bypass state and the serial number of the local unit;

[0017] When the inverter control chip of the host is normal, the inverter control chip sends its own priority data to the communication bus through the communication chip; when the inverter control chip of the host is abnormal, the rectifier control chip of the host sends its own priority data to the communication bus through the communication unit of the host;

[0018] When the priority data of the host on the communication bus and the priority data of the slave machine meet a preset condition, the slave machine competes with other slave machines for the host.

[0019] As a further improvement of the present invention, the preset condition is: the segment where the priority data of the local machine is located is lower than the segment where the priority data of the host machine is located;

[0020] The method comprises: after a first preset time when the rectifier control chip of the host replaces the inverter control chip in sending the synchronization pulse signal to the communication bus, stopping sending the synchronization pulse signal to the communication bus;

[0021] After a second preset time when any slave competes to become a new master, the new master sends a synchronization pulse signal to the communication bus through the inverter control chip or the rectifier control chip.

[0022] As a further improvement of the present invention, the inverter control chip and the rectifier control chip of the host and each slave respectively generate priority data according to the inverter unit state, bypass state and the serial number of the local machine, including:

[0023] When the inverter unit of the machine is in the on state and the bypass is in the traceable state, the inverter control chip of the machine generates priority data in the first section, and the rectifier control chip of the machine generates priority data in the second section;

[0024] When the inverter unit of the machine is in a closed state or the bypass is in an untraceable state, the inverter control chip of the machine generates priority data in the second section, and the rectifier control chip of the machine generates priority data in the third section;

[0025] When the inverter unit of the machine is in a closed state and the bypass is in an untraceable state, the inverter control chip and the rectifier control chip of the machine both generate priority data in the fourth section.

[0026] As a further improvement of the present invention, competing with other slaves for the master includes:

[0027] Sending the priority data of the local machine to the communication bus through the communication unit of the local machine;

[0028] When the priority data of other slaves on the communication bus are greater than the priority data of this machine, a synchronization pulse signal is sent through the communication unit of this machine after a preset time.

[0029] As a further improvement of the present invention, the sending of the local priority data to the communication bus through the local communication unit includes: when the local inverter control chip is normal, the inverter control chip sends its own priority data to the communication bus through the communication chip; when the local inverter control chip is abnormal, the rectifier control chip sends its own priority data to the communication bus through the local communication unit.

[0030] The present invention also provides an uninterruptible power supply parallel system, comprising a host and multiple slaves, wherein the host and the slaves are respectively composed of uninterruptible power supply units, each of the uninterruptible power supply units comprises a communication unit, and the multiple uninterruptible power supply units are respectively connected to a communication bus through the communication units, each of the uninterruptible power supply units comprises a memory and a rectifier control chip, an inverter control chip and a memory respectively connected to the communication unit of the unit, the memory stores a computer program executable by the rectifier control chip and the inverter control chip, and the steps of the parallel control method described above are implemented when the rectifier control chip and the inverter control chip execute the computer program.

[0031] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the parallel control method described above are implemented.

[0032] The present invention has the following technical effects: the rectifier control chip of the host takes over the inverter control chip to send a synchronization pulse signal to the communication bus at the moment when the inverter control chip of the local machine is abnormal, thereby avoiding mutual irrigation and other faults of a single machine in the uninterruptible power supply parallel system during the period when the host identity is lost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flowchart of a parallel control method provided by an embodiment of the present invention.

[0034] Figure 2 It is a flow chart of confirming whether the inverter control chip of the host is abnormal in the parallel control method provided by an embodiment of the present invention.

[0035] Figure 3 It is a schematic diagram of a process of sending priority data to a communication bus by a host in a parallel control method provided by an embodiment of the present invention.

[0036] Figure 4 It is a flow chart of competing hosts in the parallel control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] like Figure 1 As shown, it is a flow chart of the parallel control method provided by the present invention, and the parallel control method can be applied to an uninterruptible power supply parallel system, and the uninterruptible power supply parallel system includes multiple uninterruptible power supply units, each of which includes a communication unit (such as a CAN communication unit), and the multiple uninterruptible power supply units are respectively connected to a communication bus (such as a CAN bus) through the communication unit, so as to realize the synchronous operation of each uninterruptible power supply unit. During the operation of the uninterruptible power supply parallel system, one of the uninterruptible power supply units constitutes a master, and the other uninterruptible power supplies constitute slaves.

[0039] In the above-mentioned uninterruptible power supply parallel system, each uninterruptible power supply unit also includes a rectifier unit, an inverter unit, a rectifier control chip (for example, a DSP can be used), an inverter control chip (for example, a DSP can be used), a DC bus, etc., wherein the rectifier unit can convert AC power into DC power under the control of the rectifier control chip and output it to the DC bus, and the inverter unit can convert the DC power on the DC bus into AC power of a preset frequency under the control of the inverter control chip and output it. The above-mentioned rectifier unit, inverter unit and other structures of the uninterruptible power supply unit can adopt the conventional solutions in the field, and will not be repeated here.

[0040] In each uninterruptible power supply unit of the uninterruptible power supply parallel system, the rectifier control chip and the inverter control chip are respectively connected to the communication unit of the unit. Specifically, the parallel control method of this embodiment includes the following steps executed by the host (specifically, it can be executed by the rectifier control chip and the inverter control chip):

[0041] Step S11: The inverter control chip sends a synchronization pulse signal, current sharing information and a discrete control signal to the communication bus through the communication unit of the local machine. The above-mentioned synchronization pulse signal is used to enable the slave machine to perform phase tracking, that is, after the slave machine receives the above-mentioned synchronization pulse signal from the communication bus through its communication unit, it calculates the corresponding phase and tracks the phase, thereby realizing the coordinated work of each slave machine and the host machine.

[0042] In this step, the inverter control chip can send a synchronization pulse signal to the communication bus according to a preset frequency. Specifically, the inverter control chip can generate a synchronization pulse signal according to the phase of the inverter unit output voltage, or generate a synchronization pulse signal according to other existing schemes in the field, and the transmission frequency of the current sharing information and the discrete control signal can be lower than the transmission frequency of the synchronization pulse signal, which will not be repeated here.

[0043] Step S12: The rectifier control chip determines whether the inverter control chip is abnormal (eg damaged), and executes step S13 if the inverter control chip is confirmed to be abnormal, otherwise returns to step S11, and the inverter control chip continues to send synchronization pulse signals to the communication bus.

[0044] When the inverter control chip is abnormal, it can no longer generate a normal synchronization pulse signal, and thus cannot send a synchronization pulse signal to the communication bus through the communication unit. Specifically, the execution frequency of this step is lower than the frequency at which the inverter control chip sends the synchronization pulse signal to the communication bus. For example, this step can be executed according to the smaller clock frequency of the rectifier control chip and the inverter control chip.

[0045] Step S13: The rectifier control chip continues to send synchronization pulse signals, current sharing information and discrete control signals to the communication bus through the communication unit. That is, when the inverter control chip of the host is abnormal, the rectifier control chip of the host replaces the inverter control chip to send synchronization pulse signals to the communication bus.

[0046] In this embodiment, the rectifier control chip of the host is phase-locked to the synchronization pulse in real time. Once the inverter control chip of the host is abnormal, the host identity can be quickly obtained and the synchronization pulse can continue to be sent out. Since the rectifier control chip and the inverter control chip can quickly indicate whether they are abnormal through the IO port, the speed is much better than the parallel communication method, so the rectifier control chip can quickly confirm whether the inverter is abnormal, and the speed is much faster than other single machines in the parallel system. Therefore, the rectifier control chip can quickly take over the communication bus and synchronization pulse in the parallel system from the abnormal inverter control chip, so as to achieve seamless switching, avoid the problem of temporary loss or abnormality of synchronization pulse when the inverter control chip of the host is abnormal (before other single machines compete for the host), thereby ensuring the stable operation of the parallel system.

[0047] When the inverter control chip of the slave machine is abnormal, the rectifier control chip of the slave machine can send current sharing information and discrete control signals to the communication bus through the communication chip of the local machine, or the slave machine directly exits the system.

[0048] like Figure 2 As shown, in one embodiment of the present invention, step S12, the rectifier control chip determines whether the inverter control chip is abnormal, which may include the following steps performed by the host:

[0049] Step S121: The inverter control chip sends a heartbeat signal to the rectifier control chip in real time. Specifically, the inverter control chip and the rectifier control chip can be connected through the IO port, and the heartbeat signal is sent through the IO port, and the inverter control chip can send the heartbeat signal according to its own clock frequency, thereby improving real-time performance.

[0050] Step S122: The rectifier control chip determines whether a normal heartbeat signal is received. When the rectifier control chip does not receive a normal heartbeat signal, step S123 is executed, otherwise, step S121 is returned. Specifically, when the rectifier control chip does not receive a heartbeat signal within a preset period, it is confirmed that a normal heartbeat signal is not received.

[0051] Step S123: The rectifier control chip confirms that the inverter control chip is abnormal.

[0052] Through the above method, the rectifier control chip of the host can quickly confirm whether the inverter control chip of the local machine is abnormal, so as to facilitate the subsequent replacement of the inverter control chip to send a synchronous pulse signal.

[0053] In one embodiment of the present invention, after the above step S13, it also includes: when the rectifier control chip of the host detects that the inverter control chip is abnormal, it sends the host inverter control chip abnormal signal to the communication bus through the communication unit, that is, broadcasts the information of the host inverter control chip abnormality on the communication bus, and the rectifier control chip stops sending the synchronization pulse signal to the communication bus after the first preset time; after receiving the host inverter control chip abnormal signal on the communication bus, the slave competes for a new host, and after the second preset time, the new host sends a synchronization pulse signal to the communication bus. The above first preset time and second preset time can be set as needed, and it is only necessary to ensure that after the new host is competed in the parallel system, the rectifier control chip of the original host exits the working state.

[0054] The above method can perfectly solve the problem of temporary loss or abnormality of the synchronization pulse signal after the inverter control chip of the host is abnormal, thereby ensuring the stable operation of the parallel system. At the same time, after receiving the abnormal information of the inverter control chip of the host, the slave clears the relevant information of the inverter control chip of the host to avoid control abnormality caused by erroneous parallel information.

[0055] like Figure 3 As shown, in one embodiment of the present invention, the parallel control method further includes the following steps performed by the host:

[0056] Step S14: the inverter control chip and the rectifier control chip generate priority data according to the inverter unit state, bypass state and the serial number of the local unit.

[0057] In this step, when the inverter unit of the machine is in the on state and the bypass is in the traceable state, the inverter control chip of the machine generates priority data in the first section, and the rectifier control chip of the machine generates priority data in the second section; when the inverter unit of the machine is in the off state or the bypass is in the untraceable state, the inverter control chip of the machine generates priority data in the second section, and the rectifier control chip of the machine generates priority data in the third section; when the inverter unit of the machine is in the off state and the bypass is in the untraceable state, the inverter control chip and the rectifier control chip of the machine both generate priority data in the fourth section.

[0058] For example, the priority data of the inverter control chip can be generated according to the state S_A of the inverter unit of the local machine (S_A=1 when on, S_A=0 when half off), the bypass state S_B (S_B=1 if bypass can be tracked, otherwise S_B=0), and the machine number of the local machine (N, such as the serial number in the system). For example: if S_A and S_B are both 1, the priority of the inverter control chip is N+1; if one of S_A and S_B is 0 and the other is 1, the priority of the inverter control chip is N+2+M, where M is the maximum number of parallel machines allowed in the system; if S_A and S_B are both 0, it does not participate in the parallel competition, that is, the priority is set to infinity. The priority of the rectifier control chip is (the priority value of the inverter control chip of the local machine + 2+M). If the uninterruptible power supply parallel system includes 8 single units, the inverter unit in the 1# single unit is turned on and the bypass cannot be tracked, the priority of the inverter control chip is 11 (1+2+8) (M is 8), and the priority of the rectifier control chip in the 1# single unit is 21 (11+2+8). At the same time, 1 to N+1 are defined as priority level 1, N+2 to N+2+M as priority level 2, and N+3+M to N+3+2M as priority level 3.

[0059] Step S15: Determine whether the inverter control chip is normal. If the inverter control chip is normal, execute step S16; otherwise, execute step S17. Figure 2 The method shown.

[0060] Step S16: The inverter control chip sends its own priority data to the communication bus through the communication chip. Specifically, the priority data can be packaged into a synchronous pulse signal. Of course, in practical applications, the priority data can also be uploaded to the communication bus as a discrete control signal.

[0061] Step S17: The rectifier control chip sends its own priority data to the communication bus through the communication unit of the local chip. Similarly, the priority data can be packaged into a synchronous pulse signal, or uploaded to the communication bus as a discrete control signal.

[0062] like Figure 4As shown, in one embodiment of the present invention, the parallel control method further includes the following steps performed by the slave:

[0063] Step S21: The inverter control chip and the rectifier control chip generate priority data according to the inverter unit state, the bypass state and the serial number of the local unit. The specific method of generating priority data can refer to the above step S14.

[0064] Step S22: Determine whether the priority data of the host in the communication bus (sent by the host's inverter control unit or rectifier control unit) and the priority data of the local machine meet the preset conditions. If the priority data of the host and the priority data of the local machine meet the preset conditions, execute step S23, otherwise continue to execute step S21.

[0065] Specifically, in this step, when the priority data of the local machine is in a lower segment than the priority data of the host machine, it is confirmed that the priority data of the host machine and the priority data of the local machine meet the preset conditions. In other words, even if the priority value is small in the same segment, the host machine does not switch to avoid frequent switching of the host machine.

[0066] Step S23: compete with other slaves for the master.

[0067] If the host is 3# single machine, and its priority level is 1, that is, the priority data of 3# single machine is 4 (3+1), even if the priority data of 1# single machine is 2 (1+1) and the priority data of 2# single machine is 3 (2+1), which are both lower than the priority data of 3# single machine, but because 3# single machine has become the host and sent a flag to the communication bus that there is a host in the parallel system, the parallel system maintains the host as 3# single machine unchanged. When the inverter control chip of 3# single machine fails, its rectifier control chip continues to send synchronization pulse signals and corresponding priority data to the communication bus. Since the section where the priority data of the rectifier control chip of 3# single machine is located is higher than the section where the priority data of 1# and 2# single machines are located, 1# and 2# single machines compete for the host.

[0068] In one embodiment of the present invention, competing with other slaves for the master may include the following steps: sending the priority data of the local machine to the communication bus through the communication unit of the local machine, and specifically sending the priority data of the local machine in the form of a discrete control signal; when the priority data of other slaves on the communication bus are greater than the priority data of the local machine, sending a synchronization pulse signal through the communication unit of the local machine after a second preset time (for example, one synchronization pulse signal cycle or several synchronization pulse signal cycles). Accordingly, the rectifier control chip of the original host stops sending the synchronization pulse signal to the communication bus after the first preset time after replacing its inverter control chip to send the synchronization pulse signal to the communication bus, so as to avoid the existence of two synchronization pulse signals from different single machines in the communication bus.

[0069] When the priority data of this machine is sent to the communication bus through the communication unit of this machine, if the inverter control chip of this machine is normal, the inverter control chip will send its own priority data to the communication bus through the communication chip (the rectifier control chip does not send its priority data at this time); when the inverter control chip of this machine is abnormal, the rectifier control chip of this machine will send its own priority data to the communication bus through the communication unit of this machine.

[0070] The present invention also provides an uninterruptible power supply parallel system, comprising a host and multiple slaves, wherein the host and the slaves are respectively composed of uninterruptible power supply units, each of the uninterruptible power supply units includes a communication unit, and the multiple uninterruptible power supply units are respectively connected to a communication bus through the communication units, each of the uninterruptible power supply units includes a memory and a rectifier control chip, an inverter control chip and a memory respectively connected to the communication unit of the unit (the memory may be independent of the rectifier control chip and the inverter control chip, or the memory may also be composed of storage units respectively integrated into the rectifier control chip and the inverter control chip), the memory stores a computer program executable by the rectifier control chip and the inverter control chip, and the steps of the parallel control method described above are implemented when the rectifier control chip and the inverter control chip execute the computer program.

[0071] The uninterruptible power supply parallel system in this embodiment is similar to the above Figure 1-4 The parallel control method in the corresponding embodiment belongs to the same concept, and its specific implementation process is detailed in the corresponding method embodiment, and the technical features in the method embodiment are applicable to the embodiment of the uninterruptible power supply parallel system, which will not be repeated here.

[0072] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the parallel control method described above are implemented.

[0073] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the parallel control method described above are implemented.

[0074] The computer-readable storage medium in this embodiment is the same as the above Figure 1-4 The parallel control method in the corresponding embodiment belongs to the same concept, and its specific implementation process is detailed in the corresponding method embodiment, and the technical features in the method embodiment are applicable in this storage medium embodiment, which will not be repeated here.

[0075] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0076] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed. The functional units and modules in the embodiments can be integrated into a processor, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0077] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0079] In the embodiments provided in the present application, it should be understood that the disclosed parallel control method and uninterruptible power supply parallel system can be implemented in other ways. For example, the uninterruptible power supply parallel system embodiment described above is only illustrative.

[0080] In addition, each functional unit in each embodiment of the present application may be integrated into one processor, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0081] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or interface switching device that can carry the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0082] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A parallel control method, applied to an uninterruptible power supply parallel system, wherein the uninterruptible power supply parallel system comprises a host and a plurality of slaves, wherein the host and the slaves are respectively composed of uninterruptible power supply units, each of the uninterruptible power supply units comprises a communication unit, and the plurality of the uninterruptible power supply units are respectively connected to a communication bus through the communication units, characterized in that: Each of the uninterruptible power supply units includes a rectifier control chip and an inverter control chip respectively connected to the communication unit of the unit, and the method includes the following steps performed by the host: The inverter control chip sends a synchronous pulse signal, current sharing information and a discrete control signal to the communication bus through the communication unit of the local machine, and the synchronous pulse signal is used to enable the slave machine to perform phase tracking; When the rectifier control chip detects that the inverter control chip is abnormal, the rectifier control chip continues to send the synchronization pulse signal, the current sharing information and the discrete control signal to the communication bus through the communication unit.

2. The parallel control method according to claim 1, characterized in that: The method comprises the following steps performed by the host: The inverter control chip sends a heartbeat signal to the rectifier control chip in real time; When the rectifier control chip does not receive a heartbeat signal sent by the inverter control chip within a preset time, it is determined that the inverter control chip is abnormal.

3. The parallel control method according to claim 1, characterized in that: The method further comprises: When the rectifier control chip of the host detects that the inverter control chip is abnormal, the rectifier control chip sends an inverter control chip abnormality signal to the communication bus through the communication unit, and the rectifier control chip stops sending a synchronization pulse signal to the communication bus after a first preset time; After receiving the abnormal signal of the inverter control chip of the master of the communication bus, the multiple slaves compete for a new master, and the new master sends a synchronization pulse signal to the communication bus after a second preset time.

4. The parallel control method according to claim 1, characterized in that: The method comprises the following steps: The inverter control chip and the rectifier control chip of the host and each slave respectively generate priority data according to the inverter unit state, bypass state and the serial number of the local unit; When the inverter control chip of the host is normal, the inverter control chip sends its own priority data to the communication bus through the communication chip; when the inverter control chip of the host is abnormal, the rectifier control chip of the host sends its own priority data to the communication bus through the communication unit of the host; When the priority data of the host on the communication bus and the priority data of the slave machine meet a preset condition, the slave machine competes with other slave machines for the host.

5. The parallel control method according to claim 4, characterized in that: The preset condition is: the section where the priority data of the local machine is located is lower than the section where the priority data of the host machine is located; The method comprises: after a first preset time when the rectifier control chip of the host replaces the inverter control chip in sending the synchronization pulse signal to the communication bus, stopping sending the synchronization pulse signal to the communication bus; After a second preset time when any slave competes to become a new master, the new master sends a synchronization pulse signal to the communication bus through the inverter control chip or the rectifier control chip.

6. The parallel control method according to claim 5, characterized in that: The inverter control chip and the rectifier control chip of the host and each slave respectively generate priority data according to the inverter unit state, bypass state and the serial number of the local unit, including: When the inverter unit of the machine is in the on state and the bypass is in the traceable state, the inverter control chip of the machine generates priority data in the first section, and the rectifier control chip of the machine generates priority data in the second section; When the inverter unit of the machine is in a closed state or the bypass is in an untraceable state, the inverter control chip of the machine generates priority data in the second section, and the rectifier control chip of the machine generates priority data in the third section; When the inverter unit of the machine is in a closed state and the bypass is in an untraceable state, the inverter control chip and the rectifier control chip of the machine both generate priority data in the fourth section.

7. The parallel control method according to claim 6, characterized in that: Compete with other slaves for the master, including: Sending the priority data of the local machine to the communication bus through the communication unit of the local machine; When the priority data of other slaves on the communication bus are greater than the priority data of this machine, a synchronization pulse signal is sent through the communication unit of this machine after a preset time.

8. The parallel control method according to claim 6, characterized in that: The sending of the local priority data to the communication bus through the local communication unit includes: when the local inverter control chip is normal, the inverter control chip sends its own priority data to the communication bus through the communication chip; when the local inverter control chip is abnormal, the rectifier control chip sends its own priority data to the communication bus through the local communication unit.

9. An uninterruptible power supply parallel system, comprising a host and a plurality of slaves, wherein the host and the slaves are respectively composed of uninterruptible power supply units, each of the uninterruptible power supply units comprises a communication unit, and the plurality of the uninterruptible power supply units are respectively connected to a communication bus via the communication units, characterized in that: Each of the uninterruptible power supply units includes a memory and a rectifier control chip, an inverter control chip and a memory respectively connected to the communication unit of the unit, wherein the memory stores a computer program executable by the rectifier control chip and the inverter control chip, and when the rectifier control chip and the inverter control chip execute the computer program, the steps of the parallel control method as described in any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the parallel control method according to any one of claims 1 to 8 are implemented.

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